80458b6222
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18565 a1c6a512-1295-4272-9138-f99709370657
116 lines
6.9 KiB
C
116 lines
6.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 Vitja Makarov
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef USB_TCC7XX_H
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#define USB_TCC7XX_H
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#define MMR_REG16(base, x) (*(volatile unsigned short *) ((base) + (x)))
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/* USB PHY registers */
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#define TCC7xx_USB_PHY_CFG MMR_REG16(USB_BASE, 0xc4)
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#define TCC7xx_USB_PHY_CFG_XSEL (1<<13) /* FS/HS Transceiver enable */
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#define TCC7xx_USB_PHY_CFG_DWS (1<<6) /* Host mode */
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#define TCC7xx_USB_PHY_XO (1<<5) /* Enable XO_OUT */
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#define TCC7xx_USB_PHY_CKSEL_12 0
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#define TCC7xx_USB_PHY_CKSEL_24 1
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#define TCC7xx_USB_PHY_CKSEL_48 2
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/* USB 2.0 device registers */
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#define TCC7xx_USB_INDEX MMR_REG16(USB_BASE, 0x00) /* Endpoint Index register */
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#define TCC7xx_USB_EPIF MMR_REG16(USB_BASE, 0x04) /* Endpoint interrupt flag register */
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#define TCC7xx_USB_EPIE MMR_REG16(USB_BASE, 0x08) /* Endpoint interrupt enable register */
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#define TCC7xx_USB_FUNC MMR_REG16(USB_BASE, 0x0c) /* Function address register */
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#define TCC7xx_USB_EP_DIR MMR_REG16(USB_BASE, 0x14) /* Endpoint direction register */
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#define TCC7xx_USB_TST MMR_REG16(USB_BASE, 0x14) /* Test registerregister */
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#define TCC7xx_USB_SYS_STAT MMR_REG16(USB_BASE, 0x1c) /* System status register */
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#define TCC7xx_USB_SYS_STAT_RESET (1<<0) /* Host forced reced */
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#define TCC7xx_USB_SYS_STAT_SUSPEND (1<<1) /* Host forced suspend */
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#define TCC7xx_USB_SYS_STAT_RESUME (1<<2) /* Host forced resume */
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#define TCC7xx_USB_SYS_STAT_HIGH (1<<4) /* High speed */
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#define TCC7xx_USB_SYS_STAT_SPD_END (1<<6) /* Speed detection end */
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#define TCC7xx_USB_SYS_STAT_VBON (1<<8)
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#define TCC7xx_USB_SYS_STAT_VBOF (1<<9)
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#define TCC7xx_USB_SYS_STAT_EOERR (1<<10) /* overrun error */
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#define TCC7xx_USB_SYS_STAT_DCERR (1<<11) /* Data CRC error */
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#define TCC7xx_USB_SYS_STAT_TCERR (1<<12) /* Token CRC error */
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#define TCC7xx_USB_SYS_STAT_BSERR (1<<13) /* Bit-stuff error */
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#define TCC7xx_USB_SYS_STAT_TMERR (1<<14) /* Timeout error */
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#define TCC7xx_USB_SYS_STAT_BAERR (1<<15) /* Byte align error */
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#define TCC7xx_USB_SYS_STAT_ERRORS (TCC7xx_USB_SYS_STAT_EOERR | \
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TCC7xx_USB_SYS_STAT_DCERR | \
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TCC7xx_USB_SYS_STAT_TCERR | \
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TCC7xx_USB_SYS_STAT_BSERR | \
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TCC7xx_USB_SYS_STAT_TMERR | \
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TCC7xx_USB_SYS_STAT_BAERR)
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#define TCC7xx_USB_SYS_CTRL MMR_REG16(USB_BASE, 0x20) /* System control register */
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#define TCC7xx_USB_SYS_CTRL_RESET (1<<0) /* Reset enable */
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#define TCC7xx_USB_SYS_CTRL_SUSPEND (1<<1) /* Suspend enable */
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#define TCC7xx_USB_SYS_CTRL_RESUME (1<<2) /* Resume enable */
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#define TCC7xx_USB_SYS_CTRL_IPS (1<<4) /* Interrupt polarity */
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#define TCC7xx_USB_SYS_CTRL_RFRE (1<<5) /* Reverse read data enable */
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#define TCC7xx_USB_SYS_CTRL_SPDEN (1<<6) /* Speed detection interrupt enable */
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#define TCC7xx_USB_SYS_CTRL_BUS16 (1<<7) /* Select bus width 8/16 */
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#define TCC7xx_USB_SYS_CTRL_EIEN (1<<8) /* Error interrupt enable */
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#define TCC7xx_USB_SYS_CTRL_RWDE (1<<9) /* Reverse write data enable */
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#define TCC7xx_USB_SYS_CTRL_VBONE (1<<10) /* VBus On enable */
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#define TCC7xx_USB_SYS_CTRL_VBOFE (1<<11) /* VBus Off enable */
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#define TCC7xx_USB_SYS_CTRL_DUAL (1<<12) /* Dual interrupt enable*/
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#define TCC7xx_USB_SYS_CTRL_DMAZ (1<<14) /* DMA total count zero int */
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#define TCC7xx_USB_EP0_STAT MMR_REG16(USB_BASE, 0x24) /* EP0 status register */
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#define TCC7xx_USB_EP0_CTRL MMR_REG16(USB_BASE, 0x28) /* EP0 control register */
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#define TCC7xx_USB_EP0_BUF MMR_REG16(USB_BASE, 0x60) /* EP0 buffer register */
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#define TCC7xx_USB_EP1_BUF MMR_REG16(USB_BASE, 0x64) /* EP1 buffer register */
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#define TCC7xx_USB_EP2_BUF MMR_REG16(USB_BASE, 0x68) /* EP2 buffer register */
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#define TCC7xx_USB_EP3_BUF MMR_REG16(USB_BASE, 0x6c) /* EP3 buffer register */
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/* Indexed registers, write endpoint number to TCC7xx_USB_INDEX */
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#define TCC7xx_USB_EP_STAT MMR_REG16(USB_BASE, 0x2c) /* EP status register */
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#define TCC7xx_USP_EP_STAT_RPS (1 << 0) /* Packet received */
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#define TCC7xx_USP_EP_STAT_TPS (1 << 1) /* Packet transmited */
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#define TCC7xx_USP_EP_STAT_LWO (1 << 4) /* Last word odd */
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#define TCC7xx_USB_EP_CTRL MMR_REG16(USB_BASE, 0x30) /* EP control register */
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#define TCC7xx_USB_EP_CTRL_TZLS (1 << 0) /* TX Zero Length Set */
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#define TCC7xx_USB_EP_CTRL_ESS (1 << 1) /* Endpoint Stall Set */
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#define TCC7xx_USB_EP_CTRL_CDP (1 << 2) /* Clear Data PID */
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#define TCC7xx_USB_EP_CTRL_TTE (1 << 5) /* TX Toggle Enable */
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#define TCC7xx_USB_EP_CTRL_FLUSH (1 << 6) /* Flush FIFO */
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#define TCC7xx_USB_EP_CTRL_DUEN (1 << 7) /* Dual FIFO Mode */
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#define TCC7xx_USB_EP_CTRL_IME (1 << 8) /* ISO Mode */
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#define TCC7xx_USB_EP_CTRL_OUTHD (1 << 11) /* OUT Packet Hold */
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#define TCC7xx_USB_EP_CTRL_INHLD (1 << 12) /* IN Packet Hold */
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#define TCC7xx_USB_EP_BRCR MMR_REG16(USB_BASE, 0x34) /* EP byte read count register */
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#define TCC7xx_USB_EP_BWCR MMR_REG16(USB_BASE, 0x38) /* EP byte write count register */
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#define TCC7xx_USB_EP_MAXP MMR_REG16(USB_BASE, 0x3c) /* EP max packet register */
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#define TCC7xx_USB_EP_DMA_CTRL MMR_REG16(USB_BASE, 0x40) /* EP DMA control register */
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#define TCC7xx_USB_EP_DMA_TCNTR MMR_REG16(USB_BASE, 0x44) /* EP DMA transfer counter register */
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#define TCC7xx_USB_EP_DMA_FCNTR MMR_REG16(USB_BASE, 0x48) /* EP DMA fifo counter register */
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#define TCC7xx_USB_EP_DMA_TTCNTR1 MMR_REG16(USB_BASE, 0x4c) /* EP DMA total trasfer counter1 register */
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#define TCC7xx_USB_EP_DMA_TTCNTR2 MMR_REG16(USB_BASE, 0x50) /* EP DMA total trasfer counter2 register */
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#define TCC7xx_USB_EP_DMA_ADDR1 MMR_REG16(USB_BASE, 0xa0) /* EP DMA MCU addr1 register */
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#define TCC7xx_USB_EP_DMA_ADDR2 MMR_REG16(USB_BASE, 0xa4) /* EP DMA MCU addr2 register */
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#define TCC7xx_USB_EP_DMA_STAT MMR_REG16(USB_BASE, 0xc0) /* EP DMA Transfer Status register */
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#define TCC7xx_USB_DELAY_CTRL MMR_REG16(USB_BASE, 0x80) /* Delay control register */
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#endif /* USB_TCC7XX_H */
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