b30ca8ca5a
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16089 a1c6a512-1295-4272-9138-f99709370657
349 lines
9.9 KiB
ArmAsm
349 lines
9.9 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Jens Arnold
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* Based on the work of Alan Korr and Jörg Hohensohn
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#define LCDR (PBDR_ADDR+1)
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#define LCD_SD 1 /* PB0 = 1 --- 0001 */
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#define LCD_SC 2 /* PB1 = 1 --- 0010 */
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#define LCD_DS 4 /* PB2 = 1 --- 0100 */
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#define LCD_CS 8 /* PB3 = 1 --- 1000 */
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/*
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* About /CS,DS,SC,SD
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* ------------------
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*
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* LCD on JBP and JBR uses a SPI protocol to receive orders (SDA and SCK lines)
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*
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* - /CS -> Chip Selection line :
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* 0 : LCD chipset is activated.
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* - DS -> Data Selection line, latched at the rising edge
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* of the 8th serial clock (*) :
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* 0 : instruction register,
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* 1 : data register;
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* - SC -> Serial Clock line (SDA).
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* - SD -> Serial Data line (SCK), latched at the rising edge
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* of each serial clock (*).
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*
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* _ _
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* /CS \ /
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* \______________________________________________________/
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* _____ ____ ____ ____ ____ ____ ____ ____ ____ _____
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* SD \/ D7 \/ D6 \/ D5 \/ D4 \/ D3 \/ D2 \/ D1 \/ D0 \/
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* _____/\____/\____/\____/\____/\____/\____/\____/\____/\_____
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*
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* _____ _ _ _ _ _ _ _ ________
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* SC \ * \ * \ * \ * \ * \ * \ * \ *
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* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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* _ _________________________________________________________
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* DS \/
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* _/\_________________________________________________________
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*
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*/
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.section .icode,"ax",@progbits
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.align 2
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.global _lcd_write_command
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.type _lcd_write_command,@function
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/* Write a command byte to the lcd controller
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*
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* Arguments:
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* r4 - data byte (int)
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*
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* Register usage:
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* r0 - scratch
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* r1 - data byte (copied)
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* r2 - precalculated port value (CS, DS and SC low, SD high),
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* negated (neg)!
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* r3 - lcd port address
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* r5 - 1 (byte count for reuse of the loop in _lcd_write_data)
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*/
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_lcd_write_command:
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mov.l .lcdr, r3 /* put lcd data port address in r3 */
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mov r4, r1 /* copy data byte to r1 */
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/* This code will fail if an interrupt changes the contents of PBDRL.
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* If so, we must disable the interrupt here. */
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mov.b @r3, r0 /* r0 = PBDRL */
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mov #0, r5 /* fake end address - stop after first iteration */
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or #(LCD_SD), r0 /* r0 |= LCD_SD */
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and #(~(LCD_CS|LCD_DS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_DS|LCD_SC) */
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bra .single_transfer /* jump into the transfer loop */
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neg r0, r2 /* r2 = 0 - r0 */
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.align 2
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.global _lcd_write_data
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.type _lcd_write_data,@function
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/* A high performance function to write data to the display,
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* one or multiple bytes.
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*
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* Arguments:
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* r4 - data address
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* r5 - byte count
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*
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* Register usage:
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* r0 - scratch
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* r1 - current data byte
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* r2 - precalculated port value (CS and SC low, DS and SD high),
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* negated (neg)!
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* r3 - lcd port address
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*/
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_lcd_write_data:
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mov.l .lcdr, r3 /* put lcd data port address in r3 */
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add r4, r5 /* end address */
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/* This code will fail if an interrupt changes the contents of PBDRL.
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* If so, we must disable the interrupt here. If disabling interrupts
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* for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
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* recorders)is undesirable, the loop has to be rewritten to
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* disable/precalculate/transfer/enable for each iteration. However,
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* this would significantly decrease performance. */
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mov.b @r3, r0 /* r0 = PBDRL */
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or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
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and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
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neg r0, r2 /* r2 = 0 - r0 */
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/* loop exploits that SD is on bit 0 for recorders and Ondios */
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.align 2
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.multi_transfer:
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mov.b @r4+, r1 /* load data byte from memory */
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nop
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.single_transfer:
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shll16 r1 /* shift data to most significant byte */
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shll8 r1
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not r1, r1 /* and invert for use with negc */
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shll r1 /* shift the MSB into carry */
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negc r2, r0 /* carry to SD, SC low */
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shll r1 /* next shift here for alignment */
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mov.b r0, @r3 /* set data to port */
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or #(LCD_SC), r0 /* rise SC (independent of SD level) */
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mov.b r0, @r3 /* set to port */
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negc r2, r0
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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shll r1
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negc r2, r0
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shll r1
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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negc r2, r0
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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shll r1
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negc r2, r0
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shll r1
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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negc r2, r0
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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shll r1
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negc r2, r0
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shll r1
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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negc r2, r0
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mov.b r0, @r3
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or #(LCD_SC), r0
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mov.b r0, @r3
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cmp/hi r4, r5 /* some blocks left? */
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bt .multi_transfer
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or #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0 /* restore port */
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rts
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mov.b r0, @r3
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/* This is the place to reenable the interrupts, if we have disabled
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* them. See above. */
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.align 2
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.global _lcd_grey_data
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.type _lcd_grey_data,@function
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/* A high performance function to write grey phase data to the display,
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* one or multiple pixels.
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*
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* Arguments:
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* r4 - pixel value data address
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* r5 - pixel phase data address
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* r6 - pixel block count
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*
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* Register usage:
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* r0 - scratch / phase signs mask
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* r1 - scratch
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* r2 - precalculated port value (CS and SC low, DS and SD high),
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* negated (neg)!
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* r3 - lcd port address
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* r4 - current value address
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* r5 - current phase address
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* r6 - end address
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* r7/r8 - current/next block of phases (alternating)
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* r9/r10 - current blocks of values
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* r11 - 0x00000080 \
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* r12 - 0x00008000 > for phase sign check
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* r13 - 0x00800000 /
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*/
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_lcd_grey_data:
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mov.l r8, @-r15 /* save r8 */
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mov.l r9, @-r15 /* save r9 */
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mov.l r10, @-r15 /* save r10 */
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shll2 r6 /* v */
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mov.l r11, @-r15 /* save r11 */
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shll r6 /* r6 *= 8; (8 pixels per block) */
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mov.l .lcdr, r3 /* put lcd data port address in r3 */
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add r4, r6 /* end address */
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/* This code will fail if an interrupt changes the contents of PBDRL.
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* If so, we must disable the interrupt here. If disabling interrupts
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* for a long time is undesirable, the loop has to be rewritten to
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* disable/precalculate/transfer/enable for each iteration. However,
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* this would significantly decrease performance. */
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mov.b @r3, r0 /* r0 = PBDRL */
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or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
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mov.l r12, @-r15 /* save r12 */
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and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
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mov.l r13, @-r15 /* save r13 */
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neg r0, r2 /* r2 = 0 - r0 */
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/* loop exploits that SD is on bit 0 for recorders and Ondios */
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mov.w .ptest, r11
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swap.b r11, r12
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mov.l @r5, r7
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swap.w r11, r13
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mov.l .pmask, r0
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.greyloop:
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cmp/pz r7
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mov.l @r4+, r9
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r13, r7
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mov.l @r4+, r10
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r12, r7
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mov.l @(4,r5), r8
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r11, r7
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or r0, r7
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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cmp/pz r8
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sub r9, r7
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r13, r8
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mov.l r7, @r5
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r12, r8
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mov.l @(8,r5), r7
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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tst r11, r8
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or r0, r8
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negc r2, r1
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mov.b r1, @r3
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add #(LCD_SC), r1
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mov.b r1, @r3
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sub r10, r8
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mov.l r8, @(4,r5)
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add #8, r5
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cmp/hi r4, r6
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bt .greyloop
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mov.l @r15+, r13 /* restore r13 */
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mov #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0
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mov.l @r15+, r12 /* restore r12 */
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or r0, r1 /* restore port */
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mov.l @r15+, r11 /* restore r11 */
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mov.l @r15+, r10 /* restore r10 */
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mov.l @r15+, r9 /* restore r9 */
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mov.l @r15+, r8 /* restore r8 */
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rts
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mov.b r1, @r3
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/* This is the place to reenable the interrupts, if we have disabled
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* them. See above. */
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.ptest:
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.short 0x0080
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.align 2
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.lcdr:
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.long LCDR
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.pmask:
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.long 0x80808080
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