dea2434f3c
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5749 a1c6a512-1295-4272-9138-f99709370657
839 lines
26 KiB
C
839 lines
26 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include "config.h"
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#include <stdbool.h>
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#include "lcd.h"
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#include "font.h"
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#include "system.h"
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#if CONFIG_CPU == TCC730
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void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
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void ddma_wait_idle(void)
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{
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do {
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} while ((DDMACOM & 3) != 0);
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}
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void ddma_transfer(int dir, int mem, long intAddr, long extAddr, int num) {
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int irq = set_irq_level(1);
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ddma_wait_idle();
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long externalAddress = (long) extAddr;
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long internalAddress = (long) intAddr;
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/* HW wants those two in word units. */
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num /= 2;
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externalAddress /= 2;
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DDMACFG = (dir << 1) | (mem << 2);
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DDMAIADR = internalAddress;
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DDMAEADR = externalAddress;
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DDMANUM = num;
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DDMACOM |= 0x4; /* start */
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ddma_wait_idle(); /* wait for completion */
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set_irq_level(irq);
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}
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/* Some linker-defined symbols */
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extern int icodecopy;
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extern int icodesize;
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extern int icodestart;
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/* called by crt0 */
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void system_init(void)
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{
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/* Disable watchdog */
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WDTEN = 0xA5;
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/* Setup the CPU */
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/* PLL0 (cpu osc. frequency) */
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#if 0
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PLL0DATA = 0xf98;
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PLL0CON = 0x1; /* activate */
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do {
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asm "nop";
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} while ((PLL0CON & 0x2) == 0); /* wait for stabilization */
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PLL0CON = 0x5; /* use as CPU clock */
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#endif
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/*******************
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* configure S(D)RAM
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*/
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/************************
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* Copy .icode section to icram
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*/
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ddma_transfer(0, 0, 0x40, (long)&icodecopy, (int)&icodesize);
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/***************************
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* Interrupt mask
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*/
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/* interrupt priorities ? */
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IMR0 = 0;
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IMR1 = 0;
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/* IRQ0 BT INT */
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/* IRQ1 RTC INT */
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/* IRQ2 TA INT */
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/* IRQ3 TAOV INT */
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/* IRQ4 TB INT */
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/* IRQ5 TBOV INT */
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/* IRQ6 TC INT */
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/* IRQ7 TCOV INT */
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/* IRQ8 USB INT */
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/* IRQ9 PPIC INT */
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/* IRQ10 UART_Rx/UART_Err/ UART_tx INT */
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/* IRQ11 IIC INT */
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/* IRQ12 SIO INT */
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/* IRQ13 IIS0 INT */
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/* IRQ14 IIS1 INT */
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/* IRQ15 <20> */
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}
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#elif CONFIG_CPU == MCF5249
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIE"))) void name (void);
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static const char* const irqname[] = {
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"", "", "AccessErr","AddrErr","IllInstr", "", "","",
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"PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
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"","","","","","","","",
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"Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
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"Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
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"Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
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"SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
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"DMA2","DMA3","QSPI","","","","","",
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"PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
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"IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
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"AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
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"PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
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"IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
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"UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
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"IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
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"IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
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"GPIO0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
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"","","","","","","","SOFTINT0",
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"SOFTINT1","SOFTINT2","SOFTINT3","",
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"","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
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"CDROMNEWBLK","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","",""
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};
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default_interrupt (TRAP0); /* Trap #0 */
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default_interrupt (TRAP1); /* Trap #1 */
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default_interrupt (TRAP2); /* Trap #2 */
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default_interrupt (TRAP3); /* Trap #3 */
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default_interrupt (TRAP4); /* Trap #4 */
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default_interrupt (TRAP5); /* Trap #5 */
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default_interrupt (TRAP6); /* Trap #6 */
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default_interrupt (TRAP7); /* Trap #7 */
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default_interrupt (TRAP8); /* Trap #8 */
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default_interrupt (TRAP9); /* Trap #9 */
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default_interrupt (TRAP10); /* Trap #10 */
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default_interrupt (TRAP11); /* Trap #11 */
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default_interrupt (TRAP12); /* Trap #12 */
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default_interrupt (TRAP13); /* Trap #13 */
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default_interrupt (TRAP14); /* Trap #14 */
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default_interrupt (TRAP15); /* Trap #15 */
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default_interrupt (SWT); /* Software Watchdog Timer */
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default_interrupt (TIMER0); /* Timer 0 */
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default_interrupt (TIMER1); /* Timer 1 */
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default_interrupt (I2C); /* I2C */
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default_interrupt (UART1); /* UART 1 */
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default_interrupt (UART2); /* UART 2 */
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default_interrupt (DMA0); /* DMA 0 */
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default_interrupt (DMA1); /* DMA 1 */
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default_interrupt (DMA2); /* DMA 2 */
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default_interrupt (DMA3); /* DMA 3 */
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default_interrupt (QSPI); /* QSPI */
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default_interrupt (PDIR1FULL); /* Processor data in 1 full */
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default_interrupt (PDIR2FULL); /* Processor data in 2 full */
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default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
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default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
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default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
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default_interrupt (PDIR3FULL); /* Processor data in 3 full */
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default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
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default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
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default_interrupt (AUDIOTICK); /* "tick" interrupt */
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default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
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default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
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default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
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default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
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default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
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default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
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default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
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default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
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default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
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default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
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default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
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default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
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default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
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default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
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default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
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default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
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default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
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default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
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default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
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default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
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default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
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default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
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default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
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default_interrupt (GPI0); /* GPIO interrupt 0 */
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default_interrupt (GPI1); /* GPIO interrupt 1 */
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default_interrupt (GPI2); /* GPIO interrupt 2 */
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default_interrupt (GPI3); /* GPIO interrupt 3 */
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default_interrupt (GPI4); /* GPIO interrupt 4 */
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default_interrupt (GPI5); /* GPIO interrupt 5 */
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default_interrupt (GPI6); /* GPIO interrupt 6 */
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default_interrupt (GPI7); /* GPIO interrupt 7 */
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default_interrupt (SOFTINT0); /* Software interrupt 0 */
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default_interrupt (SOFTINT1); /* Software interrupt 1 */
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default_interrupt (SOFTINT2); /* Software interrupt 2 */
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default_interrupt (SOFTINT3); /* Software interrupt 3 */
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default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
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default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
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default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
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default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
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void UIE (void) /* Unexpected Interrupt or Exception */
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{
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unsigned int format_vector, pc;
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int vector;
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char str[32];
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asm volatile ("move.l (52,%%sp),%0": "=r"(format_vector));
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asm volatile ("move.l (56,%%sp),%0": "=r"(pc));
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vector = (format_vector >> 18) & 0xff;
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/* clear screen */
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lcd_clear_display ();
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#ifdef HAVE_LCD_BITMAP
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lcd_setfont(FONT_SYSFIXED);
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#endif
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snprintf(str,sizeof(str),"I%02x:%s",vector,irqname[vector]);
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lcd_puts(0,0,str);
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snprintf(str,sizeof(str),"at %08x",pc);
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lcd_puts(0,1,str);
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lcd_update();
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while (1)
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{
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}
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}
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/* reset vectors are handled in crt0.S */
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void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
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{
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UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,TIMER0,UIE,UIE,UIE,UIE,
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TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
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TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
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SWT,UIE,TIMER1,I2C,UART1,UART2,DMA0,DMA1,
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DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
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PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
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IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
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AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
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PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
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IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
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UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
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IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
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IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
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GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
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SOFTINT1,SOFTINT2,SOFTINT3,UIE,
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UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
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CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
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};
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void system_init(void)
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{
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}
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#elif CONFIG_CPU == SH7034
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#include "led.h"
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#include "system.h"
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#include "rolo.h"
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#define default_interrupt(name,number) \
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extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
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#define reserve_interrupt(number) \
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void UIE##number (void)
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static const char* const irqname[] = {
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"", "", "", "", "IllInstr", "", "IllSltIn","","",
|
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"CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
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"","","","","","","","","","","","","","","","","","","",
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"Trap32","Trap33","Trap34","Trap35","Trap36","Trap37","Trap38","Trap39",
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"Trap40","Trap41","Trap42","Trap43","Trap44","Trap45","Trap46","Trap47",
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"Trap48","Trap49","Trap50","Trap51","Trap52","Trap53","Trap54","Trap55",
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"Trap56","Trap57","Trap58","Trap59","Trap60","Trap61","Trap62","Trap63",
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"Irq0","Irq1","Irq2","Irq3","Irq4","Irq5","Irq6","Irq7",
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"Dma0","","Dma1","","Dma2","","Dma3","",
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"IMIA0","IMIB0","OVI0","", "IMIA1","IMIB1","OVI1","",
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"IMIA2","IMIB2","OVI2","", "IMIA3","IMIB3","OVI3","",
|
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"IMIA4","IMIB4","OVI4","",
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"Ser0Err","Ser0Rx","Ser0Tx","Ser0TE",
|
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"Ser1Err","Ser1Rx","Ser1Tx","Ser1TE",
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"ParityEr","A/D conv","","","Watchdog","DRAMRefr"
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};
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reserve_interrupt ( 0);
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reserve_interrupt ( 1);
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reserve_interrupt ( 2);
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reserve_interrupt ( 3);
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default_interrupt (GII, 4);
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reserve_interrupt ( 5);
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default_interrupt (ISI, 6);
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reserve_interrupt ( 7);
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reserve_interrupt ( 8);
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default_interrupt (CPUAE, 9);
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default_interrupt (DMAAE, 10);
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default_interrupt (NMI, 11);
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default_interrupt (UB, 12);
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reserve_interrupt ( 13);
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reserve_interrupt ( 14);
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reserve_interrupt ( 15);
|
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reserve_interrupt ( 16); /* TCB #0 */
|
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reserve_interrupt ( 17); /* TCB #1 */
|
||
reserve_interrupt ( 18); /* TCB #2 */
|
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reserve_interrupt ( 19); /* TCB #3 */
|
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reserve_interrupt ( 20); /* TCB #4 */
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reserve_interrupt ( 21); /* TCB #5 */
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reserve_interrupt ( 22); /* TCB #6 */
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reserve_interrupt ( 23); /* TCB #7 */
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reserve_interrupt ( 24); /* TCB #8 */
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reserve_interrupt ( 25); /* TCB #9 */
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reserve_interrupt ( 26); /* TCB #10 */
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reserve_interrupt ( 27); /* TCB #11 */
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reserve_interrupt ( 28); /* TCB #12 */
|
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reserve_interrupt ( 29); /* TCB #13 */
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reserve_interrupt ( 30); /* TCB #14 */
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reserve_interrupt ( 31); /* TCB #15 */
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||
default_interrupt (TRAPA32, 32);
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default_interrupt (TRAPA33, 33);
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default_interrupt (TRAPA34, 34);
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default_interrupt (TRAPA35, 35);
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default_interrupt (TRAPA36, 36);
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default_interrupt (TRAPA37, 37);
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default_interrupt (TRAPA38, 38);
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default_interrupt (TRAPA39, 39);
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default_interrupt (TRAPA40, 40);
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default_interrupt (TRAPA41, 41);
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default_interrupt (TRAPA42, 42);
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default_interrupt (TRAPA43, 43);
|
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default_interrupt (TRAPA44, 44);
|
||
default_interrupt (TRAPA45, 45);
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default_interrupt (TRAPA46, 46);
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default_interrupt (TRAPA47, 47);
|
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default_interrupt (TRAPA48, 48);
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default_interrupt (TRAPA49, 49);
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default_interrupt (TRAPA50, 50);
|
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default_interrupt (TRAPA51, 51);
|
||
default_interrupt (TRAPA52, 52);
|
||
default_interrupt (TRAPA53, 53);
|
||
default_interrupt (TRAPA54, 54);
|
||
default_interrupt (TRAPA55, 55);
|
||
default_interrupt (TRAPA56, 56);
|
||
default_interrupt (TRAPA57, 57);
|
||
default_interrupt (TRAPA58, 58);
|
||
default_interrupt (TRAPA59, 59);
|
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default_interrupt (TRAPA60, 60);
|
||
default_interrupt (TRAPA61, 61);
|
||
default_interrupt (TRAPA62, 62);
|
||
default_interrupt (TRAPA63, 63);
|
||
default_interrupt (IRQ0, 64);
|
||
default_interrupt (IRQ1, 65);
|
||
default_interrupt (IRQ2, 66);
|
||
default_interrupt (IRQ3, 67);
|
||
default_interrupt (IRQ4, 68);
|
||
default_interrupt (IRQ5, 69);
|
||
default_interrupt (IRQ6, 70);
|
||
default_interrupt (IRQ7, 71);
|
||
default_interrupt (DEI0, 72);
|
||
reserve_interrupt ( 73);
|
||
default_interrupt (DEI1, 74);
|
||
reserve_interrupt ( 75);
|
||
default_interrupt (DEI2, 76);
|
||
reserve_interrupt ( 77);
|
||
default_interrupt (DEI3, 78);
|
||
reserve_interrupt ( 79);
|
||
default_interrupt (IMIA0, 80);
|
||
default_interrupt (IMIB0, 81);
|
||
default_interrupt (OVI0, 82);
|
||
reserve_interrupt ( 83);
|
||
default_interrupt (IMIA1, 84);
|
||
default_interrupt (IMIB1, 85);
|
||
default_interrupt (OVI1, 86);
|
||
reserve_interrupt ( 87);
|
||
default_interrupt (IMIA2, 88);
|
||
default_interrupt (IMIB2, 89);
|
||
default_interrupt (OVI2, 90);
|
||
reserve_interrupt ( 91);
|
||
default_interrupt (IMIA3, 92);
|
||
default_interrupt (IMIB3, 93);
|
||
default_interrupt (OVI3, 94);
|
||
reserve_interrupt ( 95);
|
||
default_interrupt (IMIA4, 96);
|
||
default_interrupt (IMIB4, 97);
|
||
default_interrupt (OVI4, 98);
|
||
reserve_interrupt ( 99);
|
||
default_interrupt (REI0, 100);
|
||
default_interrupt (RXI0, 101);
|
||
default_interrupt (TXI0, 102);
|
||
default_interrupt (TEI0, 103);
|
||
default_interrupt (REI1, 104);
|
||
default_interrupt (RXI1, 105);
|
||
default_interrupt (TXI1, 106);
|
||
default_interrupt (TEI1, 107);
|
||
reserve_interrupt ( 108);
|
||
default_interrupt (ADITI, 109);
|
||
|
||
/* reset vectors are handled in crt0.S */
|
||
void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
|
||
{
|
||
/*** 4 General Illegal Instruction ***/
|
||
|
||
GII,
|
||
|
||
/*** 5 Reserved ***/
|
||
|
||
UIE5,
|
||
|
||
/*** 6 Illegal Slot Instruction ***/
|
||
|
||
ISI,
|
||
|
||
/*** 7-8 Reserved ***/
|
||
|
||
UIE7,UIE8,
|
||
|
||
/*** 9 CPU Address Error ***/
|
||
|
||
CPUAE,
|
||
|
||
/*** 10 DMA Address Error ***/
|
||
|
||
DMAAE,
|
||
|
||
/*** 11 NMI ***/
|
||
|
||
NMI,
|
||
|
||
/*** 12 User Break ***/
|
||
|
||
UB,
|
||
|
||
/*** 13-31 Reserved ***/
|
||
|
||
UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
|
||
|
||
/*** 32-63 TRAPA #20...#3F ***/
|
||
|
||
TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
|
||
|
||
/*** 64-71 IRQ0-7 ***/
|
||
|
||
IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
|
||
|
||
/*** 72 DMAC0 ***/
|
||
|
||
DEI0,
|
||
|
||
/*** 73 Reserved ***/
|
||
|
||
UIE73,
|
||
|
||
/*** 74 DMAC1 ***/
|
||
|
||
DEI1,
|
||
|
||
/*** 75 Reserved ***/
|
||
|
||
UIE75,
|
||
|
||
/*** 76 DMAC2 ***/
|
||
|
||
DEI2,
|
||
|
||
/*** 77 Reserved ***/
|
||
|
||
UIE77,
|
||
|
||
/*** 78 DMAC3 ***/
|
||
|
||
DEI3,
|
||
|
||
/*** 79 Reserved ***/
|
||
|
||
UIE79,
|
||
|
||
/*** 80-82 ITU0 ***/
|
||
|
||
IMIA0,IMIB0,OVI0,
|
||
|
||
/*** 83 Reserved ***/
|
||
|
||
UIE83,
|
||
|
||
/*** 84-86 ITU1 ***/
|
||
|
||
IMIA1,IMIB1,OVI1,
|
||
|
||
/*** 87 Reserved ***/
|
||
|
||
UIE87,
|
||
|
||
/*** 88-90 ITU2 ***/
|
||
|
||
IMIA2,IMIB2,OVI2,
|
||
|
||
/*** 91 Reserved ***/
|
||
|
||
UIE91,
|
||
|
||
/*** 92-94 ITU3 ***/
|
||
|
||
IMIA3,IMIB3,OVI3,
|
||
|
||
/*** 95 Reserved ***/
|
||
|
||
UIE95,
|
||
|
||
/*** 96-98 ITU4 ***/
|
||
|
||
IMIA4,IMIB4,OVI4,
|
||
|
||
/*** 99 Reserved ***/
|
||
|
||
UIE99,
|
||
|
||
/*** 100-103 SCI0 ***/
|
||
|
||
REI0,RXI0,TXI0,TEI0,
|
||
|
||
/*** 104-107 SCI1 ***/
|
||
|
||
REI1,RXI1,TXI1,TEI1,
|
||
|
||
/*** 108 Parity Control Unit ***/
|
||
|
||
UIE108,
|
||
|
||
/*** 109 AD Converter ***/
|
||
|
||
ADITI
|
||
|
||
};
|
||
|
||
|
||
void system_reboot (void)
|
||
{
|
||
set_irq_level(HIGHEST_IRQ_LEVEL);
|
||
|
||
asm volatile ("ldc\t%0,vbr" : : "r"(0));
|
||
|
||
PACR2 |= 0x4000; /* for coldstart detection */
|
||
IPRA = 0;
|
||
IPRB = 0;
|
||
IPRC = 0;
|
||
IPRD = 0;
|
||
IPRE = 0;
|
||
ICR = 0;
|
||
|
||
asm volatile ("jmp @%0; mov.l @%1,r15" : :
|
||
"r"(*(int*)0),"r"(4));
|
||
}
|
||
|
||
void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
|
||
{
|
||
bool state = true;
|
||
unsigned int n;
|
||
char str[32];
|
||
|
||
asm volatile ("sts\tpr,%0" : "=r"(n));
|
||
|
||
/* clear screen */
|
||
lcd_clear_display ();
|
||
#ifdef HAVE_LCD_BITMAP
|
||
lcd_setfont(FONT_SYSFIXED);
|
||
#endif
|
||
/* output exception */
|
||
n = (n - (unsigned)UIE0 - 4)>>2; /* get exception or interrupt number */
|
||
snprintf(str,sizeof(str),"I%02x:%s",n,irqname[n]);
|
||
lcd_puts(0,0,str);
|
||
snprintf(str,sizeof(str),"at %08x",pc);
|
||
lcd_puts(0,1,str);
|
||
|
||
#ifdef HAVE_LCD_BITMAP
|
||
lcd_update ();
|
||
#endif
|
||
|
||
while (1)
|
||
{
|
||
volatile int i;
|
||
led (state);
|
||
state = state?false:true;
|
||
|
||
for (i = 0; i < 240000; ++i);
|
||
|
||
/* try to restart firmware if ON is pressed */
|
||
#if CONFIG_KEYPAD == PLAYER_PAD
|
||
if (!(PADR & 0x0020))
|
||
rolo_load("/archos.mod");
|
||
#elif CONFIG_KEYPAD == RECORDER_PAD
|
||
#ifdef HAVE_FMADC
|
||
if (!(PCDR & 0x0008))
|
||
#else
|
||
if (!(PBDR & 0x0100))
|
||
#endif
|
||
rolo_load("/ajbrec.ajz");
|
||
#endif
|
||
}
|
||
}
|
||
|
||
asm (
|
||
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
|
||
|
||
void system_init(void)
|
||
{
|
||
/* Disable all interrupts */
|
||
IPRA = 0;
|
||
IPRB = 0;
|
||
IPRC = 0;
|
||
IPRD = 0;
|
||
IPRE = 0;
|
||
|
||
/* NMI level low, falling edge on all interrupts */
|
||
ICR = 0;
|
||
|
||
/* Enable burst and RAS down mode on DRAM */
|
||
DCR |= 0x5000;
|
||
|
||
/* Activate Warp mode (simultaneous internal and external mem access) */
|
||
BCR |= 0x2000;
|
||
|
||
/* Bus state controller initializations. These are only necessary when
|
||
running from flash. */
|
||
WCR1 = 0x40FD; /* Long wait states for CS6 (ATA), short for the rest. */
|
||
WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */
|
||
}
|
||
|
||
/* Utilize the user break controller to catch invalid memory accesses. */
|
||
int system_memory_guard(int newmode)
|
||
{
|
||
static const struct {
|
||
unsigned long addr;
|
||
unsigned long mask;
|
||
unsigned short bbr;
|
||
} modes[MAXMEMGUARD] = {
|
||
/* catch nothing */
|
||
{ 0x00000000, 0x00000000, 0x0000 },
|
||
/* catch writes to area 02 (flash ROM) */
|
||
{ 0x02000000, 0x00FFFFFF, 0x00F8 },
|
||
/* catch all accesses to areas 00 (internal ROM) and 01 (free) */
|
||
{ 0x00000000, 0x01FFFFFF, 0x00FC }
|
||
};
|
||
|
||
int oldmode = MEMGUARD_NONE;
|
||
int i;
|
||
|
||
/* figure out the old mode from what is in the UBC regs. If the register
|
||
values don't match any mode, assume MEMGUARD_NONE */
|
||
for (i = MEMGUARD_NONE; i < MAXMEMGUARD; i++)
|
||
{
|
||
if (BAR == modes[i].addr && BAMR == modes[i].mask &&
|
||
BBR == modes[i].bbr)
|
||
{
|
||
oldmode = i;
|
||
break;
|
||
}
|
||
}
|
||
|
||
if (newmode == MEMGUARD_KEEP)
|
||
newmode = oldmode;
|
||
|
||
BBR = 0; /* switch off everything first */
|
||
|
||
/* always set the UBC according to the mode, in case the old settings
|
||
didn't match any valid mode */
|
||
BAR = modes[newmode].addr;
|
||
BAMR = modes[newmode].mask;
|
||
BBR = modes[newmode].bbr;
|
||
|
||
return oldmode;
|
||
}
|
||
#endif
|
||
|
||
#if CONFIG_CPU != SH7034
|
||
/* this does nothing on non-SH systems */
|
||
int system_memory_guard(int newmode)
|
||
{
|
||
(void)newmode;
|
||
return 0;
|
||
}
|
||
void system_reboot (void)
|
||
{
|
||
/* dummy */
|
||
}
|
||
#endif
|