4fe6963e40
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31443 a1c6a512-1295-4272-9138-f99709370657
180 lines
6.9 KiB
C
180 lines
6.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef CLKCTRL_IMX233_H
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#define CLKCTRL_IMX233_H
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#include "config.h"
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#include "system.h"
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#include "cpu.h"
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#define HW_CLKCTRL_BASE 0x80040000
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#define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0))
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#define HW_CLKCTRL_PLLCTRL0__POWER (1 << 16)
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#define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS (1 << 18)
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#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP 20
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#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20)
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#define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10))
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#define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20))
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#define HW_CLKCTRL_CPU__DIV_CPU_BP 0
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#define HW_CLKCTRL_CPU__DIV_CPU_BM 0x3f
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#define HW_CLKCTRL_CPU__INTERRUPT_WAIT (1 << 12)
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#define HW_CLKCTRL_CPU__DIV_XTAL_BP 16
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#define HW_CLKCTRL_CPU__DIV_XTAL_BM (0x3ff << 16)
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#define HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN (1 << 26)
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#define HW_CLKCTRL_CPU__BUSY_REF_CPU (1 << 28)
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#define HW_CLKCTRL_HBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30))
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#define HW_CLKCTRL_HBUS__DIV_BP 0
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#define HW_CLKCTRL_HBUS__DIV_BM 0x1f
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#define HW_CLKCTRL_HBUS__DIV_FRAC_EN (1 << 5)
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#define HW_CLKCTRL_HBUS__SLOW_DIV_BP 16
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#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16)
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#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
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#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
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#define HW_CLKCTRL_XBUS__DIV_BP 0
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#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff
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#define HW_CLKCTRL_XBUS__BUSY (1 << 31)
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#define HW_CLKCTRL_XTAL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50))
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#define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26)
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#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28)
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#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30)
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#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
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#define HW_CLKCTRL_PIX__DIV_BP 0
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#define HW_CLKCTRL_PIX__DIV_BM 0xfff
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#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
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#define HW_CLKCTRL_SSP__DIV_BP 0
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#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
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#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
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#define HW_CLKCTRL_EMI__DIV_EMI_BP 0
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#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f
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#define HW_CLKCTRL_EMI__DIV_XTAL_BP 8
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#define HW_CLKCTRL_EMI__DIV_XTAL_BM (0xf << 8)
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#define HW_CLKCTRL_EMI__BUSY_REF_EMI (1 << 28)
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#define HW_CLKCTRL_EMI__SYNC_MODE_EN (1 << 30)
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#define HW_CLKCTRL_EMI__CLKGATE (1 << 31)
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#define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110))
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#define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1)
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#define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5)
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#define HW_CLKCTRL_CLKSEQ__BYPASS_EMI (1 << 6)
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#define HW_CLKCTRL_CLKSEQ__BYPASS_CPU (1 << 7)
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#define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0))
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#define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0))
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#define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1))
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#define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2))
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#define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3))
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#define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f
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#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
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#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
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#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
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#define HW_CLKCTRL_RESET_CHIP 0x2
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#define HW_CLKCTRL_RESET_DIG 0x1
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static inline void core_sleep(void)
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{
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__REG_SET(HW_CLKCTRL_CPU) = HW_CLKCTRL_CPU__INTERRUPT_WAIT;
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asm volatile (
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"mcr p15, 0, %0, c7, c0, 4 \n" /* Wait for interrupt */
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"nop\n" /* Datasheet unclear: "The lr sent to handler points here after RTI"*/
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: : "r"(0)
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);
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enable_irq();
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}
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enum imx233_clock_t
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{
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CLK_PIX, /* freq, div, frac, bypass, enable */
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CLK_SSP, /* freq, div, bypass, enable */
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CLK_IO, /* freq, frac */
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CLK_CPU, /* freq, div, frac, bypass */
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CLK_HBUS, /* freq, div, frac */
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CLK_PLL, /* freq */
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CLK_XTAL, /* freq */
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CLK_EMI, /* freq */
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CLK_XBUS, /* freq, div */
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};
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enum imx233_xtal_clk_t
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{
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XTAL_FILT = 1 << 30,
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XTAL_DRI = 1 << 28,
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XTAL_TIMROT = 1 << 26,
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};
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/* Auto-Slow monitoring */
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enum imx233_as_monitor_t
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{
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AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */
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AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */
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AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */
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AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */
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AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */
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AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */
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AS_PXP = 1 << 27, /* Monitor PXP activity */
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AS_DCP = 1 << 28, /* Monitor DCP activity */
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};
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enum imx233_as_div_t
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{
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AS_DIV_1 = 0,
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AS_DIV_2 = 1,
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AS_DIV_4 = 2,
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AS_DIV_8 = 3,
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AS_DIV_16 = 4,
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AS_DIV_32 = 5
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};
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/* can use a mask of clocks */
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void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable);
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bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk);
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/* only use it for non-fractional clocks (ie not for IO) */
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void imx233_enable_clock(enum imx233_clock_t clk, bool enable);
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bool imx233_is_clock_enable(enum imx233_clock_t cl);
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void imx233_set_clock_divisor(enum imx233_clock_t clk, int div);
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int imx233_get_clock_divisor(enum imx233_clock_t clk);
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/* call with fracdiv=0 to disable it */
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void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
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/* 0 means fractional dividor disable */
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int imx233_get_fractional_divisor(enum imx233_clock_t clk);
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void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
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bool imx233_get_bypass_pll(enum imx233_clock_t clk);
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void imx233_enable_usb_pll(bool enable);
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bool imx233_is_usb_pll_enable(void);
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unsigned imx233_get_clock_freq(enum imx233_clock_t clk);
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void imx233_set_auto_slow_divisor(enum imx233_as_div_t div);
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enum imx233_as_div_t imx233_get_auto_slow_divisor(void);
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void imx233_enable_auto_slow(bool enable);
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bool imx233_is_auto_slow_enable(void);
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void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
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bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor);
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#endif /* CLKCTRL_IMX233_H */
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