332 lines
11 KiB
C
332 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "clkctrl-imx233.h"
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#define __CLK_CLKGATE (1 << 31)
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#define __CLK_BUSY (1 << 29)
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void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
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{
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if(enable)
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HW_CLKCTRL_XTAL_CLR = xtal_clk;
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else
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HW_CLKCTRL_XTAL_SET = xtal_clk;
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}
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bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
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{
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return HW_CLKCTRL_XTAL & clk;
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}
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void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
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{
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bool gate = !enable;
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switch(clk)
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{
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case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break;
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case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break;
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case CLK_PLL:
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/* pll is a special case */
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if(enable)
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{
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BF_SET(CLKCTRL_PLLCTRL0, POWER);
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while(!BF_RD(CLKCTRL_PLLCTRL1, LOCK));
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}
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else
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BF_CLR(CLKCTRL_PLLCTRL0, POWER);
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break;
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default:
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break;
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}
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}
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bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER);
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case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE);
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case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE);
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default: return true;
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}
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}
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void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
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{
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant !
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* assume that we always derive emi and cpu from ref_XX */
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switch(clk)
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{
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case CLK_PIX: BF_WR(CLKCTRL_PIX, DIV, div); break;
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case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV_CPU, div); break;
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case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV_EMI, div); break;
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case CLK_SSP: BF_WR(CLKCTRL_SSP, DIV, div); break;
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case CLK_HBUS: BF_WR(CLKCTRL_HBUS, DIV, div); break;
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case CLK_XBUS: BF_WR(CLKCTRL_XBUS, DIV, div); break;
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default: return;
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}
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}
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int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PIX: return BF_RD(CLKCTRL_PIX, DIV);
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case CLK_CPU: return BF_RD(CLKCTRL_CPU, DIV_CPU);
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case CLK_EMI: return BF_RD(CLKCTRL_EMI, DIV_EMI);
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case CLK_SSP: return BF_RD(CLKCTRL_SSP, DIV);
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case CLK_HBUS: return BF_RD(CLKCTRL_HBUS, DIV);
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case CLK_XBUS: return BF_RD(CLKCTRL_XBUS, DIV);
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default: return 0;
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}
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}
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void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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{
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#define handle_frac(dev) \
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case CLK_##dev: \
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if(fracdiv == 0) \
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BF_SET(CLKCTRL_FRAC, CLKGATE##dev); \
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else { \
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BF_WR(CLKCTRL_FRAC, dev##FRAC, fracdiv); \
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BF_CLR(CLKCTRL_FRAC, CLKGATE##dev); } \
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break;
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switch(clk)
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{
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handle_frac(PIX)
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handle_frac(IO)
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handle_frac(CPU)
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handle_frac(EMI)
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default: break;
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}
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#undef handle_frac
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}
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int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
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{
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#define handle_frac(dev) \
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case CLK_##dev:\
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if(BF_RD(CLKCTRL_FRAC, CLKGATE##dev)) \
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return 0; \
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else \
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return BF_RD(CLKCTRL_FRAC, dev##FRAC);
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switch(clk)
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{
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handle_frac(PIX)
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handle_frac(IO)
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handle_frac(CPU)
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handle_frac(EMI)
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default: return 0;
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}
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#undef handle_frac
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}
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void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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{
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uint32_t msk;
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switch(clk)
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{
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case CLK_PIX: msk = BM_CLKCTRL_CLKSEQ_BYPASS_PIX; break;
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case CLK_SSP: msk = BM_CLKCTRL_CLKSEQ_BYPASS_SSP; break;
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case CLK_CPU: msk = BM_CLKCTRL_CLKSEQ_BYPASS_CPU; break;
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case CLK_EMI: msk = BM_CLKCTRL_CLKSEQ_BYPASS_EMI; break;
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default: return;
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}
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if(bypass)
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HW_CLKCTRL_CLKSEQ_SET = msk;
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else
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HW_CLKCTRL_CLKSEQ_CLR = msk;
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}
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bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PIX: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_PIX);
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case CLK_SSP: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_SSP);
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case CLK_CPU: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_CPU);
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case CLK_EMI: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_EMI);
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default: return false;
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}
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}
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void imx233_clkctrl_enable_usb_pll(bool enable)
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{
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if(enable)
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BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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else
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BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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}
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bool imx233_clkctrl_is_usb_pll_enabled(void)
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{
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return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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}
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void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
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{
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/* the SLOW_DIV must only be set when auto-slow is disabled */
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bool old_status = imx233_clkctrl_is_auto_slow_enabled();
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imx233_clkctrl_enable_auto_slow(false);
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BF_WR(CLKCTRL_HBUS, SLOW_DIV, div);
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imx233_clkctrl_enable_auto_slow(old_status);
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}
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enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
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{
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return BF_RD(CLKCTRL_HBUS, SLOW_DIV);
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}
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void imx233_clkctrl_enable_auto_slow(bool enable)
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{
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BF_WR(CLKCTRL_HBUS, AUTO_SLOW_MODE, enable);
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}
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bool imx233_clkctrl_is_auto_slow_enabled(void)
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{
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return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE);
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}
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void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
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{
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if(enable)
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HW_CLKCTRL_HBUS_SET = monitor;
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else
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HW_CLKCTRL_HBUS_CLR = monitor;
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}
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bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
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{
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return HW_CLKCTRL_HBUS & monitor;
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}
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bool imx233_clkctrl_is_emi_sync_enabled(void)
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{
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return BF_RD(CLKCTRL_EMI, SYNC_MODE_EN);
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}
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unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PLL: /* PLL: 480MHz when enable */
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return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0;
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case CLK_XTAL: /* crystal: 24MHz */
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return 24000;
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case CLK_CPU:
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{
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unsigned ref;
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/* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider
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* otherwise, clk_p derived from clk_cpu via int div and clk_cpu
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* derived from clk_pll fracdiv */
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if(imx233_clkctrl_get_bypass_pll(CLK_CPU))
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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/* Integer divide mode vs fractional divide mode */
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if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN))
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return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32;
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else
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return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
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}
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else
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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/* fractional divider enable ? */
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if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
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}
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}
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case CLK_HBUS:
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{
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/* Derived from clk_p via integer/fractional div */
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unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU);
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if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0)
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ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32;
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if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0)
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ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS);
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return ref;
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}
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case CLK_IO:
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{
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/* Derived from clk_pll via fracdiv */
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unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO);
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return ref;
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}
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case CLK_PIX:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(!imx233_clkctrl_is_clock_enabled(CLK_PIX))
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ref = 0;
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else if(imx233_clkctrl_get_bypass_pll(CLK_PIX))
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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else
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX);
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}
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return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX);
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}
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case CLK_SSP:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(!imx233_clkctrl_is_clock_enabled(CLK_SSP))
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ref = 0;
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else if(imx233_clkctrl_get_bypass_pll(CLK_SSP))
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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else
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ref = imx233_clkctrl_get_clock_freq(CLK_IO);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP);
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}
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case CLK_EMI:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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if(BF_RD(CLKCTRL_EMI, CLKGATE))
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return 0;
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else
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return ref / BF_RD(CLKCTRL_EMI, DIV_XTAL);
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}
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else
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI);
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}
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}
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case CLK_XBUS:
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return imx233_clkctrl_get_clock_freq(CLK_XTAL) /
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imx233_clkctrl_get_clock_divisor(CLK_XBUS);
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default:
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return 0;
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}
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}
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