238be18d03
- drop support for PP500x: it's very different from other PP and although it would be possible to support them, I don't have one to test the code - make sure only the CPU is started - add PP descriptor to report chip ID and revision - add code in shell and lua to support pp (no register description yet) - compile for ARMv4 because PP502x is an ARM7TDMI Change-Id: I36c4e465dfc2cfdfe7433b2f65cc8f6f0720fe62
53 lines
1.2 KiB
ArmAsm
53 lines
1.2 KiB
ArmAsm
.section .text,"ax",%progbits
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.code 32
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.align 0x04
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.global start
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start:
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sub r7, pc, #8 /* Copy running address */
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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/* Get processor ID */
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ldr r0, =0x60000000 /* PROC_ID */
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ldrb r4, [r0]
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/* Halt the COP */
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ldr r6, =0x60007004 /* COP_CTL */
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cmp r4, #0x55 /* CPU_ID */
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1:
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ldrne r1, [r6]
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orrne r1, #0x80000000 /* PROC_SLEEP */
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strne r1, [r6]
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bne 1b
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/* Wait for the COP to be stopped */
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1:
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ldr r0, [r6]
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tst r0, #0x80000000 /* PROC_SLEEP */
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beq 1b
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/* Relocate to right address */
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mov r2, r7
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ldr r3, =_copystart
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ldr r4, =_copyend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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mov r2, #0
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/* FIXME invalid Icache here ? */
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/* Jump to real location */
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ldr pc, =remap
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remap:
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/* NOTE on PP611x, we should make sure the MMU is disabled at this point */
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/* clear bss */
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ldr r2, =bss_start
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ldr r3, =bss_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* jump to C code */
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ldr sp, =oc_stackend
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b main
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