343c3b795a
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20417 a1c6a512-1295-4272-9138-f99709370657
348 lines
8.9 KiB
C
348 lines
8.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#if !defined(BOOTLOADER)
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(EXT0);
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default_interrupt(EXT1);
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default_interrupt(EXT2);
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default_interrupt(EXT3);
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default_interrupt(RTC);
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default_interrupt(GPSB0);
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default_interrupt(TIMER0);
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default_interrupt(TIMER1);
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default_interrupt(SCORE);
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default_interrupt(SPDTX);
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default_interrupt(VIDEO);
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default_interrupt(GSIO);
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default_interrupt(SCALER);
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default_interrupt(I2C);
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default_interrupt(DAI_RX);
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default_interrupt(DAI_TX);
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default_interrupt(CDRX);
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default_interrupt(HPI);
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default_interrupt(UART0);
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default_interrupt(UART1);
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default_interrupt(G2D);
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default_interrupt(USB_DEVICE);
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default_interrupt(USB_HOST);
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default_interrupt(DMA);
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default_interrupt(HDD);
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default_interrupt(MSTICK);
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default_interrupt(NFC);
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default_interrupt(SDMMC);
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default_interrupt(CAM);
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default_interrupt(LCD);
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default_interrupt(ADC);
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default_interrupt(GPSB1);
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/* TODO: Establish IRQ priorities (0 = highest priority) */
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static const char irqpriority[] =
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{
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0, /* EXT0 */
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1, /* EXT1 */
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2, /* EXT2 */
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3, /* EXT3 */
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4, /* RTC */
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5, /* GPSB0 */
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6, /* TIMER0 */
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7, /* TIMER1 */
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8, /* SCORE */
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9, /* SPDTX */
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10, /* VIDEO */
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11, /* GSIO */
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12, /* SCALER */
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13, /* I2C */
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14, /* DAI_RX */
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15, /* DAI_TX */
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16, /* CDRX */
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17, /* HPI */
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18, /* UART0 */
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19, /* UART1 */
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20, /* G2D */
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21, /* USB_DEVICE */
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22, /* USB_HOST */
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23, /* DMA */
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24, /* HDD */
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25, /* MSTICK */
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26, /* NFC */
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27, /* SDMMC */
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28, /* CAM */
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29, /* LCD */
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30, /* ADC */
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31, /* GPSB */
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};
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static void (* const irqvector[])(void) =
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{
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EXT0,EXT1,EXT2,EXT3,RTC,GPSB0,TIMER0,TIMER1,
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SCORE,SPDTX,VIDEO,GSIO,SCALER,I2C,DAI_RX,DAI_TX,
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CDRX,HPI,UART0,UART1,G2D,USB_DEVICE,USB_HOST,DMA,
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HDD,MSTICK,NFC,SDMMC,CAM,LCD,ADC,GPSB1
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};
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static const char * const irqname[] =
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{
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"EXT0","EXT1","EXT2","EXT3","RTC","GPSB0","TIMER0","TIMER1",
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"SCORE","SPDTX","VIDEO","GSIO","SCALER","I2C","DAI_RX","DAI_TX",
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"CDRX","HPI","UART0","UART1","G2D","USB_DEVICE","USB_HOST","DMA",
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"HDD","MSTICK","NFC","SDMMC","CAM","LCD","ADC","GPSB1"
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};
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static void UIRQ(void)
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{
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unsigned int offset = VNIRQ;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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int irq_no = VNIRQ; /* Read clears the corresponding IRQ status */
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if ((irq_no & (1<<31)) == 0) /* Ensure invalid flag is not set */
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{
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irqvector[irq_no]();
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}
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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#endif /* !defined(BOOTLOADER) */
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/* TODO - these should live in the target-specific directories and
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once we understand what all the GPIO pins do, move the init to the
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specific driver for that hardware. For now, we just perform the
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same GPIO init as the original firmware - this makes it easier to
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investigate what the GPIO pins do.
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*/
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#ifdef COWON_D2
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static void gpio_init(void)
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{
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/* Do what the original firmware does */
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GPIOA = 0x07000C83;
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GPIOA_DIR = 0x0F010CE3;
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GPIOB = 0;
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GPIOB_DIR = 0x00080000;
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GPIOC = 0x39000000;
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GPIOC_DIR = 0xB9000000;
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GPIOD = 0;
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GPIOD_DIR = 0;
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GPIOD = 0;
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GPIOD_DIR = 0x00480000;
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PORTCFG0 = 0x00034540;
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PORTCFG1 = 0x0566A000;
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PORTCFG2 = 0x000004C0;
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PORTCFG3 = 0x0AA40455;
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}
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#endif
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/* Second function called in the original firmware's startup code - we just
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set up the clocks in the same way as the original firmware for now. */
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#ifdef COWON_D2
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static void clock_init(void)
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{
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int i;
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CSCFG3 = (CSCFG3 &~ 0x3fff) | 0x841;
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/* Enable Xin (12Mhz), Fsys = Xin, Fbus = Fsys/2, MCPU=Fsys, SCPU=Fsys */
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CLKCTRL = 0x800FF014;
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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PCLK_RFREQ = 0x1401002d; /* RAM refresh source = Xin (4) / 0x2d = 266kHz */
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MCFG |= 1;
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SDCFG = (SDCFG &~ 0x7000) | 0x2000;
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MCFG1 |= 1;
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SDCFG1 = (SDCFG &~ 0x7000) | 0x2000;
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/* Configure PLL0 to 192Mhz, for CPU scaling */
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PLL0CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 24); /* disable PLL0 divider */
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PLL0CFG = 0x80019808; /* set for 192Mhz (with power down) */
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PLL0CFG = PLL0CFG &~ (1<<31); /* power up */
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/* Configure PLL1 to 216Mz, for LCD clock (when divided by 2) */
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PLL1CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 16); /* disable PLL1 divider */
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PLL1CFG = 0x80002503; /* set for 216Mhz (with power down)*/
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PLL1CFG = PLL1CFG &~ (1<<31); /* power up */
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i = 0x8000;
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while (--i) {};
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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set_cpu_frequency(CPUFREQ_NORMAL);
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#else
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/* 48Mhz: Fsys = PLL0 (192Mhz) Fbus = Fsys/4 CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (3<<4);
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#endif
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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/* configure PCK_TCT to 2Mhz (clock source 4 (Xin) divided by 6) */
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PCLK_TCT = PCK_EN | (CKSEL_XIN<<24) | 5;
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/* set TC32 timer to XIN divided by 12 (1MHz) */
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TC32EN = (1<<24) | 11;
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}
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#endif
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#ifdef COWON_D2
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void system_init(void)
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{
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MBCFG = 0x19;
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if (TCC780_VER == 0)
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ECFG0 = 0x309;
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else
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ECFG0 = 0x30d;
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/* mask all interrupts */
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IEN = 0;
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#if !defined(BOOTLOADER)
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/* Set DAI interrupts as FIQ, all others are IRQ. */
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IRQSEL = ~(DAI_RX_IRQ_MASK | DAI_TX_IRQ_MASK);
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POL = 0x200108; /* IRQs 3,8,21 active low (as OF) */
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TMODE = 0x20ce07c0; /* IRQs 6-10,17-19,22-23,29 level-triggered (as OF) */
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VCTRL |= (1<<31); /* Reading from VNIRQ clears that interrupt */
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/* Write IRQ priority registers using ints - a freeze occurs otherwise */
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int i;
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for (i = 0; i < 7; i++)
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{
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IRQ_PRIORITY_TABLE[i] = ((int*)irqpriority)[i];
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}
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ALLMASK = 3; /* Global FIQ/IRQ unmask */
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#endif /* !defined(BOOTLOADER) */
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gpio_init();
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clock_init();
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}
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#endif
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void system_reboot(void)
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{
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disable_interrupt(IRQ_FIQ_DISABLED);
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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set_cpu_frequency(CPUFREQ_DEFAULT);
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#endif
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/* TODO: implement reboot (eg. jump to boot ROM?) */
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while (1);
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}
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void system_exception_wait(void)
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{
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while ((GPIOA & 0x10) == 0); /* check for power button */
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (cpu_frequency == frequency)
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return;
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/* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max).
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Fbus should not be set below ~32Mhz with LCD enabled or the display
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will be garbled. */
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if (frequency == CPUFREQ_MAX)
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{
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/* 192Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/2
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CPU = Fsys, COP = Fsys */
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CLKCTRL = (1<<31) | (0xFF<<12) | (1<<4);
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}
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else if (frequency == CPUFREQ_NORMAL)
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{
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/* 48Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/4
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CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (3<<4);
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}
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else
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{
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/* 32Mhz:
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Fsys = PLL0 (192Mhz)
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Fbus = Fsys/6
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CPU = Fbus, COP = Fbus */
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CLKCTRL = (1<<31) | (3<<28) | (5<<4);
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}
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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"nop \n\t"
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);
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cpu_frequency = frequency;
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}
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#endif
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