2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
615 lines
18 KiB
C
615 lines
18 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#include "sound.h"
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#include "pcm.h"
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#ifdef HAVE_WM8751
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#define MROBE100_44100HZ (0x40|(0x11 << 1)|1)
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#endif
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/** DMA **/
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#ifdef CPU_PP502x
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/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
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#define SAMPLE_SIZE 16
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#else
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/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
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#define SAMPLE_SIZE 32
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#endif
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struct dma_data
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{
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/* NOTE: The order of size and p is important if you use assembler
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optimised fiq handler, so don't change it. */
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#if SAMPLE_SIZE == 16
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uint32_t *p;
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#elif SAMPLE_SIZE == 32
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uint16_t *p;
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#endif
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size_t size;
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#if NUM_CORES > 1
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unsigned core;
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#endif
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int locked;
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int state;
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};
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extern void *fiq_function;
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/* Dispatch to the proper handler and leave the main vector table alone */
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void fiq_handler(void) ICODE_ATTR __attribute__((naked));
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void fiq_handler(void)
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{
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asm volatile (
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"ldr pc, [pc, #-4] \n"
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"fiq_function: \n"
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".word 0 \n"
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);
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}
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/* TODO: Get simultaneous recording and playback to work. Just needs some tweaking */
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/****************************************************************************
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** Playback DMA transfer
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**/
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struct dma_data dma_play_data SHAREDBSS_ATTR =
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{
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/* Initialize to a locked, stopped state */
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.p = NULL,
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.size = 0,
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#if NUM_CORES > 1
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.core = 0x00,
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#endif
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.locked = 0,
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.state = 0
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};
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static unsigned long pcm_freq SHAREDDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
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#ifdef HAVE_WM8751
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/* Samplerate control for audio codec */
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static int sr_ctrl = MROBE100_44100HZ;
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#endif
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void pcm_set_frequency(unsigned int frequency)
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{
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(void)frequency;
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pcm_freq = HW_SAMPR_DEFAULT;
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#ifdef HAVE_WM8751
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sr_ctrl = MROBE100_44100HZ;
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#endif
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}
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void pcm_apply_settings(void)
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{
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#ifdef HAVE_WM8751
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audiohw_set_frequency(sr_ctrl);
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#endif
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pcm_curr_sampr = pcm_freq;
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}
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/* ASM optimised FIQ handler. Checks for the minimum allowed loop cycles by
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* evalutation of free IISFIFO-slots against available source buffer words.
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* Through this it is possible to move the check for IIS_TX_FREE_COUNT outside
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* the loop and do some further optimization. Right after the loops (source
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* buffer -> IISFIFO) are done we need to check whether we have to exit FIQ
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* handler (this must be done, if all free FIFO slots were filled) or we will
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* have to get some new source data. Important information kept from former
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* ASM implementation (not used anymore): GCC fails to make use of the fact
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* that FIQ mode has registers r8-r14 banked, and so does not need to be saved.
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* This routine uses only these registers, and so will never touch the stack
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* unless it actually needs to do so when calling pcm_callback_for_more.
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* C version is still included below for reference and testing.
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*/
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#if 1
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void fiq_playback(void) ICODE_ATTR __attribute__((naked));
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void fiq_playback(void)
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{
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/* r10 contains IISCONFIG address (set in crt0.S to minimise code in actual
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* FIQ handler. r11 contains address of p (also set in crt0.S). Most other
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* addresses we need are generated by using offsets with these two.
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* r10 + 0x40 is IISFIFO_WR, and r10 + 0x0c is IISFIFO_CFG.
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* r8 and r9 contains local copies of p and size respectively.
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* r0-r3 and r12 is a working register.
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*/
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asm volatile (
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"stmfd sp!, { r0-r3, lr } \n" /* stack scratch regs and lr */
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#if CONFIG_CPU == PP5002
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"ldr r12, =0xcf001040 \n" /* Some magic from iPodLinux */
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"ldr r12, [r12] \n"
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#endif
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"ldmia r11, { r8-r9 } \n" /* r8 = p, r9 = size */
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"cmp r9, #0 \n" /* is size 0? */
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"beq .more_data \n" /* if so, ask pcmbuf for more data */
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#if SAMPLE_SIZE == 16
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".check_fifo: \n"
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"ldr r0, [r10, %[cfg]] \n" /* read IISFIFO_CFG to check FIFO status */
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"and r0, r0, %[mask] \n" /* r0 = IIS_TX_FREE_COUNT << 16 (PP502x) */
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"mov r1, r0, lsr #16 \n" /* number of free FIFO slots */
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"cmp r1, r9, lsr #2 \n" /* number of words from source */
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"movgt r1, r9, lsr #2 \n" /* r1 = amount of allowed loops */
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"sub r9, r9, r1, lsl #2 \n" /* r1 words will be written in following loop */
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"subs r1, r1, #2 \n"
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".fifo_loop_2: \n"
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"ldmgeia r8!, {r2, r12} \n" /* load four samples */
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"strge r2 , [r10, %[wr]] \n" /* write sample 0-1 to IISFIFO_WR */
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"strge r12, [r10, %[wr]] \n" /* write sample 2-3 to IISFIFO_WR */
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"subges r1, r1, #2 \n" /* one more loop? */
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"bge .fifo_loop_2 \n" /* yes, continue */
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"tst r1, #1 \n" /* two samples (one word) left? */
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"ldrne r12, [r8], #4 \n" /* load two samples */
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"strne r12, [r10, %[wr]] \n" /* write sample 0-1 to IISFIFO_WR */
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"cmp r9, #0 \n" /* either FIFO is full or source buffer is empty */
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"bgt .exit \n" /* if source buffer is not empty, FIFO must be full */
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#elif SAMPLE_SIZE == 32
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".check_fifo: \n"
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"ldr r0, [r10, %[cfg]] \n" /* read IISFIFO_CFG to check FIFO status */
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"and r0, r0, %[mask] \n" /* r0 = IIS_TX_FREE_COUNT << 23 (PP5002) */
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"movs r1, r0, lsr #24 \n" /* number of free pairs of FIFO slots */
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"beq .exit \n" /* no complete pair? -> exit */
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"cmp r1, r9, lsr #2 \n" /* number of words from source */
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"movgt r1, r9, lsr #2 \n" /* r1 = amount of allowed loops */
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"sub r9, r9, r1, lsl #2 \n" /* r1 words will be written in following loop */
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".fifo_loop: \n"
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"ldr r12, [r8], #4 \n" /* load two samples */
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"mov r2 , r12, lsl #16 \n" /* put left sample at the top bits */
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"str r2 , [r10, %[wr]] \n" /* write top sample to IISFIFO_WR */
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"str r12, [r10, %[wr]] \n" /* write low sample to IISFIFO_WR*/
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"subs r1, r1, #1 \n" /* one more loop? */
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"bgt .fifo_loop \n" /* yes, continue */
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"cmp r9, #0 \n" /* either FIFO is full or source buffer is empty */
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"bgt .exit \n" /* if source buffer is not empty, FIFO must be full */
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#endif
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".more_data: \n"
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"ldr r2, =pcm_callback_for_more \n"
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"ldr r2, [r2] \n" /* get callback address */
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"cmp r2, #0 \n" /* check for null pointer */
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"stmneia r11, { r8-r9 } \n" /* save internal copies of variables back */
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"movne r0, r11 \n" /* r0 = &p */
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"addne r1, r11, #4 \n" /* r1 = &size */
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"movne lr, pc \n" /* call pcm_callback_for_more */
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"bxne r2 \n"
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"ldmia r11, { r8-r9 } \n" /* reload p and size */
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"cmp r9, #0 \n" /* did we actually get more data? */
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"bne .check_fifo \n"
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"ldr r12, =pcm_play_dma_stop \n"
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"mov lr, pc \n"
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"bx r12 \n"
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"ldr r12, =pcm_play_dma_stopped_callback \n"
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"mov lr, pc \n"
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"bx r12 \n"
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".exit: \n" /* (r8=0 if stopping, look above) */
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"stmia r11, { r8-r9 } \n" /* save p and size */
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"ldmfd sp!, { r0-r3, lr } \n"
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"subs pc, lr, #4 \n" /* FIQ specific return sequence */
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".ltorg \n"
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: /* These must only be integers! No regs */
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: [mask]"i"(IIS_TX_FREE_MASK),
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[cfg]"i"((int)&IISFIFO_CFG - (int)&IISCONFIG),
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[wr]"i"((int)&IISFIFO_WR - (int)&IISCONFIG)
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);
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}
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#else /* C version for reference */
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void fiq_playback(void) __attribute__((interrupt ("FIQ"))) ICODE_ATTR;
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/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
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void fiq_playback(void)
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{
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register pcm_more_callback_type get_more;
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#if CONFIG_CPU == PP5002
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inl(0xcf001040);
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#endif
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do {
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while (dma_play_data.size > 0) {
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if (IIS_TX_FREE_COUNT < 2) {
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return;
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}
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#if SAMPLE_SIZE == 16
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IISFIFO_WR = *dma_play_data.p++;
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#elif SAMPLE_SIZE == 32
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IISFIFO_WR = *dma_play_data.p++ << 16;
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IISFIFO_WR = *dma_play_data.p++ << 16;
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#endif
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dma_play_data.size -= 4;
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}
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/* p is empty, get some more data */
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get_more = pcm_callback_for_more;
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if (get_more) {
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get_more((unsigned char**)&dma_play_data.p,
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&dma_play_data.size);
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}
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} while (dma_play_data.size);
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/* No more data, so disable the FIFO/interrupt */
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pcm_play_dma_stop();
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pcm_play_dma_stopped_callback();
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}
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#endif /* ASM / C selection */
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/* For the locks, FIQ must be disabled because the handler manipulates
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IISCONFIG and the operation is not atomic - dual core support
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will require other measures */
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void pcm_play_lock(void)
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{
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int status = disable_fiq_save();
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if (++dma_play_data.locked == 1) {
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IIS_IRQTX_REG &= ~IIS_IRQTX;
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}
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restore_fiq(status);
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}
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void pcm_play_unlock(void)
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{
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int status = disable_fiq_save();
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if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
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IIS_IRQTX_REG |= IIS_IRQTX;
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}
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restore_fiq(status);
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}
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static void play_start_pcm(void)
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{
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fiq_function = fiq_playback;
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pcm_apply_settings();
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IISCONFIG &= ~IIS_TXFIFOEN; /* Stop transmitting */
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dma_play_data.state = 1;
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/* Fill the FIFO or start when data is used up */
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while (1) {
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if (IIS_TX_FREE_COUNT < 2 || dma_play_data.size == 0) {
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IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
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return;
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}
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#if SAMPLE_SIZE == 16
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IISFIFO_WR = *dma_play_data.p++;
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#elif SAMPLE_SIZE == 32
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IISFIFO_WR = *dma_play_data.p++ << 16;
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IISFIFO_WR = *dma_play_data.p++ << 16;
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#endif
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dma_play_data.size -= 4;
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}
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}
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static void play_stop_pcm(void)
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{
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/* Disable TX interrupt */
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IIS_IRQTX_REG &= ~IIS_IRQTX;
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dma_play_data.state = 0;
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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dma_play_data.p = (void *)(((uintptr_t)addr + 2) & ~3);
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dma_play_data.size = (size & ~3);
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#if NUM_CORES > 1
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/* This will become more important later - and different ! */
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dma_play_data.core = processor_id(); /* save initiating core */
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#endif
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CPU_INT_PRIORITY |= IIS_MASK; /* FIQ priority for I2S */
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CPU_INT_EN = IIS_MASK;
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play_start_pcm();
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}
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/* Stops the DMA transfer and interrupt */
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void pcm_play_dma_stop(void)
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{
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play_stop_pcm();
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dma_play_data.size = 0;
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#if NUM_CORES > 1
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dma_play_data.core = 0; /* no core in control */
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#endif
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}
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void pcm_play_dma_pause(bool pause)
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{
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if (pause) {
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play_stop_pcm();
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} else {
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play_start_pcm();
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}
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return dma_play_data.size & ~3;
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}
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void pcm_play_dma_init(void)
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{
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pcm_set_frequency(SAMPR_44);
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/* Initialize default register values. */
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audiohw_init();
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#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751)
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/* Power on */
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audiohw_enable_output(true);
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/* Unmute the master channel (DAC should be at zero point now). */
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audiohw_mute(false);
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#endif
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dma_play_data.size = 0;
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#if NUM_CORES > 1
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dma_play_data.core = 0; /* no core in control */
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#endif
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IISCONFIG |= IIS_TXFIFOEN;
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}
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void pcm_postinit(void)
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{
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audiohw_postinit();
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pcm_apply_settings();
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}
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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unsigned long addr = (unsigned long)dma_play_data.p;
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size_t cnt = dma_play_data.size;
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*count = cnt >> 2;
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return (void *)((addr + 2) & ~3);
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}
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/****************************************************************************
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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/* PCM recording interrupt routine lockout */
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static struct dma_data dma_rec_data SHAREDBSS_ATTR =
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{
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/* Initialize to a locked, stopped state */
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.p = NULL,
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.size = 0,
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#if NUM_CORES > 1
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.core = 0x00,
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#endif
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.locked = 0,
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.state = 0
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};
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/* For the locks, FIQ must be disabled because the handler manipulates
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IISCONFIG and the operation is not atomic - dual core support
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will require other measures */
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void pcm_rec_lock(void)
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{
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int status = disable_fiq_save();
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if (++dma_rec_data.locked == 1)
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IIS_IRQRX_REG &= ~IIS_IRQRX;
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restore_fiq(status);
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}
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void pcm_rec_unlock(void)
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{
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int status = disable_fiq_save();
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if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0)
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IIS_IRQRX_REG |= IIS_IRQRX;
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restore_fiq(status);
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}
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/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
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void fiq_record(void) ICODE_ATTR __attribute__((interrupt ("FIQ")));
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#if defined(SANSA_C200) || defined(SANSA_E200)
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void fiq_record(void)
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{
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register pcm_more_callback_type2 more_ready;
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register int32_t value;
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if (audio_channels == 2) {
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/* RX is stereo */
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while (dma_rec_data.size > 0) {
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if (IIS_RX_FULL_COUNT < 2) {
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return;
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}
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/* Discard every other sample since ADC clock is 1/2 LRCK */
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value = IISFIFO_RD;
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IISFIFO_RD;
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*dma_rec_data.p++ = value;
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dma_rec_data.size -= 4;
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/* TODO: Figure out how to do IIS loopback */
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if (audio_output_source != AUDIO_SRC_PLAYBACK) {
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if (IIS_TX_FREE_COUNT >= 16) {
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/* Resync the output FIFO - it ran dry */
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IISFIFO_WR = 0;
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IISFIFO_WR = 0;
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}
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IISFIFO_WR = value;
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IISFIFO_WR = value;
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}
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}
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}
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else {
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/* RX is left channel mono */
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while (dma_rec_data.size > 0) {
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if (IIS_RX_FULL_COUNT < 2) {
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return;
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}
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/* Discard every other sample since ADC clock is 1/2 LRCK */
|
|
value = IISFIFO_RD;
|
|
IISFIFO_RD;
|
|
|
|
value = (uint16_t)value | (value << 16);
|
|
|
|
*dma_rec_data.p++ = value;
|
|
dma_rec_data.size -= 4;
|
|
|
|
if (audio_output_source != AUDIO_SRC_PLAYBACK) {
|
|
if (IIS_TX_FREE_COUNT >= 16) {
|
|
/* Resync the output FIFO - it ran dry */
|
|
IISFIFO_WR = 0;
|
|
IISFIFO_WR = 0;
|
|
}
|
|
|
|
value = *((int32_t *)dma_rec_data.p - 1);
|
|
IISFIFO_WR = value;
|
|
IISFIFO_WR = value;
|
|
}
|
|
}
|
|
}
|
|
|
|
more_ready = pcm_callback_more_ready;
|
|
|
|
if (more_ready == NULL || more_ready(0) < 0) {
|
|
/* Finished recording */
|
|
pcm_rec_dma_stop();
|
|
pcm_rec_dma_stopped_callback();
|
|
}
|
|
}
|
|
|
|
#else
|
|
void fiq_record(void)
|
|
{
|
|
register pcm_more_callback_type2 more_ready;
|
|
|
|
while (dma_rec_data.size > 0) {
|
|
if (IIS_RX_FULL_COUNT < 2) {
|
|
return;
|
|
}
|
|
|
|
#if SAMPLE_SIZE == 16
|
|
*dma_rec_data.p++ = IISFIFO_RD;
|
|
#elif SAMPLE_SIZE == 32
|
|
*dma_rec_data.p++ = IISFIFO_RD >> 16;
|
|
*dma_rec_data.p++ = IISFIFO_RD >> 16;
|
|
#endif
|
|
dma_rec_data.size -= 4;
|
|
}
|
|
|
|
more_ready = pcm_callback_more_ready;
|
|
|
|
if (more_ready == NULL || more_ready(0) < 0) {
|
|
/* Finished recording */
|
|
pcm_rec_dma_stop();
|
|
pcm_rec_dma_stopped_callback();
|
|
}
|
|
}
|
|
|
|
#endif /* SANSA_E200 */
|
|
|
|
/* Continue transferring data in */
|
|
void pcm_record_more(void *start, size_t size)
|
|
{
|
|
pcm_rec_peak_addr = start; /* Start peaking at dest */
|
|
dma_rec_data.p = start; /* Start of RX buffer */
|
|
dma_rec_data.size = size; /* Bytes to transfer */
|
|
}
|
|
|
|
void pcm_rec_dma_stop(void)
|
|
{
|
|
/* disable interrupt */
|
|
IIS_IRQRX_REG &= ~IIS_IRQRX;
|
|
|
|
dma_rec_data.state = 0;
|
|
dma_rec_data.size = 0;
|
|
#if NUM_CORES > 1
|
|
dma_rec_data.core = 0x00;
|
|
#endif
|
|
|
|
/* disable fifo */
|
|
IISCONFIG &= ~IIS_RXFIFOEN;
|
|
IISFIFO_CFG |= IIS_RXCLR;
|
|
}
|
|
|
|
void pcm_rec_dma_start(void *addr, size_t size)
|
|
{
|
|
pcm_rec_dma_stop();
|
|
|
|
pcm_rec_peak_addr = addr;
|
|
dma_rec_data.p = addr;
|
|
dma_rec_data.size = size;
|
|
#if NUM_CORES > 1
|
|
/* This will become more important later - and different ! */
|
|
dma_rec_data.core = processor_id(); /* save initiating core */
|
|
#endif
|
|
/* setup FIQ handler */
|
|
fiq_function = fiq_record;
|
|
|
|
/* interrupt on full fifo, enable record fifo interrupt */
|
|
dma_rec_data.state = 1;
|
|
|
|
/* enable RX FIFO */
|
|
IISCONFIG |= IIS_RXFIFOEN;
|
|
|
|
/* enable IIS interrupt as FIQ */
|
|
CPU_INT_PRIORITY |= IIS_MASK;
|
|
CPU_INT_EN = IIS_MASK;
|
|
}
|
|
|
|
void pcm_rec_dma_close(void)
|
|
{
|
|
pcm_rec_dma_stop();
|
|
} /* pcm_close_recording */
|
|
|
|
void pcm_rec_dma_init(void)
|
|
{
|
|
#if defined(IPOD_COLOR) || defined (IPOD_4G)
|
|
/* The usual magic from IPL - I'm guessing this configures the headphone
|
|
socket to be input or output - in this case, input. */
|
|
GPIOI_OUTPUT_VAL &= ~0x40;
|
|
GPIOA_OUTPUT_VAL &= ~0x4;
|
|
#endif
|
|
|
|
pcm_rec_dma_stop();
|
|
} /* pcm_init */
|
|
|
|
const void * pcm_rec_dma_get_peak_buffer(int *count)
|
|
{
|
|
unsigned long addr = (unsigned long)pcm_rec_peak_addr;
|
|
unsigned long end = (unsigned long)dma_rec_data.p;
|
|
*count = (end >> 2) - (addr >> 2);
|
|
return (void *)(addr & ~3);
|
|
} /* pcm_rec_dma_get_peak_buffer */
|
|
|
|
#endif /* HAVE_RECORDING */
|