rockbox/firmware/target/mips/ingenic_x1000/x1000/intc.h
Aidan MacDonald 3ec66893e3 New port: FiiO M3K on bare metal
Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
2021-03-28 00:01:37 +00:00

57 lines
2.3 KiB
C

/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_INTC_H__
#define __HEADERGEN_INTC_H__
#include "macro.h"
#define REG_INTC_SRC(_n1) jz_reg(INTC_SRC(_n1))
#define JA_INTC_SRC(_n1) (0xb0001000 + 0x0 + (_n1) * 0x20)
#define JT_INTC_SRC(_n1) JIO_32_RW
#define JN_INTC_SRC(_n1) INTC_SRC
#define JI_INTC_SRC(_n1) (_n1)
#define REG_INTC_MSK(_n1) jz_reg(INTC_MSK(_n1))
#define JA_INTC_MSK(_n1) (0xb0001000 + 0x4 + (_n1) * 0x20)
#define JT_INTC_MSK(_n1) JIO_32_RW
#define JN_INTC_MSK(_n1) INTC_MSK
#define JI_INTC_MSK(_n1) (_n1)
#define REG_INTC_MSK_SET(_n1) jz_reg(INTC_MSK_SET(_n1))
#define JA_INTC_MSK_SET(_n1) (JA_INTC_MSK(_n1) + 0x4)
#define JT_INTC_MSK_SET(_n1) JIO_32_WO
#define JN_INTC_MSK_SET(_n1) INTC_MSK
#define JI_INTC_MSK_SET(_n1) (_n1)
#define REG_INTC_MSK_CLR(_n1) jz_reg(INTC_MSK_CLR(_n1))
#define JA_INTC_MSK_CLR(_n1) (JA_INTC_MSK(_n1) + 0x8)
#define JT_INTC_MSK_CLR(_n1) JIO_32_WO
#define JN_INTC_MSK_CLR(_n1) INTC_MSK
#define JI_INTC_MSK_CLR(_n1) (_n1)
#define REG_INTC_PND(_n1) jz_reg(INTC_PND(_n1))
#define JA_INTC_PND(_n1) (0xb0001000 + 0x10 + (_n1) * 0x20)
#define JT_INTC_PND(_n1) JIO_32_RW
#define JN_INTC_PND(_n1) INTC_PND
#define JI_INTC_PND(_n1) (_n1)
#endif /* __HEADERGEN_INTC_H__*/