28c89386af
- Proper error codes are now returned from all functions. These codes will be used by a host-side flash tool for error reporting. - nand_erase_block() was replaced by nand_erase_bytes(). The caller can't know how big an eraseblock is with the current API, so next best thing is to verify the correct alignment inside the call and reject the erase if it isn't properly aligned. - Fixed typo in nandcmd_block_erase() which would cause an SFC error to be interpreted as success. Yikes. Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
214 lines
8.5 KiB
C
214 lines
8.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __NAND_X1000_H__
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#define __NAND_X1000_H__
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/* NOTE: this is a very minimal API designed only to support a bootloader.
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* Not suitable for general data storage. It doesn't have proper support for
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* partial page writes, access to spare area, etc, which are all necessary
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* for an effective flash translation layer.
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "nand-x1000-err.h"
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/* Chip supports quad I/O for page read/write */
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#define NANDCHIP_FLAG_QUAD 0x01
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/* Set/clear the BRWD bit when enabling/disabling write protection */
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#define NANDCHIP_FLAG_USE_BRWD 0x02
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typedef struct nand_drv nand_drv;
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/* Defines some static information about a NAND chip */
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typedef struct nand_chip_data {
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const char* name; /* Name for debugging purposes */
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uint8_t mf_id; /* Manufacturer ID */
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uint8_t dev_id; /* Device ID */
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uint8_t rowaddr_width; /* Number of bytes in row addresses */
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uint8_t coladdr_width; /* Number of bytes in column addresses */
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uint32_t dev_conf; /* Value to write to SFC_DEV_CONF register */
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uint32_t clock_freq; /* Frequency to switch to after identification */
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uint32_t block_size; /* Number of pages per eraseblock */
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uint32_t page_size; /* Number of data bytes per page */
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uint32_t spare_size; /* Number of spare bytes per page */
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int flags; /* Various flags */
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} nand_chip_data;
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/* Defines high-level operations used to implement the public API.
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* Chips may need to override operations if the default ones aren't suitable.
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*
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* Negative return codes return an error, while zero or positive codes are
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* considered successful. This allows a function to return meaningful data,
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* if applicable.
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*/
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typedef struct nand_chip_ops {
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/* Called once after identifying the chip */
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int(*open)(nand_drv* d);
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/* Called once when the driver is closed */
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void(*close)(nand_drv* d);
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/* Read or write a complete page including both main and spare areas. */
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int(*read_page)(nand_drv* d, uint32_t rowaddr, unsigned char* buf);
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int(*write_page)(nand_drv* d, uint32_t rowaddr, const unsigned char* buf);
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/* Erase a block. */
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int(*erase_block)(nand_drv* d, uint32_t blockaddr);
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/* Enable or disable the chip's write protection. */
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int(*set_wp_enable)(nand_drv* d, bool en);
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/* Perform error correction and detection on a raw page (main + spare).
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* Return the number of errors detected and corrected, or a negative value
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* if errors were detected but could not be corrected.
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*/
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int(*ecc_read)(nand_drv* d, unsigned char* buf);
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/* Generate ECC data for a page. The buffer main area is already filled
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* and this function should write ECC data into the spare area.
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*/
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void(*ecc_write)(nand_drv* d, unsigned char* buf);
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} nand_chip_ops;
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/* Struct used to list all supported NAND chips in an array */
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typedef struct nand_chip_desc {
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const nand_chip_data* data;
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const nand_chip_ops* ops;
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} nand_chip_desc;
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/* NAND driver structure. It can be accessed by chip ops, but they must not
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* modify any fields except for "auxbuf", which is a small buffer that can
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* be used for commands that need to read/write small amounts of data: often
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* needed for polling status, etc.
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*/
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struct nand_drv {
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const nand_chip_ops* chip_ops;
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const nand_chip_data* chip_data;
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unsigned char* pagebuf;
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unsigned char* auxbuf;
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uint32_t raw_page_size;
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int flags;
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};
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/* Note: sfc_init() must be called prior to nand_open() */
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extern int nand_open(void);
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extern void nand_close(void);
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/* Controls device-side write protection registers as well as software lock.
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* Erase and program operations will fail unless you first enable writes.
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*/
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extern int nand_enable_writes(bool en);
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/* Byte-based NAND operations */
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extern int nand_read_bytes(uint32_t byteaddr, int count, void* buf);
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extern int nand_write_bytes(uint32_t byteaddr, int count, const void* buf);
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extern int nand_erase_bytes(uint32_t byteaddr, int count);
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/* NAND command numbers */
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#define NAND_CMD_READ_ID 0x9f
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#define NAND_CMD_WRITE_ENABLE 0x06
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#define NAND_CMD_GET_FEATURE 0x0f
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#define NAND_CMD_SET_FEATURE 0x1f
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#define NAND_CMD_PAGE_READ_TO_CACHE 0x13
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#define NAND_CMD_READ_FROM_CACHE 0x0b
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#define NAND_CMD_READ_FROM_CACHEx4 0x6b
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#define NAND_CMD_PROGRAM_LOAD 0x02
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#define NAND_CMD_PROGRAM_LOADx4 0x32
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#define NAND_CMD_PROGRAM_EXECUTE 0x10
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#define NAND_CMD_BLOCK_ERASE 0xd8
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/* NAND device register addresses for GET_FEATURE / SET_FEATURE */
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#define NAND_FREG_PROTECTION 0xa0
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#define NAND_FREG_FEATURE 0xb0
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#define NAND_FREG_STATUS 0xc0
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/* Protection register bits */
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#define NAND_FREG_PROTECTION_BRWD 0x80
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#define NAND_FREG_PROTECTION_BP2 0x20
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#define NAND_FREG_PROTECTION_BP1 0x10
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#define NAND_FREG_PROTECTION_BP0 0x80
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/* Mask of BP bits 0-2 */
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#define NAND_FREG_PROTECTION_ALLBP (0x38)
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/* Feature register bits */
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#define NAND_FREG_FEATURE_QE 0x01
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/* Status register bits */
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#define NAND_FREG_STATUS_OIP 0x01
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#define NAND_FREG_STATUS_WEL 0x02
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#define NAND_FREG_STATUS_E_FAIL 0x04
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#define NAND_FREG_STATUS_P_FAIL 0x08
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/* Standard implementations for low-level NAND commands. I'm not aware of any
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* actual standard governing these, but it seems many vendors follow the same
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* command numbering, status bits, and behavior so these implementations should
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* work across a wide variety of chips.
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*
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* If adding a new NAND chip which only has a minor deviation from these
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* standard implementations, consider adding a flag and modifying these
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* functions to change their behavior based on the flag, instead of writing
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* a whole new implementation.
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*
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* None of these functions are directly called by the high-level driver code,
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* except for nandcmd_std_read_id(). They can be used to implement higher-level
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* functions in a device's "nand_chip_ops".
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*/
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extern int nandcmd_read_id(nand_drv* d);
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extern int nandcmd_write_enable(nand_drv* d);
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extern int nandcmd_get_feature(nand_drv* d, int reg);
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extern int nandcmd_set_feature(nand_drv* d, int reg, int val);
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extern int nandcmd_page_read_to_cache(nand_drv* d, uint32_t rowaddr);
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extern int nandcmd_read_from_cache(nand_drv* d, unsigned char* buf);
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extern int nandcmd_program_load(nand_drv* d, const unsigned char* buf);
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extern int nandcmd_program_execute(nand_drv* d, uint32_t rowaddr);
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extern int nandcmd_block_erase(nand_drv* d, uint32_t blockaddr);
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/* Table filled with all the standard operations for chips which don't
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* need to override any operations.
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*/
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extern const nand_chip_ops nand_chip_ops_std;
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/* Standard NAND chip ops based on the standard "nandcmd" functions.
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*
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* Same advice applies here as there: if it's possible to support minor
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* chip variations with a flag, modify these functions to do so.
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*/
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extern int nandop_std_open(nand_drv* d);
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extern void nandop_std_close(nand_drv* d);
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extern int nandop_std_read_page(nand_drv* d, uint32_t rowaddr, unsigned char* buf);
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extern int nandop_std_write_page(nand_drv* d, uint32_t rowaddr, const unsigned char* buf);
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extern int nandop_std_erase_block(nand_drv* d, uint32_t blockaddr);
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extern int nandop_std_set_wp_enable(nand_drv* d, bool en);
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/* The default ECC implementation is a no-op: reads always succeed without
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* reporting errors and writes will fill the spare area with '0xff' bytes.
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*
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* For chips that support internal ECC, this often works because the chip will
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* ignore writes to the ECC areas.
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*/
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extern int nandop_ecc_none_read(nand_drv* d, unsigned char* buf);
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extern void nandop_ecc_none_write(nand_drv* d, unsigned char* buf);
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#endif /* __NAND_X1000_H__ */
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