355 lines
9 KiB
C
355 lines
9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "gcc_extensions.h"
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#include "panic.h"
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#include "avic-imx31.h"
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#include "gpio-imx31.h"
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#include "mmu-imx31.h"
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#include "system-target.h"
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#include "powermgmt.h"
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#include "lcd.h"
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#include "serial-imx31.h"
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#include "debug.h"
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#include "ccm-imx31.h"
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#include "mc13783.h"
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#include "dvfs_dptc-imx31.h"
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static unsigned long product_rev;
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static unsigned long system_rev;
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/** IC revision info routines **/
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unsigned int iim_system_rev(void)
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{
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return system_rev & IIM_SREV_SREV;
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}
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unsigned int iim_prod_rev(void)
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{
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return product_rev;
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}
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static void INIT_ATTR iim_init(void)
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{
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/* Initialize the IC revision info (required by SDMA) */
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ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT);
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product_rev = IIM_PREV;
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system_rev = IIM_SREV;
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}
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/** Watchdog timer routines **/
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/* Initialize the watchdog timer */
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void watchdog_init(unsigned int half_seconds)
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{
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uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) |
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WDOG_WCR_WOE | /* WDOG output enabled */
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WDOG_WCR_WDA | /* WDOG assertion - no effect */
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WDOG_WCR_SRS | /* System reset - no effect */
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WDOG_WCR_WRE; /* Generate a WDOG signal */
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ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
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WDOG_WCR = wcr;
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WDOG_WSR = 0x5555;
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WDOG_WCR = wcr | WDOG_WCR_WDE; /* Enable timer - hardware does
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not allow a disable now */
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WDOG_WSR = 0xaaaa;
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}
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/* Service the watchdog timer */
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void watchdog_service(void)
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{
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WDOG_WSR = 0x5555;
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WDOG_WSR = 0xaaaa;
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}
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/** uevent APIs **/
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static uevent_cb_type ucallback = NULL; /* uevent callback */
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static void cancel_uevent(void)
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{
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GPTSR = GPTSR_OF1;
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GPTIR &= ~GPTIR_OF1IE;
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ucallback = NULL;
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}
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static void __attribute__((interrupt("IRQ"))) GPT_HANDLER(void)
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{
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uevent_cb_type cb = ucallback;
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cancel_uevent();
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cb();
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}
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void uevent(unsigned long usecs, uevent_cb_type callback)
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{
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if (!callback || ucallback)
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return; /* Is busy */
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unsigned long status = disable_interrupt_save(IRQ_FIQ_STATUS);
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ucallback = callback;
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for (int i = 0; i < 1; i++)
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{
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unsigned long utime = GPTCNT;
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unsigned long time = utime + usecs + 1;
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GPTOCR1 = time;
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GPTSR = GPTSR_OF1;
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GPTIR |= GPTIR_OF1IE;
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if (TIME_BEFORE(GPTCNT, time))
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break; /* Didn't miss it */
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}
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restore_interrupt(status);
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}
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void uevent_cancel(void)
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{
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unsigned long status = disable_interrupt_save(IRQ_FIQ_STATUS);
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if (ucallback)
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cancel_uevent();
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restore_interrupt(status);
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}
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/** GPT timer routines - basis for udelay/uevent **/
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/* Start the general-purpose timer (1MHz) */
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void gpt_start(void)
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{
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ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
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unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000;
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GPTCR &= ~GPTCR_EN; /* Disable counter */
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GPTCR |= GPTCR_SWR; /* Reset module */
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while (GPTCR & GPTCR_SWR);
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/* No output
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* No capture
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* Enable in wait and run mode
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* Freerun mode (count to 0xFFFFFFFF and roll-over to 0x00000000)
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*/
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GPTCR = GPTCR_FRR | GPTCR_WAITEN | GPTCR_CLKSRC_IPG_CLK;
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GPTPR = ipg_mhz - 1;
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GPTSR = GPTSR_OF1;
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GPTCR |= GPTCR_EN;
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avic_enable_int(INT_GPT, INT_TYPE_IRQ, INT_PRIO_GPT, GPT_HANDLER);
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}
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/* Stop the general-purpose timer */
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void gpt_stop(void)
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{
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unsigned long status = disable_interrupt_save(IRQ_FIQ_STATUS);
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avic_disable_int(INT_GPT);
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cancel_uevent();
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GPTCR &= ~GPTCR_EN;
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restore_interrupt(status);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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void system_halt(void)
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{
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disable_interrupt(IRQ_FIQ_STATUS);
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avic_set_ni_level(AVIC_NIL_DISABLE);
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while (1)
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core_idle();
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}
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void system_reboot(void)
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{
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/* Multi-context so no SPI available (WDT?) */
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system_halt();
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}
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void system_exception_wait(void)
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{
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/* Called in many contexts so button reading may be a chore */
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system_halt();
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}
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void INIT_ATTR system_init(void)
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{
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static const enum IMX31_CG_LIST disable_clocks[] INITDATA_ATTR =
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{
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/* CGR0 */
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CG_SD_MMC1,
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CG_SD_MMC2,
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CG_IIM,
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CG_SDMA,
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CG_CSPI3,
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CG_RNG,
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CG_UART1,
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CG_UART2,
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CG_SSI1,
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CG_I2C1,
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CG_I2C2,
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CG_I2C3,
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/* CGR1 */
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CG_HANTRO,
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CG_MEMSTICK1,
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CG_MEMSTICK2,
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CG_CSI,
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CG_RTC,
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CG_WDOG,
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CG_PWM,
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CG_SIM,
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CG_ECT,
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CG_USBOTG,
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CG_KPP,
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CG_UART3,
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CG_UART4,
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CG_UART5,
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CG_1_WIRE,
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/* CGR2 */
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CG_SSI2,
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CG_CSPI1,
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CG_CSPI2,
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CG_GACC,
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CG_RTIC,
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CG_FIR
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};
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unsigned int i;
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/* Initialize frequency with current */
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cpu_frequency = ccm_get_mcu_clk();
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/* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
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bitclr32(&CCM_CCMR, CCM_CCMR_LPM);
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iim_init();
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bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
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bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
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bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
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bitclr32(&UCR1_1, EUARTUCR1_UARTEN);
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bitclr32(&UCR1_2, EUARTUCR1_UARTEN);
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bitclr32(&UCR1_3, EUARTUCR1_UARTEN);
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bitclr32(&UCR1_4, EUARTUCR1_UARTEN);
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bitclr32(&UCR1_5, EUARTUCR1_UARTEN);
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for (i = 0; i < ARRAYLEN(disable_clocks); i++)
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ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
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avic_init();
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gpt_start();
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gpio_init();
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}
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void system_prepare_fw_start(void)
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{
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dvfs_stop();
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dptc_stop();
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mc13783_close();
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tick_stop();
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disable_interrupt(IRQ_FIQ_STATUS);
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avic_set_ni_level(AVIC_NIL_DISABLE);
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}
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#ifndef BOOTLOADER
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void rolo_restart_firmware(const unsigned char *source, unsigned char *dest,
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int length) NORETURN_ATTR;
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void NORETURN_ATTR
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rolo_restart(const unsigned char *source, unsigned char *dest, int length)
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{
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/* Some housekeeping tasks must be performed for a safe changeover */
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charging_algorithm_close();
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system_prepare_fw_start();
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/* Copying routine where new image is run */
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rolo_restart_firmware(source, dest, length);
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}
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#endif /* BOOTLOADER */
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void dumpregs(void)
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{
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asm volatile ("mov %0,r0\n\t"
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"mov %1,r1\n\t"
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"mov %2,r2\n\t"
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"mov %3,r3":
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"=r"(regs.r0),"=r"(regs.r1),
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"=r"(regs.r2),"=r"(regs.r3):);
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asm volatile ("mov %0,r4\n\t"
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"mov %1,r5\n\t"
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"mov %2,r6\n\t"
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"mov %3,r7":
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"=r"(regs.r4),"=r"(regs.r5),
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"=r"(regs.r6),"=r"(regs.r7):);
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asm volatile ("mov %0,r8\n\t"
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"mov %1,r9\n\t"
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"mov %2,r10\n\t"
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"mov %3,r12":
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"=r"(regs.r8),"=r"(regs.r9),
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"=r"(regs.r10),"=r"(regs.r11):);
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asm volatile ("mov %0,r12\n\t"
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"mov %1,sp\n\t"
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"mov %2,lr\n\t"
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"mov %3,pc\n"
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"sub %3,%3,#8":
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"=r"(regs.r12),"=r"(regs.sp),
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"=r"(regs.lr),"=r"(regs.pc):);
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#ifdef HAVE_SERIAL
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dprintf("Register Dump :\n");
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dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
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dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
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dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
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dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
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//dprintf("CPSR=0x%x\t\n",regs.cpsr);
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#endif
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DEBUGF("Register Dump :\n");
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DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
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DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
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DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
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DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
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//DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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(void)freqency;
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}
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#endif
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