225 lines
6.3 KiB
ArmAsm
225 lines
6.3 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2008 by Marcoen Hirschberg
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* Copyright (C) 2008 by Denes Balatoni
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* Copyright (C) 2010 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#define ASM
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#include "config.h"
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#include "cpu.h"
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.global start
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.global entry_point
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/* Exception vectors */
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.section .intvect,"ax",%progbits
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ldr pc, =start
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ldr pc, =undef_instr_handler
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ldr pc, =software_int_handler
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ldr pc, =prefetch_abort_handler
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ldr pc, =data_abort_handler
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ldr pc, =reserved_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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.ltorg
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.text
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start:
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifdef BOOTLOADER
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sub r4, pc, #12 /* copy running address, accomodate
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* for prefetch (-8) and msr instr (-4)
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*/
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ldr r0, =0xefff0000 /* cache controler base address */
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ldrh r1, [r0]
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strh r1, [r0] /* global cache disable */
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ldr r2, =_relocstart
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ldr r3, =_relocend
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cmp r2, r4
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beq entry_point /* skip copying if we are in place already */
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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entry_point_jmp:
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ldr pc, =entry_point
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#endif
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entry_point:
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mov r0, #0x18000000
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add r0, r0, #0x1c000
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/* setup ARM core freq = 200MHz
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* AHB bus freq (HCLK) = 100MHz
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* APB bus freq (PCLK) = 50MHz
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* Note: it seems there is no way to run AHB bus at ARM freq
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* bit2 in DIVCON1 must have different meaning to what datasheet
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* states. It influences SDRAM read speed but does not change
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* APB freq
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*/
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ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
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bic r1, r1, #0x1f
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orr r1, r1, #9 /* ((1<<3)|(1<<0)) ARM slow mode, HCLK:PCLK = 2:1 */
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str r1, [r0,#0x14]
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ldr r1,=0x1850310 /* ((1<<24)|(1<<23)|(5<<16)|(49<<4)) */
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str r1, [r0,#0x08]
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ldr r2,=0x40000
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1:
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ldr r1, [r0,#0x2c] /* SCU_STATUS */
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tst r1, #1 /* ARM pll lock */
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bne 1f
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subs r2, r2, #1
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bne 1b
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1:
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ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
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bic r1, #1 /* leave ARM slow mode */
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str r1, [r0,#0x14]
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#if defined(BOOTLOADER)
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/* remap iram to 0x00000000 */
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ldr r1,=0xdeadbeef
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str r1, [r0, #4]
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#endif
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/* setup caches */
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ldr r0, =0xefff0000 /* cache controler base address */
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ldrh r1, [r0]
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strh r1, [r0] /* global cache disable */
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/* setup uncached regions */
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mov r1, #0x18000000
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orr r1, r1, #0xfe
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str r1, [r0,#0x10] /* MemMapA BUS0IP, 32MB */
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str r1, [r0,#0x14] /* MemMapB BUS0IP, 32MB */
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mov r1, #0x30000000
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orr r1, r1, #0xfe
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str r1, [r0,#0x18] /* MemMapC DSPMEM, 32MB */
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mov r1, #0xee000000 /* 0xefff0000 & 0xfe000000 */
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orr r1, r1, #0xfe
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str r1, [r0,#0x1c] /* MemMapD cache controller, 32MB */
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mov r1, #2 /* invalidate way opcode */
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str r1, [r0,#4] /* invalidate way0 */
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1:
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ldr r2, [r0,#4]
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tst r2, #3
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bne 1b /* wait for invalidate to complete */
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orr r1, r1, #0x80000000
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str r1, [r0,#4] /* invalidate way1 */
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1:
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ldr r2, [r0,#4]
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tst r2, #3
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bne 1b /* wait for invalidate to complete */
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ldr r1, [r0]
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orr r1, r1, #0x80000000
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str r1, [r0] /* global cache enable */
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/* Copy interrupt vectors to iram */
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ldr r2, =_intvectstart
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ldr r3, =_intvectend
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ldr r4, =_intvectcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Initialise bss, ibss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =_irqstackend
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =_fiqstackend
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3
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ldr sp, =_irqstackend
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msr cpsr_c, #0xd7
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ldr sp, =_irqstackend
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msr cpsr_c, #0xdb
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ldr sp, =_irqstackend
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r2, =stackbegin
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ldr r3, =0xdeadbeef
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1:
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cmp sp, r2
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strhi r3, [r2], #4
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bhi 1b
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bl main
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/* All illegal exceptions call into UIE with exception address as first
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* parameter. This is calculated differently depending on which exception
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* we're in. Second parameter is exception number, used for a string lookup
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* in UIE. */
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undef_instr_handler:
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sub r0, lr, #4
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mov r1, #0
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b UIE
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prefetch_abort_handler:
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sub r0, lr, #4
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mov r1, #1
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b UIE
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data_abort_handler:
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sub r0, lr, #8
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mov r1, #2
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b UIE
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/* We run sys mode most of the time, and should never see a software
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* exception being thrown. Make it illegal and call UIE */
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software_int_handler:
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reserved_handler:
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sub r0, lr, #4
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mov r1, #5
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b UIE
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