355 lines
15 KiB
C
355 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SH7034_H__
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#define __SH7034_H__
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#define GBR 0x00000000
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/* register address macros: */
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#define SMR0_ADDR 0x05FFFEC0
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#define BRR0_ADDR 0x05FFFEC1
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#define SCR0_ADDR 0x05FFFEC2
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#define TDR0_ADDR 0x05FFFEC3
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#define SSR0_ADDR 0x05FFFEC4
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#define RDR0_ADDR 0x05FFFEC5
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#define SMR1_ADDR 0x05FFFEC8
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#define BRR1_ADDR 0x05FFFEC9
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#define SCR1_ADDR 0x05FFFECA
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#define TDR1_ADDR 0x05FFFECB
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#define SSR1_ADDR 0x05FFFECC
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#define RDR1_ADDR 0x05FFFECD
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#define ADDRAH_ADDR 0x05FFFEE0
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#define ADDRAL_ADDR 0x05FFFEE1
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#define ADDRBH_ADDR 0x05FFFEE2
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#define ADDRBL_ADDR 0x05FFFEE3
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#define ADDRCH_ADDR 0x05FFFEE4
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#define ADDRCL_ADDR 0x05FFFEE5
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#define ADDRDH_ADDR 0x05FFFEE6
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#define ADDRDL_ADDR 0x05FFFEE7
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#define ADCSR_ADDR 0x05FFFEE8
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#define ADCR_ADDR 0x05FFFEE9
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#define TSTR_ADDR 0x05FFFF00
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#define TSNC_ADDR 0x05FFFF01
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#define TMDR_ADDR 0x05FFFF02
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#define TFCR_ADDR 0x05FFFF03
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#define TCR0_ADDR 0x05FFFF04
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#define TIOR0_ADDR 0x05FFFF05
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#define TIER0_ADDR 0x05FFFF06
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#define TSR0_ADDR 0x05FFFF07
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#define TCNT0_ADDR 0x05FFFF08
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#define GRA0_ADDR 0x05FFFF0A
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#define GRB0_ADDR 0x05FFFF0C
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#define TCR1_ADDR 0x05FFFF0E
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#define TIOR1_ADDR 0x05FFFF0F
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#define TIER1_ADDR 0x05FFFF10
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#define TSR1_ADDR 0x05FFFF11
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#define TCNT1_ADDR 0x05FFFF12
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#define GRA1_ADDR 0x05FFFF14
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#define GRB1_ADDR 0x05FFFF16
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#define TCR2_ADDR 0x05FFFF18
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#define TIOR2_ADDR 0x05FFFF19
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#define TIER2_ADDR 0x05FFFF1A
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#define TSR2_ADDR 0x05FFFF1B
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#define TCNT2_ADDR 0x05FFFF1C
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#define GRA2_ADDR 0x05FFFF1E
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#define GRB2_ADDR 0x05FFFF20
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#define TCR3_ADDR 0x05FFFF22
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#define TIOR3_ADDR 0x05FFFF23
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#define TIER3_ADDR 0x05FFFF24
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#define TSR3_ADDR 0x05FFFF25
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#define TCNT3_ADDR 0x05FFFF26
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#define GRA3_ADDR 0x05FFFF28
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#define GRB3_ADDR 0x05FFFF2A
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#define BRA3_ADDR 0x05FFFF2C
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#define BRB3_ADDR 0x05FFFF2E
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#define TOCR_ADDR 0x05FFFF31
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#define TCR4_ADDR 0x05FFFF32
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#define TIOR4_ADDR 0x05FFFF33
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#define TIER4_ADDR 0x05FFFF34
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#define TSR4_ADDR 0x05FFFF35
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#define TCNT4_ADDR 0x05FFFF36
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#define GRA4_ADDR 0x05FFFF38
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#define GRB4_ADDR 0x05FFFF3A
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#define BRA4_ADDR 0x05FFFF3C
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#define BRB4_ADDR 0x05FFFF3E
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#define SAR0_ADDR 0x05FFFF40
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#define DAR0_ADDR 0x05FFFF44
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#define DMAOR_ADDR 0x05FFFF48
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#define DTCR0_ADDR 0x05FFFF4A
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#define CHCR0_ADDR 0x05FFFF4E
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#define SAR1_ADDR 0x05FFFF50
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#define DAR1_ADDR 0x05FFFF54
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#define DTCR1_ADDR 0x05FFFF5A
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#define CHCR1_ADDR 0x05FFFF5E
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#define SAR2_ADDR 0x05FFFF60
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#define DAR2_ADDR 0x05FFFF64
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#define DTCR2_ADDR 0x05FFFF6A
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#define CHCR2_ADDR 0x05FFFF6E
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#define SAR3_ADDR 0x05FFFF70
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#define DAR3_ADDR 0x05FFFF74
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#define DTCR3_ADDR 0x05FFFF7A
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#define CHCR3_ADDR 0x05FFFF7E
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#define IPRA_ADDR 0x05FFFF84
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#define IPRB_ADDR 0x05FFFF86
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#define IPRC_ADDR 0x05FFFF88
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#define IPRD_ADDR 0x05FFFF8A
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#define IPRE_ADDR 0x05FFFF8C
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#define ICR_ADDR 0x05FFFF8E
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#define BARH_ADDR 0x05FFFF90
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#define BARL_ADDR 0x05FFFF92
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#define BAMRH_ADDR 0x05FFFF94
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#define BAMRL_ADDR 0x05FFFF96
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#define BBR_ADDR 0x05FFFF98
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#define BCR_ADDR 0x05FFFFA0
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#define WCR1_ADDR 0x05FFFFA2
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#define WCR2_ADDR 0x05FFFFA4
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#define WCR3_ADDR 0x05FFFFA6
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#define DCR_ADDR 0x05FFFFA8
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#define PCR_ADDR 0x05FFFFAA
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#define RCR_ADDR 0x05FFFFAC
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#define RTCSR_ADDR 0x05FFFFAE
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#define RTCNT_ADDR 0x05FFFFB0
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#define RTCOR_ADDR 0x05FFFFB2
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#define TCSR_ADDR 0x05FFFFB8
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#define TCNT_ADDR 0x05FFFFB9
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#define RSTCSR_ADDR 0x05FFFFBB
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#define SBYCR_ADDR 0x05FFFFBC
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#define PADR_ADDR 0x05FFFFC0
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#define PBDR_ADDR 0x05FFFFC2
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#define PAIOR_ADDR 0x05FFFFC4
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#define PBIOR_ADDR 0x05FFFFC6
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#define PACR1_ADDR 0x05FFFFC8
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#define PACR2_ADDR 0x05FFFFCA
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#define PBCR1_ADDR 0x05FFFFCC
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#define PBCR2_ADDR 0x05FFFFCE
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#define PCDR_ADDR 0x05FFFFD0
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#define CASCR_ADDR 0x05FFFFEE
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/* Port B data register bits */
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#define PBDR_LCD_SDA 0x0001 /* LCD serial data */
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#define PBDR_LCD_SCK 0x0002 /* LCD serial clock */
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#define PBDR_LCD_DC 0x0004 /* LCD data (1) / command (0) */
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#define PBDR_LCD_CS1 0x0008 /* LCD chip select 1 (active low) */
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#define PBDR_BTN_OFF 0x0010 /* Off button (active low) */
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#define PBDR_LED_RED 0x0040 /* Red LED */
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#define PBDR_BTN_ON 0x0100 /* On button (active low) */
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/* A/D control/status register bits */
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#define ADCSR_CH 0x07 /* Channel/group select */
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#define ADCSR_CKS 0x08 /* Clock select */
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#define ADCSR_SCAN 0x10 /* Scan mode */
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#define ADCSR_ADST 0x20 /* A/D start */
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#define ADCSR_ADIE 0x40 /* A/D interrupt enable */
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#define ADCSR_ADF 0x80 /* A/D end flag */
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/* A/D control register bits */
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#define ADCR_TRGE 0x80 /* Trigger enable */
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/* register macros for direct access: */
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#define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
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#define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
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#define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
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#define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
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#define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
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#define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
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#define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
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#define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
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#define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
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#define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
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#define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
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#define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
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#define ADDRA (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */
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#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
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#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
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#define ADDRB (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */
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#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
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#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
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#define ADDRC (*((volatile unsigned short*)ADDRCJ_ADDR)) /* combined */
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#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
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#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
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#define ADDRD (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */
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#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
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#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
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#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
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#define ADCR (*((volatile unsigned char*)ADCR_ADDR))
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#define TSTR (*((volatile unsigned char*)TSTR_ADDR))
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#define TSNC (*((volatile unsigned char*)TSNC_ADDR))
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#define TMDR (*((volatile unsigned char*)TMDR_ADDR))
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#define TFCR (*((volatile unsigned char*)TFCR_ADDR))
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#define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
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#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
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#define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
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#define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
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#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
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#define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
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#define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
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#define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
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#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
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#define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
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#define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
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#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
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#define GRA1 (*((volatile unsigned short*)GRA1_ADDR))
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#define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
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#define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
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#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
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#define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
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#define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
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#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
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#define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
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#define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
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#define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
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#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
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#define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
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#define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
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#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
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#define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
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#define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
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#define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
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#define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
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#define TOCR (*((volatile unsigned char*)TOCR_ADDR))
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#define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
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#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
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#define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
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#define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
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#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
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#define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
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#define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
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#define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
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#define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
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#define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
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#define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
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#define DMAOR (*((volatile unsigned short*)DMAOR_ADDR))
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#define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR))
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#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
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#define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
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#define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
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#define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR))
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#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
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#define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
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#define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
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#define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR))
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#define HCR2 (*((volatile unsigned short*)CHCR2_ADDR))
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#define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
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#define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
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#define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR))
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#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
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#define IPRA (*((volatile unsigned short*)IPRA_ADDR))
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#define IPRB (*((volatile unsigned short*)IPRB_ADDR))
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#define IPRC (*((volatile unsigned short*)IPRC_ADDR))
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#define IPRD (*((volatile unsigned short*)IPRD_ADDR))
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#define IPRE (*((volatile unsigned short*)IPRE_ADDR))
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#define ICR (*((volatile unsigned short*)ICR_ADDR))
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#define BAR (*((volatile unsigned long*)BARH_ADDR)) /* combined */
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#define BARH (*((volatile unsigned short*)BARH_ADDR))
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#define BARL (*((volatile unsigned short*)BARL_ADDR))
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#define BAMR (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */
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#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
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#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
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#define BBR (*((volatile unsigned short*)BBR_ADDR))
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#define BCR (*((volatile unsigned short*)BCR_ADDR))
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#define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
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#define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
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#define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
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#define DCR (*((volatile unsigned short*)DCR_ADDR))
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#define PCR (*((volatile unsigned short*)PCR_ADDR))
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#define RCR (*((volatile unsigned short*)RCR_ADDR))
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#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
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#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
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#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
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#define TCSR (*((volatile unsigned char*)TCSR_ADDR))
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#define TCNT (*((volatile unsigned char*)TCNT_ADDR))
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#define RSTCSR (*((volatile unsigned char*)RSTCSR_ADDR))
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#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
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#define PADR (*((volatile unsigned short*)PADR_ADDR))
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#define PBDR (*((volatile unsigned short*)PBDR_ADDR))
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#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
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#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
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#define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
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#define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
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#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
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#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
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#define PCDR (*((volatile unsigned short*)PCDR_ADDR))
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#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
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/***************************************************************************
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* Register bit definitions
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**************************************************************************/
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/*
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* Serial mode register bits
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*/
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#define SYNC_MODE 0x80
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#define SEVEN_BIT_DATA 0x40
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#define PARITY_ON 0x20
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#define ODD_PARITY 0x10
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#define STOP_BITS_2 0x08
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#define ENABLE_MULTIP 0x04
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#define PHI_64 0x03
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#define PHI_16 0x02
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#define PHI_4 0x01
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/*
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* Serial control register bits
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*/
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#define SCI_TIE 0x80 /* Transmit interrupt enable */
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#define SCI_RIE 0x40 /* Receive interrupt enable */
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#define SCI_TE 0x20 /* Transmit enable */
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#define SCI_RE 0x10 /* Receive enable */
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#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
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#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
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#define SCI_CKE1 0x02 /* Clock enable 1 */
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#define SCI_CKE0 0x01 /* Clock enable 0 */
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/*
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* Serial status register bits
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*/
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#define SCI_TDRE 0x80 /* Transmit data register empty */
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#define SCI_RDRF 0x40 /* Receive data register full */
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#define SCI_ORER 0x20 /* Overrun error */
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#define SCI_FER 0x10 /* Framing error */
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#define SCI_PER 0x08 /* Parity error */
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#define SCI_TEND 0x04 /* Transmit end */
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#define SCI_MPB 0x02 /* Multiprocessor bit */
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#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
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#endif
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