11cca264ff
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
279 lines
13 KiB
C
279 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2010 by Michael Sevakis
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*
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* Target-specific i.MX31 DVFS and DPTC driver declarations
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _DVFS_DPTC_TARGET_H_
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#define _DVFS_DPTC_TARGET_H_
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#define DVFS_LEVEL_DEFAULT 1 /* 264 MHz - safe frequency for 1.35V */
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#define DVFS_NUM_LEVELS 3 /* 528 MHz, 264 MHz, 132 MHz */
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#define DVFS_NO_PWRRDY /* PWRRDY is connected to different SoC port */
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#define DPTC_WP_DEFAULT 1 /* 1.600, 1.350, 1.350 */
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#define DPTC_WP_PANIC 3 /* Up to minimum for > 400 MHz */
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#define DPTC_NUM_WP 17
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#define VOLTAGE_SETTING_MIN MC13783_SW_1_350
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#define VOLTAGE_SETTING_MAX MC13783_SW_1_625
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/* Frequency increase threshold. Increase frequency change request
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* will be sent if DVFS counter value will be more than this value. */
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#define DVFS_UPTHR 30
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/* Frequency decrease threshold. Decrease frequency change request
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* will be sent if DVFS counter value will be less than this value. */
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#define DVFS_DNTHR 18
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/* Panic threshold. Panic frequency change request
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* will be sent if DVFS counter value will be more than this value. */
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#define DVFS_PNCTHR 63
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/* With the ARM clocked at 532, this setting yields a DIV_3_CLK of 2.03 kHz.
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*
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* Note: To get said clock, the divider would have to be 262144. The values
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* and their meanings are not published in the reference manual for i.MX31
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* but show up in the i.MX35 reference manual. Either that chip is different
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* and the values have an additional division or the comments in the BSP are
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* incorrect.
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*/
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#define DVFS_DIV3CK CCM_LTR0_DIV3CK_131072
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/* UPCNT defines the amount of times the up threshold should be exceeded
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* before DVFS will trigger frequency increase request. */
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#if 0
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/* Freescale BSP value: a bit too agressive IMHO */
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#define DVFS_UPCNT 0x33
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#endif
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#define DVFS_UPCNT 0x48
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/* DNCNT defines the amount of times the down threshold should be undershot
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* before DVFS will trigger frequency decrease request. */
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#define DVFS_DNCNT 0x33
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/* EMAC defines how many samples are included in EMA calculation */
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#define DVFS_EMAC 0x20
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/* Define mask of which reference circuits are employed for DPTC */
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#define DPTC_DRCE_MASK (CCM_PMCR0_DRCE1 | CCM_PMCR0_DRCE3)
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/* When panicing, this working point is used */
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#define DPTC_PANIC_WP
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/* Due to a hardware bug in chip revisions < 2.0, when switching between
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* Serial and MCU PLLs, DVFS forces the target PLL to go into reset and
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* relock, only post divider frequency scaling is possible.
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*/
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static const union dvfs_dptc_voltage_table_entry
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dvfs_dptc_voltage_table[DPTC_NUM_WP] =
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{
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/* For each working point, there are four DVFS settings, chosen by the
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* DVS pin states on the PMIC set by the DVFS routines. Pins are reversed
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* and actual order as used by PMIC for DVSUP values of 00, 01, 10 and 11
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* is below.
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*
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* SW1A SW1ADVS SW1BDVS SW1BSTBY
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* 0 2 1 3 */
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{ { MC13783_SW_1_625, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_600, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_575, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_550, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_525, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_500, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_475, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_450, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_425, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_400, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_375, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_325, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_300, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_275, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_250, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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{ { MC13783_SW_1_225, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
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};
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#if 1
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/* For 27 MHz PLL reference clock */
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static const struct dptc_dcvr_table_entry
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dptc_dcvr_table[DVFS_NUM_LEVELS][DPTC_NUM_WP] =
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{
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/* DCVR0 DCVR1 DCVR2 DCVR3 */
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{ /* 528 MHz */
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{ 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
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{ 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 },
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{ 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 },
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{ 0xffc00000, 0x90629894, 0xffc00000, 0xdd74fd24 },
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{ 0xffc00000, 0x90a2a894, 0xffc00000, 0xddb50d28 },
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{ 0xffc00000, 0x90e2b89c, 0xffc00000, 0xde352d30 },
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{ 0xffc00000, 0x9162d8a0, 0xffc00000, 0xdef55d38 },
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{ 0xffc00000, 0x91e2f8a8, 0xffc00000, 0xdfb58d44 },
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{ 0xffc00000, 0x926308b0, 0xffc00000, 0xe0b5cd54 },
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{ 0xffc00000, 0x92e328bc, 0xffc00000, 0xe1f60d64 },
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{ 0xffc00000, 0x93a358c0, 0xffc00000, 0xe3365d74 },
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{ 0xffc00000, 0xf66388cc, 0xffc00000, 0xf6768d84 },
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{ 0xffc00000, 0xf663b8d4, 0xffc00000, 0xf676dd98 },
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{ 0xffc00000, 0xf663e8e0, 0xffc00000, 0xf6773da4 },
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{ 0xffc00000, 0xf66418ec, 0xffc00000, 0xf6778dbc },
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{ 0xffc00000, 0xf66458fc, 0xffc00000, 0xf677edd0 },
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{ 0xffc00000, 0xf6648908, 0xffc00000, 0xf6783de8 },
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},
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{ /* 264 MHz */
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{ 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd4d4348 },
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{ 0xffc00000, 0x9088b228, 0xffc00000, 0xdd8d434c },
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{ 0xffc00000, 0x90c8b228, 0xffc00000, 0xde0d534c },
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{ 0xffc00000, 0x9148b228, 0xffc00000, 0xdecd5350 },
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{ 0xffc00000, 0x91c8c22c, 0xffc00000, 0xdf8d6354 },
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{ 0xffc00000, 0x9248d22c, 0xffc00000, 0xe08d7354 },
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{ 0xffc00000, 0x92c8d230, 0xffc00000, 0xe1cd8358 },
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{ 0xffc00000, 0x9388e234, 0xffc00000, 0xe30d935c },
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{ 0xffc00000, 0xf648e234, 0xffc00000, 0xf64db364 },
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{ 0xffc00000, 0xf648f238, 0xffc00000, 0xf64dc368 },
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{ 0xffc00000, 0xf648f23c, 0xffc00000, 0xf64dd36c },
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{ 0xffc00000, 0xf649023c, 0xffc00000, 0xf64de370 },
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{ 0xffc00000, 0xf649123c, 0xffc00000, 0xf64df374 },
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{ 0xffc00000, 0xf6492240, 0xffc00000, 0xf64e1378 },
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},
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{ /* 132 MHz */
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{ 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
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{ 0xffc00000, 0x9048a224, 0xffc00000, 0xdd4d4348 },
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{ 0xffc00000, 0x9088b228, 0xffc00000, 0xdd8d434c },
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{ 0xffc00000, 0x90c8b228, 0xffc00000, 0xde0d534c },
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{ 0xffc00000, 0x9148b228, 0xffc00000, 0xdecd5350 },
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{ 0xffc00000, 0x91c8c22c, 0xffc00000, 0xdf8d6354 },
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{ 0xffc00000, 0x9248d22c, 0xffc00000, 0xe08d7354 },
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{ 0xffc00000, 0x92c8d230, 0xffc00000, 0xe1cd8358 },
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{ 0xffc00000, 0x9388e234, 0xffc00000, 0xe30d935c },
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{ 0xffc00000, 0xf648e234, 0xffc00000, 0xf64db364 },
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{ 0xffc00000, 0xf648f238, 0xffc00000, 0xf64dc368 },
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{ 0xffc00000, 0xf648f23c, 0xffc00000, 0xf64dd36c },
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{ 0xffc00000, 0xf649023c, 0xffc00000, 0xf64de370 },
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{ 0xffc00000, 0xf649123c, 0xffc00000, 0xf64df374 },
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{ 0xffc00000, 0xf6492240, 0xffc00000, 0xf64e1378 },
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},
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};
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#else/* For 26 MHz PLL reference clock */
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static const struct dptc_dcvr_table_entry
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dptc_dcvr_table[DVFS_NUM_LEVELS][DPTC_NUM_WP] =
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{
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/* DCVR0 DCVR1 DCVR2 DCVR3 */
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{ /* 528 MHz */
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{ 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 },
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{ 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 },
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{ 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 },
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{ 0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4 },
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{ 0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8 },
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{ 0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0 },
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{ 0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc },
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{ 0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8 },
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{ 0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8 },
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{ 0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8 },
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{ 0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8 },
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{ 0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08 },
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{ 0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c },
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{ 0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c },
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{ 0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44 },
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{ 0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58 },
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{ 0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70 },
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},
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{ /* 264 MHz */
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{ 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe5cdc368 },
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{ 0xffc00000, 0x9609023c, 0xffc00000, 0xe60dc36c },
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{ 0xffc00000, 0x9649023c, 0xffc00000, 0xe68dd36c },
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{ 0xffc00000, 0x96c9023c, 0xffc00000, 0xe74dd370 },
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{ 0xffc00000, 0x97491240, 0xffc00000, 0xe80de374 },
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{ 0xffc00000, 0x97c92240, 0xffc00000, 0xe94df374 },
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{ 0xffc00000, 0x98892244, 0xffc00000, 0xea8e0378 },
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{ 0xffc00000, 0x99493248, 0xffc00000, 0xebce137c },
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{ 0xffc00000, 0xffc93248, 0xffc00000, 0xffce3384 },
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{ 0xffc00000, 0xffc9424c, 0xffc00000, 0xffce4388 },
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{ 0xffc00000, 0xffc95250, 0xffc00000, 0xffce538c },
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{ 0xffc00000, 0xffc96250, 0xffc00000, 0xffce7390 },
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{ 0xffc00000, 0xffc97254, 0xffc00000, 0xffce8394 },
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{ 0xffc00000, 0xffc98258, 0xffc00000, 0xffcea39c },
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},
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{ /* 132 MHz */
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{ 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
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{ 0xffc00000, 0x95c8f238, 0xffc00000, 0xe5cdc368 },
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{ 0xffc00000, 0x9609023c, 0xffc00000, 0xe60dc36c },
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{ 0xffc00000, 0x9649023c, 0xffc00000, 0xe68dd36c },
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{ 0xffc00000, 0x96c9023c, 0xffc00000, 0xe74dd370 },
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{ 0xffc00000, 0x97491240, 0xffc00000, 0xe80de374 },
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{ 0xffc00000, 0x97c92240, 0xffc00000, 0xe94df374 },
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{ 0xffc00000, 0x98892244, 0xffc00000, 0xea8e0378 },
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{ 0xffc00000, 0x99493248, 0xffc00000, 0xebce137c },
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{ 0xffc00000, 0xffc93248, 0xffc00000, 0xffce3384 },
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{ 0xffc00000, 0xffc9424c, 0xffc00000, 0xffce4388 },
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{ 0xffc00000, 0xffc95250, 0xffc00000, 0xffce538c },
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{ 0xffc00000, 0xffc96250, 0xffc00000, 0xffce7390 },
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{ 0xffc00000, 0xffc97254, 0xffc00000, 0xffce8394 },
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{ 0xffc00000, 0xffc98258, 0xffc00000, 0xffcea39c },
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},
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};
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#endif
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/* For 27 MHz PLL reference clock */
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static const struct dvfs_clock_table_entry
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dvfs_clock_table[DVFS_NUM_LEVELS] =
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{
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/* PLL val PDR0 val PLL VSCNT */
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{ 0x00082407, 0xff841e58, 1, 7 }, /* MCUPLL, 528 MHz, /1 = 528 MHz */
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{ 0x00082407, 0xff841e59, 1, 7 }, /* MCUPLL, 528 MHz, /2 = 264 MHz */
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{ 0x00082407, 0xff841e5b, 1, 7 }, /* MCUPLL, 528 MHz, /4 = 132 MHz */
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};
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/* DVFS load-tracking signal weights and detect modes */
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static const struct dvfs_lt_signal_descriptor lt_signals[16] =
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{
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M0_BUF */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M1 */
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{ 0, 0 }, /* DVFS_LT_SIG_MBX_MBXCLKGATE */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M3 */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M4 */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M5 */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M6 */
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{ 0, 0 }, /* DVFS_LT_SIG_M3IF_M7 */
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{ 0, 0 }, /* DVFS_LT_SIG_ARM11_P_IRQ_B_RBT_GATE */
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{ 0, 0 }, /* DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE */
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{ 0, 0 }, /* DVFS_LT_SIG_IPI_GPIO1_INT0 */
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{ 0, 0 }, /* DVFS_LT_SIG_IPI_INT_IPU_FUNC */
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{ 7, 0 }, /* DVFS_LT_SIG_DVGP0 */
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{ 7, 0 }, /* DVFS_LT_SIG_DVGP1 */
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{ 7, 0 }, /* DVFS_LT_SIG_DVGP2 */
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{ 7, 0 }, /* DVFS_LT_SIG_DVGP3 */
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};
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#endif /* _DVFS_DPTC_TARGET_H_ */
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