4604e984e8
There are tricky DMA/cache related issue on the imx233 which could pop up with the old driver. The new one ensures that all dma tranfers are cache safe by using an intermediate buffer. Change-Id: I72060682d1c285c83ae16455cfdb62f372b5d687
138 lines
5.9 KiB
C
138 lines
5.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by amaury Pouly
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*
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* Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
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* and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __I2C_IMX233_H__
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#define __I2C_IMX233_H__
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#include "cpu.h"
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#include "system.h"
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#include "system-target.h"
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#include "i2c.h"
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#define HW_I2C_BASE 0x80058000
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#define HW_I2C_CTRL0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x0))
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#define HW_I2C_CTRL0__XFER_COUNT_BM 0xffff
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#define HW_I2C_CTRL0__TRANSMIT (1 << 16)
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#define HW_I2C_CTRL0__MASTER_MODE (1 << 17)
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#define HW_I2C_CTRL0__SLAVE_ADDRESS_ENABLE (1 << 18)
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#define HW_I2C_CTRL0__PRE_SEND_START (1 << 19)
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#define HW_I2C_CTRL0__POST_SEND_STOP (1 << 20)
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#define HW_I2C_CTRL0__RETAIN_CLOCK (1 << 21)
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#define HW_I2C_CTRL0__CLOCK_HELD (1 << 22)
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#define HW_I2C_CTRL0__PIO_MODE (1 << 24)
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#define HW_I2C_CTRL0__SEND_NAK_ON_LAST (1 << 25)
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#define HW_I2C_CTRL0__ACKNOWLEDGE (1 << 26)
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#define HW_I2C_CTRL0__RUN (1 << 29)
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#define HW_I2C_TIMING0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x10))
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#define HW_I2C_TIMING0__RECV_COUNT_BM 0x3ff
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#define HW_I2C_TIMING0__HIGH_COUNT_BM (0x3ff << 16)
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#define HW_I2C_TIMING0__HIGH_COUNT_BP 16
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#define HW_I2C_TIMING1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x20))
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#define HW_I2C_TIMING1__XMIT_COUNT_BM 0x3ff
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#define HW_I2C_TIMING1__LOW_COUNT_BM (0x3ff << 16)
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#define HW_I2C_TIMING1__LOW_COUNT_BP 16
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#define HW_I2C_TIMING2 (*(volatile uint32_t *)(HW_I2C_BASE + 0x30))
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#define HW_I2C_TIMING2__LEADIN_COUNT_BM 0x3ff
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#define HW_I2C_TIMING2__BUS_FREE_BM (0x3ff << 16)
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#define HW_I2C_TIMING2__BUS_FREE_BP 16
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#define HW_I2C_CTRL1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x40))
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#define HW_I2C_CTRL1__SLAVE_IRQ (1 << 0)
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#define HW_I2C_CTRL1__SLAVE_STOP_IRQ (1 << 1)
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#define HW_I2C_CTRL1__MASTER_LOSS_IRQ (1 << 2)
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#define HW_I2C_CTRL1__EARLY_TERM_IRQ (1 << 3)
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#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ (1 << 4)
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#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ (1 << 5)
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#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ (1 << 6)
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#define HW_I2C_CTRL1__BUS_FREE_IRQ (1 << 7)
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#define HW_I2C_CTRL1__SLAVE_IRQ_EN (1 << 8)
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#define HW_I2C_CTRL1__SLAVE_STOP_IRQ_EN (1 << 9)
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#define HW_I2C_CTRL1__MASTER_LOSS_IRQ_EN (1 << 10)
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#define HW_I2C_CTRL1__EARLY_TERM_IRQ_EN (1 << 11)
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#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
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#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ_EN (1 << 13)
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#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ_EN (1 << 14)
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#define HW_I2C_CTRL1__BUS_FREE_IRQ_EN (1 << 15)
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#define HW_I2C_CTRL1__BCAST_SLAVE_EN (1 << 24)
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#define HW_I2C_CTRL1__FORCE_CLK_IDLE (1 << 25)
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#define HW_I2C_CTRL1__FORCE_DATA_IDLE (1 << 26)
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#define HW_I2C_CTRL1__ACK_MODE (1 << 27)
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#define HW_I2C_CTRL1__CLR_GOT_A_NAK (1 << 28)
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#define HW_I2C_CTRL1__ALL_IRQ 0xff
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#define HW_I2C_CTRL1__ALL_IRQ_EN 0xff00
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#define HW_I2C_STAT (*(volatile uint32_t *)(HW_I2C_BASE + 0x50))
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#define HW_I2C_STAT__SLAVE_IRQ_SUMMARY (1 << 0)
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#define HW_I2C_STAT__SLAVE_STOP_IRQ_SUMMARY (1 << 1)
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#define HW_I2C_STAT__MASTER_LOSS_IRQ_SUMMARY (1 << 2)
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#define HW_I2C_STAT__EARLY_TERM_IRQ_SUMMARY (1 << 3)
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#define HW_I2C_STAT__OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
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#define HW_I2C_STAT__NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
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#define HW_I2C_STAT__DATA_ENGINE_COMPLT_IRQ_SUMMARY (1 << 6)
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#define HW_I2C_STAT__BUS_FREE_IRQ_SUMMARY (1 << 7)
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#define HW_I2C_STAT__SLAVE_BUSY (1 << 8)
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#define HW_I2C_STAT__DATA_ENGINE_BUSY (1 << 9)
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#define HW_I2C_STAT__CLK_GEN_BUSY (1 << 10)
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#define HW_I2C_STAT__BUS_BUSY (1 << 11)
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#define HW_I2C_STAT__DATA_ENGINE_DMA_WAIT (1 << 12)
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#define HW_I2C_STAT__SLAVE_SEARCHING (1 << 13)
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#define HW_I2C_STAT__SLAVE_FOUND (1 << 14)
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#define HW_I2C_STAT__SLAVE_ADDR_EQ_ZERO (1 << 15)
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#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BM (0xff << 16)
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#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BP 16
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#define HW_I2C_STAT__GOT_A_NAK (1 << 28)
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#define HW_I2C_STAT__ANY_ENABLED_IRQ (1 << 29)
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#define HW_I2C_STAT__MASTER_PRESENT (1 << 31)
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#define HW_I2C_DATA (*(volatile uint32_t *)(HW_I2C_BASE + 0x60))
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#define HW_I2C_DEBUG0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x70))
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#define HW_I2C_DEBUG1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x80))
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#define HW_I2C_VERSION (*(volatile uint32_t *)(HW_I2C_BASE + 0x90))
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enum imx233_i2c_error_t
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{
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I2C_SUCCESS = 0,
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I2C_ERROR = -1,
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I2C_TIMEOUT = -2,
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I2C_MASTER_LOSS = -3,
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I2C_NO_SLAVE_ACK = -4,
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I2C_SLAVE_NAK = -5,
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I2C_BUFFER_FULL = -6,
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};
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void imx233_i2c_init(void);
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/* start building a transfer, will acquire an exclusive lock */
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void imx233_i2c_begin(void);
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/* add stage */
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enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, unsigned size, bool stop);
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/* end building a transfer and start the transfer */
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enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout);
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#endif // __I2C_IMX233_H__
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