dd5dd8cfd9
The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
221 lines
6.6 KiB
C
221 lines
6.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#define nop \
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asm volatile ("trapf")
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#define or_l(mask, address) \
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asm \
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("or.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define and_l(mask, address) \
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asm \
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("and.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define eor_l(mask, address) \
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asm \
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("eor.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define add_l(addend, address) \
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asm \
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("add.l %0, (%1)" \
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: \
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: /* %0 */ "r"(addend), \
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/* %1 */ "a"(address))
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#define EMAC_ROUND 0x10
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#define EMAC_FRACTIONAL 0x20
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#define EMAC_UNSIGNED 0x40
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#define EMAC_SATURATE 0x80
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static inline void coldfire_set_macsr(unsigned long flags)
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{
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asm volatile ("move.l %0, %%macsr" : : "i,r" (flags));
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}
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static inline unsigned long coldfire_get_macsr(void)
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{
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unsigned long m;
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asm volatile ("move.l %%macsr, %0" : "=r" (m));
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return m;
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}
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/* ColdFire IRQ Levels/Priorities in Rockbox summary:
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* DMA0 - level 6, priority 0 (playback)
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* DMA1 - level 6, priority 1 (recording)
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* TIMER1 - level 4, priority 0 (timers)
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* TIMER0 - level 3, priority 0 (ticks)
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* GPI0 - level 3, priority 0 (pcf50606 PMU, secondary controller)
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*/
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#define HIGHEST_IRQ_LEVEL (5<<8) /* Disable all but DMA and higher */
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#define DMA_IRQ_LEVEL (6<<8) /* Disable DMA and lower */
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#define DISABLE_INTERRUPTS (7<<8) /* Disable all but NMIs */
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static inline int set_irq_level(int level)
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{
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int oldlevel;
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/* Read the old level and set the new one */
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/* Not volatile - can be removed if oldlevel isn't used */
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asm ("move.w %%sr, %0" : "=d"(oldlevel));
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/* Keep supervisor state set */
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asm volatile ("move.w %0, %%sr \n" : : "d"(level | 0x2000));
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return oldlevel;
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}
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/* Enable all interrupts */
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static inline void enable_irq(void)
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{
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int tmp;
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/* Using move.w over the compiler's move.l saves 2 bytes per instance */
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asm volatile ("move.w %1, %0 \n"
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"move.w %0, %%sr \n"
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: "=&d"(tmp) : "i"(0x2000));
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}
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/* Disable interrupts up to HIGHEST_IRQ_LEVEL */
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static inline void disable_irq(void)
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{
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int tmp;
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/* Using move.w over the compiler's move.l saves 2 bytes per instance */
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asm volatile ("move.w %1, %0 \n"
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"move.w %0, %%sr \n"
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: "=&d"(tmp)
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: "i"(0x2000 | HIGHEST_IRQ_LEVEL));
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}
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static inline int disable_irq_save(void)
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{
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int oldlevel, tmp;
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/* Using move.w over the compiler's move.l saves 2 bytes per instance */
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asm volatile ("move.w %%sr, %1 \n"
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"move.w %2, %0 \n"
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"move.w %0, %%sr \n"
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: "=&d"(tmp), "=d"(oldlevel)
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: "i"(0x2000 | HIGHEST_IRQ_LEVEL));
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return oldlevel;
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}
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static inline void restore_irq(int oldlevel)
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{
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/* Restore the sr value returned by disable_irq_save or
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* set_irq_level */
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asm volatile ("move.w %0, %%sr" : : "d"(oldlevel));
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}
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline uint32_t SWAW32(uint32_t value)
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/*
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result[31..16] = value[15.. 0];
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result[15.. 0] = value[31..16];
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*/
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{
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asm ("swap %%0" : "+r"(value));
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return value;
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}
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static inline uint32_t swap32(uint32_t value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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uint32_t mask = 0x00FF00FF;
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asm ( /* val = ABCD */
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"and.l %[val],%[mask] \n" /* mask = .B.D */
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"eor.l %[mask],%[val] \n" /* val = A.C. */
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"lsl.l #8,%[mask] \n" /* mask = B.D. */
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"lsr.l #8,%[val] \n" /* val = .A.C */
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"or.l %[mask],%[val] \n" /* val = BADC */
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"swap %[val] \n" /* val = DCBA */
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: /* outputs */
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[val] "+d"(value),
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[mask]"+d"(mask)
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);
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return value;
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}
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static inline uint32_t swap_odd_even32(uint32_t value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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uint32_t mask = 0x00FF00FF;
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asm ( /* val = ABCD */
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"and.l %[val],%[mask] \n" /* mask = .B.D */
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"eor.l %[mask],%[val] \n" /* val = A.C. */
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"lsl.l #8,%[mask] \n" /* mask = B.D. */
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"lsr.l #8,%[val] \n" /* val = .A.C */
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"or.l %[mask],%[val] \n" /* val = BADC */
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: /* outputs */
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[val] "+d"(value),
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[mask]"+d"(mask)
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);
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return value;
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}
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#define HAVE_CPUCACHE_COMMIT_DISCARD
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/* deprecated alias */
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#define HAVE_CPUCACHE_INVALIDATE
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#define DEFAULT_PLLCR_AUDIO_BITS 0x10400000
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void coldfire_set_pllcr_audio_bits(long bits);
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/* Set DATAINCONTROL without disturbing FIFO reset state */
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void coldfire_set_dataincontrol(unsigned long value);
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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extern void cf_set_cpu_frequency(long frequency);
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#endif
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/* 11.2896 MHz */
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#define CPUFREQ_DEFAULT_MULT 1
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#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
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/* 45.1584 MHz */
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#define CPUFREQ_NORMAL_MULT 4
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#define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ)
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/* 124.1856 MHz */
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#define CPUFREQ_MAX_MULT 11
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#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
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#endif /* SYSTEM_TARGET_H */
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