dd5dd8cfd9
The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
380 lines
15 KiB
C
380 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include "config.h"
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#include "gcc_extensions.h"
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#include "adc.h"
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#include "system.h"
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#include "lcd.h"
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#include "font.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIE"))) void name (void)
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static const char* const irqname[] = {
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"", "", "AccessErr","AddrErr","IllInstr", "DivX0", "","",
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"PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
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"","","","","","","","",
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"Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
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"Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
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"Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
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"SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
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"DMA2","DMA3","QSPI","","","","","",
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"PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
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"IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
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"AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
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"PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
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"IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
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"UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
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"IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
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"IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
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"GPI0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
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"","","","","","","","SOFTINT0",
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"SOFTINT1","SOFTINT2","SOFTINT3","",
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"","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
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"CDROMNEWBLK","","","","","","IIC2","ADC",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","",""
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};
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default_interrupt (TRAP0); /* Trap #0 */
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default_interrupt (TRAP1); /* Trap #1 */
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default_interrupt (TRAP2); /* Trap #2 */
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default_interrupt (TRAP3); /* Trap #3 */
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default_interrupt (TRAP4); /* Trap #4 */
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default_interrupt (TRAP5); /* Trap #5 */
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default_interrupt (TRAP6); /* Trap #6 */
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default_interrupt (TRAP7); /* Trap #7 */
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default_interrupt (TRAP8); /* Trap #8 */
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default_interrupt (TRAP9); /* Trap #9 */
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default_interrupt (TRAP10); /* Trap #10 */
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default_interrupt (TRAP11); /* Trap #11 */
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default_interrupt (TRAP12); /* Trap #12 */
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default_interrupt (TRAP13); /* Trap #13 */
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default_interrupt (TRAP14); /* Trap #14 */
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default_interrupt (TRAP15); /* Trap #15 */
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default_interrupt (SWT); /* Software Watchdog Timer */
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default_interrupt (TIMER0); /* Timer 0 */
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default_interrupt (TIMER1); /* Timer 1 */
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default_interrupt (I2C); /* I2C */
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default_interrupt (UART1); /* UART 1 */
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default_interrupt (UART2); /* UART 2 */
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default_interrupt (DMA0); /* DMA 0 */
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default_interrupt (DMA1); /* DMA 1 */
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default_interrupt (DMA2); /* DMA 2 */
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default_interrupt (DMA3); /* DMA 3 */
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default_interrupt (QSPI); /* QSPI */
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default_interrupt (PDIR1FULL); /* Processor data in 1 full */
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default_interrupt (PDIR2FULL); /* Processor data in 2 full */
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default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
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default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
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default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
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default_interrupt (PDIR3FULL); /* Processor data in 3 full */
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default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
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default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
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default_interrupt (AUDIOTICK); /* "tick" interrupt */
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default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
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default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
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default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
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default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
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default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
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default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
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default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
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default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
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default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
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default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
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default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
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default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
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default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
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default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
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default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
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default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
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default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
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default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
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default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
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default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
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default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
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default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
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default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
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default_interrupt (GPI0); /* GPIO interrupt 0 */
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default_interrupt (GPI1); /* GPIO interrupt 1 */
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default_interrupt (GPI2); /* GPIO interrupt 2 */
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default_interrupt (GPI3); /* GPIO interrupt 3 */
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default_interrupt (GPI4); /* GPIO interrupt 4 */
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default_interrupt (GPI5); /* GPIO interrupt 5 */
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default_interrupt (GPI6); /* GPIO interrupt 6 */
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default_interrupt (GPI7); /* GPIO interrupt 7 */
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default_interrupt (SOFTINT0); /* Software interrupt 0 */
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default_interrupt (SOFTINT1); /* Software interrupt 1 */
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default_interrupt (SOFTINT2); /* Software interrupt 2 */
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default_interrupt (SOFTINT3); /* Software interrupt 3 */
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default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
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default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
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default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
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default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
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default_interrupt (IIC2); /* I2C 2 */
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default_interrupt (ADC); /* A/D converter */
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#if defined(IAUDIO_X5) || defined(IAUDIO_M5)
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#define EXCP_BUTTON_GPIO_READ GPIO_READ
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#define EXCP_BUTTON_MASK 0x0c000000
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#define EXCP_BUTTON_VALUE 0x08000000 /* On button and !hold */
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#define EXCP_PLLCR 0x10400000
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#elif defined(IAUDIO_M3)
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#define EXCP_BUTTON_GPIO_READ GPIO1_READ
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#define EXCP_BUTTON_MASK 0x00000202
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#define EXCP_BUTTON_VALUE 0x00000200 /* On button and !hold */
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#define EXCP_PLLCR 0x10800000
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#elif defined(MPIO_HD200)
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#define EXCP_BUTTON_GPIO_READ GPIO1_READ
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#define EXCP_BUTTON_MASK 0x01000010
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#define EXCP_BUTTON_VALUE 0x01000000 /* Play button and !hold */
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#define EXCP_PLLCR 0x10800000
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#else
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#define EXCP_BUTTON_GPIO_READ GPIO1_READ
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#define EXCP_BUTTON_MASK 0x00000022
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#define EXCP_BUTTON_VALUE 0x00000000
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#define EXCP_PLLCR 0x10800000
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#endif
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static void system_display_exception_info(unsigned long format,
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unsigned long pc) __attribute__ ((noreturn, used));
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static void system_display_exception_info(unsigned long format,
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unsigned long pc)
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{
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int vector = (format >> 18) & 0xff;
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/* clear screen */
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#if LCD_DEPTH > 1
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lcd_set_backdrop(NULL);
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lcd_set_drawmode(DRMODE_SOLID);
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lcd_set_foreground(LCD_BLACK);
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lcd_set_background(LCD_WHITE);
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#endif
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lcd_setfont(FONT_SYSFIXED);
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lcd_set_viewport(NULL);
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lcd_clear_display();
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lcd_putsf(0, 0, "I%02x:%s", vector, irqname[vector]);
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lcd_putsf(0, 1, "at %08x", pc);
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lcd_update();
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system_exception_wait();
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/* Start watchdog timer with 512 cycles timeout. Don't service it. */
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SYPCR = 0xc0;
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while (1);
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/* We need a reset method that works in all cases. Calling system_reboot()
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doesn't work when we're called from the debug interrupt, because then
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the CPU is in emulator mode and the only ways leaving it are exexcuting
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an rte instruction or performing a reset. Even disabling the breakpoint
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logic and performing special rte magic doesn't make system_reboot()
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reliable. The system restarts, but boot often fails with ata error -42. */
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}
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static void UIE(void) NORETURN_ATTR;
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static void UIE(void)
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{
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asm volatile("subq.l #4,%sp"); /* phony return address - never used */
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asm volatile("jmp system_display_exception_info");
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while (1); /* loop to silence 'noreturn' function does return */
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}
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/* reset vectors are handled in crt0.S */
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void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
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{
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UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,TIMER0,TIMER1,UIE,UIE,UIE,
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/* lvl 3 lvl 4 */
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TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
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TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
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SWT,UIE,UIE,I2C,UART1,UART2,DMA0,DMA1,
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DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
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PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
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IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
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AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
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PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
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IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
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UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
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IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
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IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
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GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
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SOFTINT1,SOFTINT2,SOFTINT3,UIE,
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UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
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CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,IIC2,ADC,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
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};
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void system_init(void)
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{
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/* Clear the accumulators. From here on it's the responsibility of
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whoever uses them to clear them after use and before giving control
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to "foreign" code (use movclr instruction). */
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asm volatile ("movclr.l %%acc0, %%d0\n\t"
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"movclr.l %%acc1, %%d0\n\t"
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"movclr.l %%acc2, %%d0\n\t"
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"movclr.l %%acc3, %%d0\n\t"
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: : : "d0");
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/* Set EMAC unit to fractional mode with saturation, since that's
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what'll be the most useful for most things which the main thread
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will do. */
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coldfire_set_macsr(EMAC_FRACTIONAL | EMAC_SATURATE);
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IMR = 0x3ffff;
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INTPRI1 = 0;
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INTPRI2 = 0;
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INTPRI3 = 0;
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INTPRI4 = 0;
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INTPRI5 = 0;
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INTPRI6 = 0;
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INTPRI7 = 0;
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INTPRI8 = 0;
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/* Set INTBASE and SPURVEC */
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INTBASE = 64;
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SPURVEC = 24;
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MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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cf_set_cpu_frequency(CPUFREQ_DEFAULT);
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#endif
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}
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void system_reboot (void)
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{
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adc_close();
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set_cpu_frequency(0);
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asm(" move.w #0x2700,%sr");
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/* Reset the cookie for the crt0 crash check */
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asm(" move.l #0,%d0");
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asm(" move.l %d0,0x10017ffc");
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asm(" movec.l %d0,%vbr");
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asm(" move.l 0,%sp");
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asm(" move.l 4,%a0");
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asm(" jmp (%a0)");
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}
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void system_exception_wait(void)
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{
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/* set cpu frequency to 11mhz (to prevent overheating) */
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DCR = (DCR & ~0x01ff) | 1;
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PLLCR = EXCP_PLLCR;
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while ((EXCP_BUTTON_GPIO_READ & EXCP_BUTTON_MASK) != EXCP_BUTTON_VALUE);
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}
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/* Utilise the breakpoint hardware to catch invalid memory accesses. */
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int system_memory_guard(int newmode)
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{
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static const unsigned long modes[MAXMEMGUARD][8] = {
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{ /* catch nothing */
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0x2C870000, 0x00000000, /* TDR = 0x00000000 */
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0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
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0x2C8C0000, 0x00000000, /* ABHR = 0x00000000 */
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0x2C860000, 0x00050000, /* AATR = 0x0005 */
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},
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{ /* catch flash ROM writes */
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0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
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0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
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0x2C860000, 0x6F050000, /* AATR = 0x6F05 */
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0x2C878000, 0x20080000, /* TDR = 0x80002008 */
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},
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{ /* catch all accesses to zero area */
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0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
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0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
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0x2C860000, 0xEF050000, /* AATR = 0xEF05 */
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0x2C878000, 0x20080000, /* TDR = 0x80002008 */
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}
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/* Note: CPU space accesses (movec instruction), interrupt acknowledges
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and emulator mode accesses are never caught. */
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};
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static int cur_mode = MEMGUARD_NONE;
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int oldmode = cur_mode;
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const unsigned long *ptr;
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int i;
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if (newmode == MEMGUARD_KEEP)
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newmode = oldmode;
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/* Always set the new mode, we don't know the old settings
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as we cannot read back */
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ptr = modes[newmode];
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for (i = 0; i < 4; i++)
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{
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asm ( "wdebug (%0) \n" : : "a"(ptr));
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ptr += 2;
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}
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cur_mode = newmode;
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return oldmode;
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}
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/* allow setting of audio clock related bits */
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void coldfire_set_pllcr_audio_bits(long bits)
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{
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PLLCR = (PLLCR & ~0x70400000) | (bits & 0x70400000);
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}
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/* Set DATAINCONTROL without disturbing FIFO reset state */
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void coldfire_set_dataincontrol(unsigned long value)
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{
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/* Have to be atomic against recording stop initiated by DMA1 */
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int level = set_irq_level(DMA_IRQ_LEVEL);
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DATAINCONTROL = (DATAINCONTROL & (1 << 9)) | value;
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restore_irq(level);
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}
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void cpucache_commit_discard(void)
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{
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asm volatile ("move.l #0x01000000,%d0\n"
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"movec.l %d0,%cacr\n"
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"move.l #0x80000000,%d0\n"
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"movec.l %d0,%cacr");
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}
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void cpucache_invalidate(void) __attribute__((alias("cpucache_commit_discard")));
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