491 lines
22 KiB
C
491 lines
22 KiB
C
/***************************************************************************
|
|
* __________ __ ___.
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
* \/ \/ \/ \/ \/
|
|
* This file was automatically generated by headergen, DO NOT EDIT it.
|
|
* headergen version: 2.1.7
|
|
* XML versions: stmp3600:2.3.0
|
|
*
|
|
* Copyright (C) 2013 by Amaury Pouly
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version 2
|
|
* of the License, or (at your option) any later version.
|
|
*
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
* KIND, either express or implied.
|
|
*
|
|
****************************************************************************/
|
|
#ifndef __HEADERGEN__STMP3600__UARTDBG__H__
|
|
#define __HEADERGEN__STMP3600__UARTDBG__H__
|
|
|
|
#define REGS_UARTDBG_BASE (0x80070000)
|
|
|
|
#define REGS_UARTDBG_VERSION "2.3.0"
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_DR
|
|
* Address: 0
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
|
|
#define BP_UARTDBG_DR_UNAVAILABLE 16
|
|
#define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_DR_RESERVED 12
|
|
#define BM_UARTDBG_DR_RESERVED 0xf000
|
|
#define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000)
|
|
#define BP_UARTDBG_DR_OE 11
|
|
#define BM_UARTDBG_DR_OE 0x800
|
|
#define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800)
|
|
#define BP_UARTDBG_DR_BE 10
|
|
#define BM_UARTDBG_DR_BE 0x400
|
|
#define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_DR_PE 9
|
|
#define BM_UARTDBG_DR_PE 0x200
|
|
#define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_DR_FE 8
|
|
#define BM_UARTDBG_DR_FE 0x100
|
|
#define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_DR_DATA 0
|
|
#define BM_UARTDBG_DR_DATA 0xff
|
|
#define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_RSR_ECR
|
|
* Address: 0x4
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
|
|
#define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8
|
|
#define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00
|
|
#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00)
|
|
#define BP_UARTDBG_RSR_ECR_EC 4
|
|
#define BM_UARTDBG_RSR_ECR_EC 0xf0
|
|
#define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0)
|
|
#define BP_UARTDBG_RSR_ECR_OE 3
|
|
#define BM_UARTDBG_RSR_ECR_OE 0x8
|
|
#define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_RSR_ECR_BE 2
|
|
#define BM_UARTDBG_RSR_ECR_BE 0x4
|
|
#define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_RSR_ECR_PE 1
|
|
#define BM_UARTDBG_RSR_ECR_PE 0x2
|
|
#define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_RSR_ECR_FE 0
|
|
#define BM_UARTDBG_RSR_ECR_FE 0x1
|
|
#define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_FR
|
|
* Address: 0x18
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
|
|
#define BP_UARTDBG_FR_UNAVAILABLE 16
|
|
#define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_FR_RESERVED 9
|
|
#define BM_UARTDBG_FR_RESERVED 0xfe00
|
|
#define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00)
|
|
#define BP_UARTDBG_FR_RI 8
|
|
#define BM_UARTDBG_FR_RI 0x100
|
|
#define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_FR_TXFE 7
|
|
#define BM_UARTDBG_FR_TXFE 0x80
|
|
#define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_FR_RXFF 6
|
|
#define BM_UARTDBG_FR_RXFF 0x40
|
|
#define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40)
|
|
#define BP_UARTDBG_FR_TXFF 5
|
|
#define BM_UARTDBG_FR_TXFF 0x20
|
|
#define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20)
|
|
#define BP_UARTDBG_FR_RXFE 4
|
|
#define BM_UARTDBG_FR_RXFE 0x10
|
|
#define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_FR_BUSY 3
|
|
#define BM_UARTDBG_FR_BUSY 0x8
|
|
#define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_FR_DCD 2
|
|
#define BM_UARTDBG_FR_DCD 0x4
|
|
#define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_FR_DSR 1
|
|
#define BM_UARTDBG_FR_DSR 0x2
|
|
#define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_FR_CTS 0
|
|
#define BM_UARTDBG_FR_CTS 0x1
|
|
#define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_ILPR
|
|
* Address: 0x20
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
|
|
#define BP_UARTDBG_ILPR_UNAVAILABLE 8
|
|
#define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00
|
|
#define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00)
|
|
#define BP_UARTDBG_ILPR_ILPDVSR 0
|
|
#define BM_UARTDBG_ILPR_ILPDVSR 0xff
|
|
#define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_IBRD
|
|
* Address: 0x24
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
|
|
#define BP_UARTDBG_IBRD_UNAVAILABLE 16
|
|
#define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_IBRD_BAUD_DIVINT 0
|
|
#define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff
|
|
#define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_FBRD
|
|
* Address: 0x28
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
|
|
#define BP_UARTDBG_FBRD_UNAVAILABLE 8
|
|
#define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00
|
|
#define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00)
|
|
#define BP_UARTDBG_FBRD_RESERVED 6
|
|
#define BM_UARTDBG_FBRD_RESERVED 0xc0
|
|
#define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0)
|
|
#define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0
|
|
#define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f
|
|
#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_LCR_H
|
|
* Address: 0x2c
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
|
|
#define BP_UARTDBG_LCR_H_UNAVAILABLE 16
|
|
#define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_LCR_H_RESERVED 8
|
|
#define BM_UARTDBG_LCR_H_RESERVED 0xff00
|
|
#define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00)
|
|
#define BP_UARTDBG_LCR_H_SPS 7
|
|
#define BM_UARTDBG_LCR_H_SPS 0x80
|
|
#define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_LCR_H_WLEN 5
|
|
#define BM_UARTDBG_LCR_H_WLEN 0x60
|
|
#define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60)
|
|
#define BP_UARTDBG_LCR_H_FEN 4
|
|
#define BM_UARTDBG_LCR_H_FEN 0x10
|
|
#define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_LCR_H_STP2 3
|
|
#define BM_UARTDBG_LCR_H_STP2 0x8
|
|
#define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_LCR_H_EPS 2
|
|
#define BM_UARTDBG_LCR_H_EPS 0x4
|
|
#define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_LCR_H_PEN 1
|
|
#define BM_UARTDBG_LCR_H_PEN 0x2
|
|
#define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_LCR_H_BRK 0
|
|
#define BM_UARTDBG_LCR_H_BRK 0x1
|
|
#define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_CR
|
|
* Address: 0x30
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
|
|
#define BP_UARTDBG_CR_UNAVAILABLE 16
|
|
#define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_CR_CTSEN 15
|
|
#define BM_UARTDBG_CR_CTSEN 0x8000
|
|
#define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000)
|
|
#define BP_UARTDBG_CR_RTSEN 14
|
|
#define BM_UARTDBG_CR_RTSEN 0x4000
|
|
#define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000)
|
|
#define BP_UARTDBG_CR_OUT2 13
|
|
#define BM_UARTDBG_CR_OUT2 0x2000
|
|
#define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000)
|
|
#define BP_UARTDBG_CR_OUT1 12
|
|
#define BM_UARTDBG_CR_OUT1 0x1000
|
|
#define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000)
|
|
#define BP_UARTDBG_CR_RTS 11
|
|
#define BM_UARTDBG_CR_RTS 0x800
|
|
#define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800)
|
|
#define BP_UARTDBG_CR_DTR 10
|
|
#define BM_UARTDBG_CR_DTR 0x400
|
|
#define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_CR_RXE 9
|
|
#define BM_UARTDBG_CR_RXE 0x200
|
|
#define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_CR_TXE 8
|
|
#define BM_UARTDBG_CR_TXE 0x100
|
|
#define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_CR_LBE 7
|
|
#define BM_UARTDBG_CR_LBE 0x80
|
|
#define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_CR_RESERVED 3
|
|
#define BM_UARTDBG_CR_RESERVED 0x78
|
|
#define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78)
|
|
#define BP_UARTDBG_CR_SIRLP 2
|
|
#define BM_UARTDBG_CR_SIRLP 0x4
|
|
#define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_CR_SIREN 1
|
|
#define BM_UARTDBG_CR_SIREN 0x2
|
|
#define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_CR_UARTEN 0
|
|
#define BM_UARTDBG_CR_UARTEN 0x1
|
|
#define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_IFLS
|
|
* Address: 0x34
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
|
|
#define BP_UARTDBG_IFLS_UNAVAILABLE 16
|
|
#define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_IFLS_RESERVED 6
|
|
#define BM_UARTDBG_IFLS_RESERVED 0xffc0
|
|
#define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0)
|
|
#define BP_UARTDBG_IFLS_RXIFLSEL 3
|
|
#define BM_UARTDBG_IFLS_RXIFLSEL 0x38
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6
|
|
#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7
|
|
#define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38)
|
|
#define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
|
|
#define BP_UARTDBG_IFLS_TXIFLSEL 0
|
|
#define BM_UARTDBG_IFLS_TXIFLSEL 0x7
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6
|
|
#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7
|
|
#define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7)
|
|
#define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_IMSC
|
|
* Address: 0x38
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
|
|
#define BP_UARTDBG_IMSC_UNAVAILABLE 16
|
|
#define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_IMSC_RESERVED 11
|
|
#define BM_UARTDBG_IMSC_RESERVED 0xf800
|
|
#define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800)
|
|
#define BP_UARTDBG_IMSC_OEIM 10
|
|
#define BM_UARTDBG_IMSC_OEIM 0x400
|
|
#define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_IMSC_BEIM 9
|
|
#define BM_UARTDBG_IMSC_BEIM 0x200
|
|
#define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_IMSC_PEIM 8
|
|
#define BM_UARTDBG_IMSC_PEIM 0x100
|
|
#define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_IMSC_FEIM 7
|
|
#define BM_UARTDBG_IMSC_FEIM 0x80
|
|
#define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_IMSC_RTIM 6
|
|
#define BM_UARTDBG_IMSC_RTIM 0x40
|
|
#define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40)
|
|
#define BP_UARTDBG_IMSC_TXIM 5
|
|
#define BM_UARTDBG_IMSC_TXIM 0x20
|
|
#define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20)
|
|
#define BP_UARTDBG_IMSC_RXIM 4
|
|
#define BM_UARTDBG_IMSC_RXIM 0x10
|
|
#define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_IMSC_DSRMIM 3
|
|
#define BM_UARTDBG_IMSC_DSRMIM 0x8
|
|
#define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_IMSC_DCDMIM 2
|
|
#define BM_UARTDBG_IMSC_DCDMIM 0x4
|
|
#define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_IMSC_CTSMIM 1
|
|
#define BM_UARTDBG_IMSC_CTSMIM 0x2
|
|
#define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_IMSC_RIMIM 0
|
|
#define BM_UARTDBG_IMSC_RIMIM 0x1
|
|
#define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_RIS
|
|
* Address: 0x3c
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
|
|
#define BP_UARTDBG_RIS_UNAVAILABLE 16
|
|
#define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_RIS_RESERVED 11
|
|
#define BM_UARTDBG_RIS_RESERVED 0xf800
|
|
#define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800)
|
|
#define BP_UARTDBG_RIS_OERIS 10
|
|
#define BM_UARTDBG_RIS_OERIS 0x400
|
|
#define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_RIS_BERIS 9
|
|
#define BM_UARTDBG_RIS_BERIS 0x200
|
|
#define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_RIS_PERIS 8
|
|
#define BM_UARTDBG_RIS_PERIS 0x100
|
|
#define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_RIS_FERIS 7
|
|
#define BM_UARTDBG_RIS_FERIS 0x80
|
|
#define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_RIS_RTRIS 6
|
|
#define BM_UARTDBG_RIS_RTRIS 0x40
|
|
#define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40)
|
|
#define BP_UARTDBG_RIS_TXRIS 5
|
|
#define BM_UARTDBG_RIS_TXRIS 0x20
|
|
#define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20)
|
|
#define BP_UARTDBG_RIS_RXRIS 4
|
|
#define BM_UARTDBG_RIS_RXRIS 0x10
|
|
#define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_RIS_DSRRMIS 3
|
|
#define BM_UARTDBG_RIS_DSRRMIS 0x8
|
|
#define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_RIS_DCDRMIS 2
|
|
#define BM_UARTDBG_RIS_DCDRMIS 0x4
|
|
#define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_RIS_CTSRMIS 1
|
|
#define BM_UARTDBG_RIS_CTSRMIS 0x2
|
|
#define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_RIS_RIRMIS 0
|
|
#define BM_UARTDBG_RIS_RIRMIS 0x1
|
|
#define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_MIS
|
|
* Address: 0x40
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
|
|
#define BP_UARTDBG_MIS_UNAVAILABLE 16
|
|
#define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_MIS_RESERVED 11
|
|
#define BM_UARTDBG_MIS_RESERVED 0xf800
|
|
#define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800)
|
|
#define BP_UARTDBG_MIS_OEMIS 10
|
|
#define BM_UARTDBG_MIS_OEMIS 0x400
|
|
#define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_MIS_BEMIS 9
|
|
#define BM_UARTDBG_MIS_BEMIS 0x200
|
|
#define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_MIS_PEMIS 8
|
|
#define BM_UARTDBG_MIS_PEMIS 0x100
|
|
#define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_MIS_FEMIS 7
|
|
#define BM_UARTDBG_MIS_FEMIS 0x80
|
|
#define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_MIS_RTMIS 6
|
|
#define BM_UARTDBG_MIS_RTMIS 0x40
|
|
#define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40)
|
|
#define BP_UARTDBG_MIS_TXMIS 5
|
|
#define BM_UARTDBG_MIS_TXMIS 0x20
|
|
#define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20)
|
|
#define BP_UARTDBG_MIS_RXMIS 4
|
|
#define BM_UARTDBG_MIS_RXMIS 0x10
|
|
#define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_MIS_DSRMMIS 3
|
|
#define BM_UARTDBG_MIS_DSRMMIS 0x8
|
|
#define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_MIS_DCDMMIS 2
|
|
#define BM_UARTDBG_MIS_DCDMMIS 0x4
|
|
#define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_MIS_CTSMMIS 1
|
|
#define BM_UARTDBG_MIS_CTSMMIS 0x2
|
|
#define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_MIS_RIMMIS 0
|
|
#define BM_UARTDBG_MIS_RIMMIS 0x1
|
|
#define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_ICR
|
|
* Address: 0x44
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
|
|
#define BP_UARTDBG_ICR_UNAVAILABLE 16
|
|
#define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_ICR_RESERVED 11
|
|
#define BM_UARTDBG_ICR_RESERVED 0xf800
|
|
#define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800)
|
|
#define BP_UARTDBG_ICR_OEIC 10
|
|
#define BM_UARTDBG_ICR_OEIC 0x400
|
|
#define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400)
|
|
#define BP_UARTDBG_ICR_BEIC 9
|
|
#define BM_UARTDBG_ICR_BEIC 0x200
|
|
#define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200)
|
|
#define BP_UARTDBG_ICR_PEIC 8
|
|
#define BM_UARTDBG_ICR_PEIC 0x100
|
|
#define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100)
|
|
#define BP_UARTDBG_ICR_FEIC 7
|
|
#define BM_UARTDBG_ICR_FEIC 0x80
|
|
#define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80)
|
|
#define BP_UARTDBG_ICR_RTIC 6
|
|
#define BM_UARTDBG_ICR_RTIC 0x40
|
|
#define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40)
|
|
#define BP_UARTDBG_ICR_TXIC 5
|
|
#define BM_UARTDBG_ICR_TXIC 0x20
|
|
#define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20)
|
|
#define BP_UARTDBG_ICR_RXIC 4
|
|
#define BM_UARTDBG_ICR_RXIC 0x10
|
|
#define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10)
|
|
#define BP_UARTDBG_ICR_DSRMIC 3
|
|
#define BM_UARTDBG_ICR_DSRMIC 0x8
|
|
#define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8)
|
|
#define BP_UARTDBG_ICR_DCDMIC 2
|
|
#define BM_UARTDBG_ICR_DCDMIC 0x4
|
|
#define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_ICR_CTSMIC 1
|
|
#define BM_UARTDBG_ICR_CTSMIC 0x2
|
|
#define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_ICR_RIMIC 0
|
|
#define BM_UARTDBG_ICR_RIMIC 0x1
|
|
#define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1)
|
|
|
|
/**
|
|
* Register: HW_UARTDBG_DMACR
|
|
* Address: 0x48
|
|
* SCT: no
|
|
*/
|
|
#define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
|
|
#define BP_UARTDBG_DMACR_UNAVAILABLE 16
|
|
#define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000
|
|
#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
|
|
#define BP_UARTDBG_DMACR_RESERVED 3
|
|
#define BM_UARTDBG_DMACR_RESERVED 0xfff8
|
|
#define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8)
|
|
#define BP_UARTDBG_DMACR_DMAONERR 2
|
|
#define BM_UARTDBG_DMACR_DMAONERR 0x4
|
|
#define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4)
|
|
#define BP_UARTDBG_DMACR_TXDMAE 1
|
|
#define BM_UARTDBG_DMACR_TXDMAE 0x2
|
|
#define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2)
|
|
#define BP_UARTDBG_DMACR_RXDMAE 0
|
|
#define BM_UARTDBG_DMACR_RXDMAE 0x1
|
|
#define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1)
|
|
|
|
#endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */
|