223 lines
9.3 KiB
C
223 lines
9.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3600:2.3.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__HWECC__H__
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#define __HEADERGEN__STMP3600__HWECC__H__
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#define REGS_HWECC_BASE (0x80008000)
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#define REGS_HWECC_VERSION "2.3.0"
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/**
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* Register: HW_HWECC_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_HWECC_CTRL (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0))
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#define HW_HWECC_CTRL_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4))
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#define HW_HWECC_CTRL_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8))
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#define HW_HWECC_CTRL_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc))
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#define BP_HWECC_CTRL_SFTRST 31
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#define BM_HWECC_CTRL_SFTRST 0x80000000
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#define BF_HWECC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BP_HWECC_CTRL_CLKGATE 30
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#define BM_HWECC_CTRL_CLKGATE 0x40000000
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#define BF_HWECC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BP_HWECC_CTRL_NUM_SYMBOLS 16
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#define BM_HWECC_CTRL_NUM_SYMBOLS 0x1ff0000
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#define BF_HWECC_CTRL_NUM_SYMBOLS(v) (((v) << 16) & 0x1ff0000)
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#define BP_HWECC_CTRL_DMAWAIT_COUNT 8
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#define BM_HWECC_CTRL_DMAWAIT_COUNT 0x1f00
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#define BF_HWECC_CTRL_DMAWAIT_COUNT(v) (((v) << 8) & 0x1f00)
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#define BP_HWECC_CTRL_BYTE_ENABLE 6
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#define BM_HWECC_CTRL_BYTE_ENABLE 0x40
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#define BF_HWECC_CTRL_BYTE_ENABLE(v) (((v) << 6) & 0x40)
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#define BP_HWECC_CTRL_ECC_SEL 5
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#define BM_HWECC_CTRL_ECC_SEL 0x20
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#define BF_HWECC_CTRL_ECC_SEL(v) (((v) << 5) & 0x20)
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#define BP_HWECC_CTRL_ENC_SEL 4
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#define BM_HWECC_CTRL_ENC_SEL 0x10
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#define BF_HWECC_CTRL_ENC_SEL(v) (((v) << 4) & 0x10)
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#define BP_HWECC_CTRL_UNCORR_IRQ 2
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#define BM_HWECC_CTRL_UNCORR_IRQ 0x4
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#define BF_HWECC_CTRL_UNCORR_IRQ(v) (((v) << 2) & 0x4)
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#define BP_HWECC_CTRL_UNCORR_IRQ_EN 1
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#define BM_HWECC_CTRL_UNCORR_IRQ_EN 0x2
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#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v) (((v) << 1) & 0x2)
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#define BP_HWECC_CTRL_RUN 0
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#define BM_HWECC_CTRL_RUN 0x1
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#define BF_HWECC_CTRL_RUN(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_HWECC_STAT
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* Address: 0x10
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* SCT: no
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*/
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#define HW_HWECC_STAT (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10))
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#define BP_HWECC_STAT_RSDEC_PRESENT 31
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#define BM_HWECC_STAT_RSDEC_PRESENT 0x80000000
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#define BF_HWECC_STAT_RSDEC_PRESENT(v) (((v) << 31) & 0x80000000)
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#define BP_HWECC_STAT_RSENC_PRESENT 30
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#define BM_HWECC_STAT_RSENC_PRESENT 0x40000000
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#define BF_HWECC_STAT_RSENC_PRESENT(v) (((v) << 30) & 0x40000000)
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#define BP_HWECC_STAT_SSDEC_PRESENT 29
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#define BM_HWECC_STAT_SSDEC_PRESENT 0x20000000
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#define BF_HWECC_STAT_SSDEC_PRESENT(v) (((v) << 29) & 0x20000000)
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#define BP_HWECC_STAT_SSENC_PRESENT 28
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#define BM_HWECC_STAT_SSENC_PRESENT 0x10000000
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#define BF_HWECC_STAT_SSENC_PRESENT(v) (((v) << 28) & 0x10000000)
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/**
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* Register: HW_HWECC_DEBUG0
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* Address: 0x20
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* SCT: no
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*/
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#define HW_HWECC_DEBUG0 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20))
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#define BP_HWECC_DEBUG0_DMA_PENDCMD 29
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#define BM_HWECC_DEBUG0_DMA_PENDCMD 0x20000000
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#define BF_HWECC_DEBUG0_DMA_PENDCMD(v) (((v) << 29) & 0x20000000)
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#define BP_HWECC_DEBUG0_DMA_PREQ 28
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#define BM_HWECC_DEBUG0_DMA_PREQ 0x10000000
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#define BF_HWECC_DEBUG0_DMA_PREQ(v) (((v) << 28) & 0x10000000)
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#define BP_HWECC_DEBUG0_SYMBOL_STATE 24
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#define BM_HWECC_DEBUG0_SYMBOL_STATE 0xf000000
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#define BF_HWECC_DEBUG0_SYMBOL_STATE(v) (((v) << 24) & 0xf000000)
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#define BP_HWECC_DEBUG0_CTRL_STATE 16
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#define BM_HWECC_DEBUG0_CTRL_STATE 0x3f0000
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#define BF_HWECC_DEBUG0_CTRL_STATE(v) (((v) << 16) & 0x3f0000)
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#define BP_HWECC_DEBUG0_ECC_EXCEPTION 12
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#define BM_HWECC_DEBUG0_ECC_EXCEPTION 0xf000
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#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v) (((v) << 12) & 0xf000)
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#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS 4
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#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS 0x3f0
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#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v) (((v) << 4) & 0x3f0)
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#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0
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#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0x7
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#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) (((v) << 0) & 0x7)
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/**
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* Register: HW_HWECC_DEBUG1
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* Address: 0x30
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* SCT: no
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*/
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#define HW_HWECC_DEBUG1 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30))
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#define BP_HWECC_DEBUG1_SYNDROME2 18
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#define BM_HWECC_DEBUG1_SYNDROME2 0x7fc0000
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#define BF_HWECC_DEBUG1_SYNDROME2(v) (((v) << 18) & 0x7fc0000)
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#define BP_HWECC_DEBUG1_SYNDROME1 9
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#define BM_HWECC_DEBUG1_SYNDROME1 0x3fe00
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#define BF_HWECC_DEBUG1_SYNDROME1(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG1_SYNDROME0 0
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#define BM_HWECC_DEBUG1_SYNDROME0 0x1ff
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#define BF_HWECC_DEBUG1_SYNDROME0(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DEBUG2
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* Address: 0x40
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* SCT: no
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*/
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#define HW_HWECC_DEBUG2 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40))
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#define BP_HWECC_DEBUG2_SYNDROME5 18
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#define BM_HWECC_DEBUG2_SYNDROME5 0x7fc0000
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#define BF_HWECC_DEBUG2_SYNDROME5(v) (((v) << 18) & 0x7fc0000)
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#define BP_HWECC_DEBUG2_SYNDROME4 9
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#define BM_HWECC_DEBUG2_SYNDROME4 0x3fe00
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#define BF_HWECC_DEBUG2_SYNDROME4(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG2_SYNDROME3 0
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#define BM_HWECC_DEBUG2_SYNDROME3 0x1ff
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#define BF_HWECC_DEBUG2_SYNDROME3(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DEBUG3
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* Address: 0x50
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* SCT: no
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*/
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#define HW_HWECC_DEBUG3 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50))
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#define BP_HWECC_DEBUG3_OMEGA0 18
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#define BM_HWECC_DEBUG3_OMEGA0 0x7fc0000
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#define BF_HWECC_DEBUG3_OMEGA0(v) (((v) << 18) & 0x7fc0000)
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#define BP_HWECC_DEBUG3_SYNDROME7 9
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#define BM_HWECC_DEBUG3_SYNDROME7 0x3fe00
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#define BF_HWECC_DEBUG3_SYNDROME7(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG3_SYNDROME6 0
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#define BM_HWECC_DEBUG3_SYNDROME6 0x1ff
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#define BF_HWECC_DEBUG3_SYNDROME6(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DEBUG4
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* Address: 0x60
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* SCT: no
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*/
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#define HW_HWECC_DEBUG4 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60))
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#define BP_HWECC_DEBUG4_OMEGA3 18
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#define BM_HWECC_DEBUG4_OMEGA3 0x7fc0000
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#define BF_HWECC_DEBUG4_OMEGA3(v) (((v) << 18) & 0x7fc0000)
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#define BP_HWECC_DEBUG4_OMEGA2 9
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#define BM_HWECC_DEBUG4_OMEGA2 0x3fe00
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#define BF_HWECC_DEBUG4_OMEGA2(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG4_OMEGA1 0
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#define BM_HWECC_DEBUG4_OMEGA1 0x1ff
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#define BF_HWECC_DEBUG4_OMEGA1(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DEBUG5
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* Address: 0x70
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* SCT: no
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*/
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#define HW_HWECC_DEBUG5 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70))
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#define BP_HWECC_DEBUG5_LAMBDA2 18
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#define BM_HWECC_DEBUG5_LAMBDA2 0x7fc0000
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#define BF_HWECC_DEBUG5_LAMBDA2(v) (((v) << 18) & 0x7fc0000)
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#define BP_HWECC_DEBUG5_LAMBDA1 9
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#define BM_HWECC_DEBUG5_LAMBDA1 0x3fe00
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#define BF_HWECC_DEBUG5_LAMBDA1(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG5_LAMBDA0 0
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#define BM_HWECC_DEBUG5_LAMBDA0 0x1ff
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#define BF_HWECC_DEBUG5_LAMBDA0(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DEBUG6
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* Address: 0x80
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* SCT: no
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*/
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#define HW_HWECC_DEBUG6 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80))
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#define BP_HWECC_DEBUG6_LAMBDA4 9
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#define BM_HWECC_DEBUG6_LAMBDA4 0x3fe00
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#define BF_HWECC_DEBUG6_LAMBDA4(v) (((v) << 9) & 0x3fe00)
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#define BP_HWECC_DEBUG6_LAMBDA3 0
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#define BM_HWECC_DEBUG6_LAMBDA3 0x1ff
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#define BF_HWECC_DEBUG6_LAMBDA3(v) (((v) << 0) & 0x1ff)
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/**
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* Register: HW_HWECC_DATA
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* Address: 0x90
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* SCT: yes
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*/
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#define HW_HWECC_DATA (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0))
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#define HW_HWECC_DATA_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4))
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#define HW_HWECC_DATA_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8))
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#define HW_HWECC_DATA_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc))
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#define BP_HWECC_DATA_DATA 0
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#define BM_HWECC_DATA_DATA 0xffffffff
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#define BF_HWECC_DATA_DATA(v) (((v) << 0) & 0xffffffff)
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#endif /* __HEADERGEN__STMP3600__HWECC__H__ */
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