rk27xx Marcin Bukat 1.1 GPIO0 GPIO GPIO0

0x1800c000

PADR PADR

0x0

PACON PACON

0x4

PBDR PBDR

0x8

PBCON PBCON

0xc

PCDR PCDR

0x10

PCCON PCCON

0x14

PDDR PDDR

0x18

PDCON PDCON

0x1c

TEST TEST

0x20

IEA IEA

0x24

IEB IEB

0x28

IEC IEC

0x2c

IED IED

0x30

ISA ISA

0x34

ISB ISB

0x38

ISC ISC

0x3c

ISD ISD

0x40

IBEA IBEA

0x44

IBEB IBEB

0x48

IBEC IBEC

0x4c

IBED IBED

0x50

IEVA IEVA

0x54

IEVB IEVB

0x58

IEVC IEVC

0x5c

IEVD IEVD

0x60

ICA ICA

0x64

ICB ICB

0x68

ICC ICC

0x6c

ICD ICD

0x70

ISR ISR

0x74

WDT Watchdog WDT

0x18010000

LR LR

0x0

CVR CVR

0x4

CON CON

0x8

RTC Real time clock RTC

0x18014000

TIME TIME

0x0

DATE DATE

0x4

TALARM TALARM

0x8

DALARM DALARM

0xc

CTRL CTRL

0x10

RESET RESET

0x14

PWOFF PWOFF

0x18

PWFAIL PWFAIL

0x1c

SPI Serial peripherial interface SPI

0x18018000

TXR TXR

0x0

RXR RXR

0x0

IER IER

0x4

FCR FCR

0x8

FWCR FWCR

0xc

DLYCR DLYCR

0x10

TXCR TXCR

0x14

RXCR RXCR

0x18

SSCR SSCR

0x1c

ISR ISR

0x20

SCU System control unit SCU

0x1801c000

ID ID

0x0

SOC_ID 0 32 REVISION_B 0xa100027b REVISION_A 0xa1000604 REMAP REMAP

0x4

MEM_REMAP 0 32 ROM_0x000000 0x0 IRAM_0x000000 0xdeadbeef PLLCON1 PLLCON1

0x8

ARM_PLL_TEST_CONTROL 25 NORMAL 0x0 TEST 0x1 ARM_PLL_SATURATION 24 DISABLE 0x0 ENABLE 0x1 ARM_PLL_FAST_LOCK 23 DISABLE 0x0 ENABLE 0x1 ARM_PLL_POWERDOWN 22 PLL_ON 0x0 PLL_OFF 0x1 ARM_PLL_CLKR 16 6 ARM_PLL_CLKF 4 12 ARM_PLL_CLKOD 1 3 ARM_PLL_BYPASS 0 DISABLE 0x0 ENABLE 0x1 PLLCON2 PLLCON2

0xc

DSP_PLL_TEST_CONTROL 25 NORMAL 0x0 TEST 0x1 DSP_PLL_SATURATION 24 DISABLE 0x0 ENABLE 0x1 DSP_PLL_FAST_LOCK 23 DISABLE 0x0 ENABLE 0x1 DSP_PLL_POWERDOWN 22 PLL_ON 0x0 PLL_OFF 0x1 DSP_PLL_CLKR 16 6 DSP_PLL_CLKF 4 12 DSP_PLL_CLKOD 1 3 DSP_PLL_BYPASS 0 DISABLE 0x0 ENABLE 0x1 PLLCON3 PLLCON3

0x10

CODEC_PLL_TEST_CONTROL 25 NORMAL 0x0 TEST 0x1 CODEC_PLL_SATURATION 24 DISABLE 0x0 ENABLE 0x1 CODEC_PLL_FAST_LOCK 23 DISABLE 0x0 ENABLE 0x1 CODEC_PLL_POWERDOWN 22 PLL_ON 0x0 PLL_OFF 0x1 CODEC_PLL_CLKR 16 6 CODEC_PLL_CLKF 4 12 CODEC_PLL_CLKOD 1 3 CODEC_PLL_BYPASS 0 DISABLE 0x0 ENABLE 0x1 DIVCON1 DIVCON1

0x14

USB_PHY_CLK 31 24MHz 0x0 12MHz 0x1 VIP_SENSOR_CLK 29 2 24MHz 0x0 48MHz 0x1 27MHz 0x2 LCDC_CLK 28 EXT_SOC_27MHz 0x0 LCDC_CLK_DIV_OUT 0x1 LCDC_CLK_DIV 20 8 LCDC_CLK_DIV_SRC 18 2 ARM_PLL 0x0 DSP_PLL 0x1 CODEC_PLL 0x2 LSADC_CLK_DIV 10 8 CODEC_CLK_SRC 9 CODEC_CLK_DIV_OUT 0x0 12MHz_OSC 0x1 CODEC_CLK_DIV 5 4 PCLK_CLK_DIV 3 2 HCLK_to_PCLK_1_1 0x0 HCLK_to_PCLK_2_1 0x1 HCLK_to_PCLK_4_1 0x2 ARM_CLK_DIV 2 ARMPLL_to_ARMCLK_1_1 0x0 ARMPLL_to_ARMCLK_2_1 0x1 DSP_SLOW_MODE 1 DISABLE 0x0 ENABLE 0x1 ARM_SLOW_MODE 0 DISABLE 0x0 ENABLE 0x1 CLKCFG CLKCFG

0x18

WDT_PCLK 31 UNGATE 0x0 GATE 0x1 RTC_PCLK 30 UNGATE 0x0 GATE 0x1 PWM_PCLK 29 UNGATE 0x0 GATE 0x1 TIMER_PCLK 28 UNGATE 0x0 GATE 0x1 GPIO_PCLK 27 UNGATE 0x0 GATE 0x1 HSADC_PCLK 26 UNGATE 0x0 GATE 0x1 HSADC_HCLK 25 UNGATE 0x0 GATE 0x1 LSADC_CLK 24 UNGATE 0x0 GATE 0x1 LSADC_PCLK 23 UNGATE 0x0 GATE 0x1 SD_CLK 22 UNGATE 0x0 GATE 0x1 SPI_CLK 21 UNGATE 0x0 GATE 0x1 I2C_CLK 20 UNGATE 0x0 GATE 0x1 UART1_CLK 19 UNGATE 0x0 GATE 0x1 UART0_CLK 18 UNGATE 0x0 GATE 0x1 I2S_PCLK 17 UNGATE 0x0 GATE 0x1 I2S_CLK 16 UNGATE 0x0 GATE 0x1 VIP_CLK 15 UNGATE 0x0 GATE 0x1 VIP_HCLK 14 UNGATE 0x0 GATE 0x1 LCDC_CLK 13 UNGATE 0x0 GATE 0x1 LCDC_HCLK 12 UNGATE 0x0 GATE 0x1 IRAM_HCLK 11 UNGATE 0x0 GATE 0x1 A2A_HCLK 10 UNGATE 0x0 GATE 0x1 NANDC_HCLK 9 UNGATE 0x0 GATE 0x1 UDC_CLK 6 UNGATE 0x0 GATE 0x1 UHC_CLK 5 UNGATE 0x0 GATE 0x1 DWDMA_CLK 4 UNGATE 0x0 GATE 0x1 HDMA_CLK 3 UNGATE 0x0 GATE 0x1 SDRAM_HCLK 2 UNGATE 0x0 GATE 0x1 DSP_CLK 1 UNGATE 0x0 GATE 0x1 OTP_CLK 0 UNGATE 0x0 GATE 0x1 RSTCFG RSTCFG

0x1c

ARM_RST 12 DEASSERT 0x0 ASSERT 0x1 DUALCORE_ECT_RST 11 DEASSERT 0x0 ASSERT 0x1 DUALCORE_MAILBOX_RST 10 DEASSERT 0x0 ASSERT 0x1 SD_RST 9 DEASSERT 0x0 ASSERT 0x1 HSADC_RST 8 DEASSERT 0x0 ASSERT 0x1 LSADC_RST 7 DEASSERT 0x0 ASSERT 0x1 CODEC_RST 6 DEASSERT 0x0 ASSERT 0x1 DSP_PERIPHERAL_RST 5 DEASSERT 0x0 ASSERT 0x1 DSP_CORE_RST 4 DEASSERT 0x0 ASSERT 0x1 VIP_RST 3 DEASSERT 0x0 ASSERT 0x1 LCDC_RST 2 DEASSERT 0x0 ASSERT 0x1 UDC_RST 1 DEASSERT 0x0 ASSERT 0x1 UHC_RST 0 DEASSERT 0x0 ASSERT 0x1 PWM PWM

0x20

PLL_LOCK_PERIOD 16 16 EXT_WAKEUP_PIN_POLARITY 6 POSITIVE 0x0 NEGATIVE 0x1 RTC_ALARM_WAKEUP 5 ENABLE 0x0 DISABLE 0x1 EXT_WAKEUP 4 ENABLE 0x0 DISABLE 0x1 SCU_IRQ_CLEAR 3 PENDING 0x0 CLEAR 0x1 POWERMANAGEMENT_MODE 0 3 NORMAL 0x0 STOP 0x4 CPUPD CPUPD

0x24

CHIPCFG CHIPCFG

0x28

NOR_FLASH_BUSWIDTH 19 16BIT 0x0 8BIT 0x1 DSP2ARM_IRQ 17 ARM2DSP_IRQ 16 ARM_HIGHVECTOR 3 UHC_DATABUS_WIDTH 2 8BIT 0x0 16BIT 0x1 USB_PHY_MUX 1 USB_PHY_UDC 0x0 USB_PHY_UHC 0x1 STATUS STATUS

0x2c

DSPSYSCLKVALID 4 UNSTABLE 0x0 VALID 0x1 ARMSYSCLKVALID 3 UNSTABLE 0x0 VALID 0x1 CODEC_PLL_LOCKED 2 UNSTABLE 0x0 LOCKED 0x1 DSP_PLL_LOCKED 1 UNSTABLE 0x0 LOCKED 0x1 ARM_PLL_LOCKED 0 UNSTABLE 0x0 LOCKED 0x1 IOMUXA_CON IOMUXA_CON

0x30

I2S_CODEC_EXT_SEL 19 INTERNAL_CODEC 0x0 PIN 0x1 I2C_CODEC_EXT_SEL 18 INTERNAL_CODEC 0x0 PIN 0x1 I2C_FLASHCS3_GPIOB_SEL 16 2 I2C_SDA 0x0 FLASH_CS3 0x1 GPIOB7 0x2 I2C_FLASHCS2_GPIOB_SEL 14 2 I2C_SCL 0x0 FLASH_CS2 0x1 GPIOB6 0x2 GPIOB_SD_SPI_SEL 12 2 GPIOB_0_5 0x0 SD 0x1 SPI 0x2 GPIO_LCDVSYN_SEL 11 GPIOA7 0x0 LCD_VSYN 0x1 GPIO_LCDEN_SEL 10 GPIOA6 0x0 LCD_DATA_ENABLE 0x1 GPIO_FLASHCS1_SEL 9 GPIOA5 0x0 FLASH_CS1 0x1 GPIO_LCD22_SEL 8 GPIOA4 0x0 LCD_DATA22 0x1 GPIOA_LCD20_NRTS0_SEL 6 2 GPIOA3 0x0 LCD_DATA20 0x1 UART0_NRTS 0x2 GPIOA_LCD18_NCTS0_SEL 4 2 GPIOA2 0x0 LCD_DATA18 0x1 UART0_NCTS 0x2 GPIOA_LCD17_TXD0_SEL 2 2 GPIOA1 0x0 LCD_DATA17 0x1 UART0_TXD 0x2 GPIOA_LCD16_RXD0_SEL 0 2 GPIOA0 0x0 LCD_DATA16 0x1 UART0_RXD 0x2 IOMUXB_CON IOMUXB_CON

0x34

VIP_HSADC_SEL 22 VIP 0x0 HSADC 0x1 GPIOD_SDCKE_SEL 21 GPIOD3 0x0 SDRAM_CKE 0x1 GPIOF_UHCVBUS_SEL 20 GPIOF4 0x0 UHC_VBUS 0x1 GPIOF_UHCOCUR_SEL 19 GPIOF3 0x0 UHC_OCUR 0x1 SDTADDR12_GPIOF_SEL 18 SDT_ADDR12 0x0 GPIOF2 0x1 SDTADDR11_GPIOF_SEL 17 SDT_ADDR11 0x0 GPIOF1 0x1 GPIOF_VIPCLK_SEL 16 GPIOF0 0x0 VIP_CLK 0x1 GPIOE_LCD_SEL 15 GPIOE_0_7 0x0 LCD_DATA_8_15 0x1 GPIOD_PWM3_SEL 14 GPIOD7 0x0 PWM3 0x1 GPIOD_PWM2_SEL 13 GPIOD6 0x0 PWM2 0x1 GPIOD_PWM1_SEL 12 GPIOD5 0x0 PWM1 0x1 GPIOD_PWM0_SEL 11 GPIOD4 0x0 PWM0 0x1 GPIOD_SDWPA_SEL 10 GPIOD2 0x0 SD_WPA 0x1 GPIOD_SDCDA_RXD1_SEL 8 2 GPIOD1 0x0 SD_CDA 0x1 UART1_RXD 0x2 GPIOD_SDPCA_TXD1_SEL 6 2 GPIOD0 0x0 SD_PCA 0x1 UART1_RXD 0x2 GPIOC_STCS1_SEL 5 GPIOC7 0x0 ST_CS1 0x1 GPIOC_I2SCLK1_SEL 4 GPIOC6 0x0 I2S_CLK 0x1 GPIOC_I2SSDO_SEL 3 GPIOC5 0x0 I2S_SDO 0x1 GPIOC_I2SSDI_SEL 2 GPIOC4 0x0 I2S_SDI 0x1 GPIOC_I2SLRCK_SEL 1 GPIOC3 0x0 I2S_LRCK 0x1 GPIOC_I2SSCLK_SEL 0 GPIOC2 0x0 I2S_SCLK 0x1 SCU_GPIOUPCON SCU_GPIOUPCON

0x38

SCU_DIVCON2 SCU_DIVCON2

0x3c

I2C I2C controller I2C

0x18020000

MTXR MTXR

0x0

MRXR MRXR

0x4

STXR STXR

0x8

SRXR SRXR

0xc

SADDR SADDR

0x10

IER IER

0x14

ISR ISR

0x18

LCMR LCMR

0x1c

LSR LSR

0x20

CONR CONR

0x24

OPR OPR

0x28

SD SD controller SD

0x18024000

MMU_CTRL MMU_CTRL

0x0

RESERVED31_13 13 19 ENDIANEESE Endian control when CPU access to data buffer. 12 LITTLE_ENDIAN 0x0 BIG_ENDIAN 0x1 MMU_DMA_XFER 11 MMU_DMA_DIR 10 READ 0x0 WRITE 0x1 MMU_BUF_PTR 9 BUF1 0x0 BUF2 0x1 CPU_BUF_PTR 8 BUF1 0x0 BUF2 0x1 BUF2_RST 7 BUF2_END_SIGNAL 6 BUF2_XFER_WIDTH 4 2 BYTE 0x0 HALFWORD 0x1 RESERVED 0x2 WORD 0x3 BUF1_RST 3 BUF1_END_SIGNAL 2 BUF1_XFER_WIDTH 0 2 BYTE 0x0 HALFWORD 0x1 RESERVED 0x2 WORD 0x3 MMU_PNRI MMU_PNRI

0x4

RESERVED31_11 11 21 BUF1_PTR 0 11 CUR_PNRI CUR_PNRI

0x8

RESERVED31_11 11 21 BUF1_PTR 0 11 MMU_PNRII MMU_PNRII

0xc

RESERVED31_11 11 21 BUF2_PTR 0 11 CUR_PNRII CUR_PNRII

0x10

RESERVED31_11 11 21 BUF2_PTR 0 11 MMU_ADDR MMU_ADDR

0x14

RESERVED31_24 24 8 ADDR 0 24 CUR_ADDR CUR_ADDR

0x18

RESERVED31_24 24 8 ADDR 0 24 MMU_DATA MMU_DATA

0x1c

CTRL CTRL

0x20

RESERVED31_14 14 18 PWR_CTRL Power control type for SD/MMC cards 13 CPU The SD/MMC card power is controlled by CPU 0x0 CD The SD/MMC card power is controlled by CD/DAT3 0x1 DETECT_CTRL Card detect type for SD cards 12 SWITCH The card detect function is used by mechanism 0x0 CD The card detect function is used by CD/DAT3 0x1 STOP 11 SD_CLK_EN Run the SD/MMC Card clock 0x0 SD_CLK_DIS Stop the SD/MMC Card clock 0x1 DIVIDER 0 11 INT INT

0x24

RESERVED31_7 7 25 CMD_RSP_STS Command and response transfer interrupt status 6 NO 0x0 YES 0x1 DATA_STS Data transfer interrupt status 5 NO 0x0 YES 0x1 CARD_DETECT_STS Card detect interrupt status 4 NO 0x0 YES 0x1 RESERVED3 3 CMD_RSP_INT_EN Command and response transfer interrupt enable 2 DISABLE 0x0 ENABLE 0x1 DATA_INT_EN Data transfer interrupt enable 1 DISABLE 0x0 ENABLE 0x1 CARD_DETECT_INT_EN Card detect interrupt enable 0 DISABLE 0x0 ENABLE 0x1 CARD CARD

0x28

RESERVED31_7 7 25 SELECT 6 NO 0x0 YES 0x1 PWR_CTRL 5 NO 0x0 YES 0x1 DETECT_INT_EN 4 NO 0x0 YES 0x1 RESERVED3 3 BUSY 2 WR_PROTECT 1 CARD_DETECT 0 CMDREST CMDREST

0x30

SD/MMC command and response transfer register RESERVED31_14 14 18 CMD_XFER Command transfer signal 13 END 0x0 BEGIN 0x1 RSP_XFER Response transfer signal 12 END 0x0 BEGIN 0x1 RSP_TYPE Response transfer type 9 3 R1 0x0 R1b 0x1 R2 0x2 R3 0x3 R6 0x6 CMD_RSP_ERR_STS 8 NO_ERROR 0x0 ERROR 0x1 RESERVED7_6 6 2 CMD_INDEX 0 6 CMDRES CMDRES

0x34

SD/MMC command and response transfer status register RESERVED31_9 9 23 CMD_XFER 8 END 0x0 BEGIN 0x1 RSP_XFER 7 END 0x0 BEGIN 0x1 CMD_RSP_ERR Card command and response error status 6 NO_ERROR 0x0 ERROR 0x1 CMD_RSP_BUS_ERR Card command and response bus conflict error 5 NO_ERROR 0x0 ERROR 0x1 RSP_TIMEOUT_ERR 4 NO_ERROR 0x0 ERROR 0x1 RSP_BIT_ERR 3 NO_ERROR 0x0 ERROR 0x1 RSP_INDEX_ERR 2 NO_ERROR 0x0 ERROR 0x1 RSP_CRC_ERR 1 NO_ERROR 0x0 ERROR 0x1 RSP_END_BIT_ERR 0 NO_ERROR 0x0 ERROR 0x1 DATAT DATAT

0x3c

SD/MMC data transfer register RESERVED_31_14 14 18 DATA_XFER 13 END 0x0 BEGIN 0x1 DATA_XFER_DIR 12 READ 0x0 WRITE 0x1 DATA_BUS_WIDTH 11 1BIT 0x0 4BITS 0x1 DMA_EN 10 DISABLE 0x0 ENABLE 0x1 DATA_XFER_CYCLE 9 SINGLE_LAST 0x0 MULTIPLE 0x1 DATA_XFER_ERR 8 NO_ERROR 0x0 ERROR 0x1 DATA_XFER_TIMEOUT 6 NO_ERROR 0x0 ERROR 0x1 DATA_XFER_CRC_ERR 5 NO_ERROR 0x0 ERROR 0x1 RX_DATA_START_BIT_ERR 4 NO_ERROR 0x0 ERROR 0x1 RX_DATA_END_BIT_ERR 3 NO_ERROR 0x0 ERROR 0x1 DATA_XFER_CRC_STS 0 3 NO_ERROR 0x2 CRC_ERROR 0x5 NO_RSP 0x7 CMD CMD

0x40

RES3 RES3

0x44

RES2 RES2

0x48

RES1 RES1

0x4c

RES0 RES0

0x50

I2S I2S controller I2S

0x18028000

OPR OPR

0x0

I2S_VERSION 24 8 RESERVED23_18 18 6 TX_RESET 17 RX_RESET 16 RESERVED15_7 7 9 HDMA_REQ1_DIS 6 ENABLE 0x0 DISABLE HDMA REQ1 Always 1 0x1 HDMA_REQ2_DIS 5 ENABLE 0x0 DISABLE HDMA REQ2 Always 1 0x1 HDMA_REQ1_CH This bit is to indicate the Hardware DMA IF1 is used for which FIFO 4 TX_FIFO 0x0 RX_FIFO 0x1 HDMA_REQ2_CH his bit is to indicate the Hardware DMA IF2 is used for which FIFO 3 TX_FIFO 0x0 RX_FIFO 0x1 I2S_LOOPBACK 2 NORMAL 0x0 LOOPBACK 0x1 I2S_TX_START 1 I2S_RX_START 0 TXR TXR

0x4

I2S transmit FIFO RXR RXR

0x8

I2S receive FIFO TXCTL TXCTL

0xc

RESERVED31_18 18 14 OVERSAMPLING Oversampling rate = LRCK / SCLK 16 2 32FS 0x0 64FS 0x1 128FS 0x2 RESERVED 0x3 MCLK_DIV 8 8 RESERVED7_6 6 2 SAMPLE_WIDTH 4 2 8BITS 0x0 16BITS 0x1 MONO_STEREO When the bit is set to 1, transmitter is at Mono mode and data output from left channel. 3 STEREO 0x0 MONO 0x1 IF_MODE 1 2 I2S 0x0 LEFT_JUSTIFIED 0x1 RIGHT_JUSTIFIED 0x2 MASTER_SLAVE This bit decides that transmitter acts as a master or slave. 0 SLAVE 0x0 MASTER 0x1 RXCTL RXCTL

0x10

RESERVED31_25 25 7 RX_FIFO_RESET 24 RESERVED23_18 18 6 OVERSAMPLING Oversampling rate = LRCK / SCLK 16 2 32fs 0x0 64fs 0x1 128fs 0x2 MCLK_DIV 8 8 RESERVED7_6 6 2 SAMPLE_WIDTH 4 2 8BITS 0x0 16BITS 0x1 MONO_STEREO 3 STEREO 0x0 MONO 0x1 IF_MODE 1 2 I2S 0x0 LEFT_JUSTIFIED 0x1 RIGHT_JUSTIFIED 0x2 MASTER_SLAVE 0 SLAVE 0x0 MASTER 0x1 FIFOSTS FIFOSTS

0x14

his register shows FIFO status and interrupts trigger level. RESERVED 20 12 TX_INT_TRIG Tx interrupt trigger level. 18 2 ALMOST_EMPTY 0x0 HALF_FULL 0x1 ALMOST_FULL 0x2 RX_INT_TRIG Rx interrupt trigger level. 16 2 ALMOST_EMPTY 0x0 HALF_FULL 0x1 ALMOST_FULL 0x2 RESERVED15_10 10 6 TX_FIFO_HALF 9 RX_FIFO_HALF 8 TX_FIFO_ALMOST_FULL 7 TX_FIFO_ALMOST_EMPTY 6 RX_FIFO_ALMOST_FULL 5 RX_FIFO_ALMOST_EMPTY 4 TX_FIFO_FULL 3 TX_FIFO_EMPTY 2 RX_FIFO_FULL 1 RX_FIFO_EMPTY 0 IER IER

0x18

RESERVED31_3 3 29 TX_FIFO_LEVEL_EN This bit enables the interrupt when Tx FIFO trigger level is reached. 2 RX_FIFO_LEVEL_EN This bit enables the interrupt when Rx FIFO trigger level is reached. 1 RX_FIFO_OVERRUN_EN This bit enables the interrupt when Rx FIFO overrun condition occurred. 0 ISR ISR

0x1c

I2S interrupt status register RESERVED31_3 3 29 TX_FIFO_LEVEL_INT 2 RX_FIFO_LEVEL_INT 1 RX_FIFO_OVERRUN_INT 0 ADC 4 channels 10-bit SAR A/D converter ADC

0x18030000

DATA DATA

0x0

STAT STAT

0x4

CTRL CTRL

0x8

GPIO1 GPIO GPIO1

0x18038000

PEDR PEDR

0x0

PECON PECON

0x4

PFDR PFDR

0x8

PFCON PFCON

0xc

_TEST _TEST

0x20

IEE IEE

0x24

IEF IEF

0x28

ISE ISE

0x34

ISF ISF

0x38

IBEE IBEE

0x44

IBEF IBEF

0x48

IEVE IEVE

0x54

IEVF IEVF

0x58

ICE ICE

0x64

ICF ICF

0x68

ISR ISR

0x74

INTC Interrupt controller INTC

0x18080000

INTC_SCRn INTC_SCRn 0 32 0x0 0x4 ISR ISR

0x104

IPR IPR

0x108

IMR IMR

0x10c

IECR IECR

0x114

ICCR ICCR

0x118

ISCR ISCR

0x11c

TEST TEST

0x124

ARB AHB bus arbiter ARB

0x18084000

MODE MODE

0x0

PRIOn PRIOn 0 15 0x4 0x4 MAILBOX CPU-DSP mailbox MAILBOX

0x18088000

MAILBOX_ID MAILBOX_ID

0x0

H2C_STA H2C_STA

0x10

H2Cn_DATA H2Cn_DATA 0 4 0x20 0x8 H2Cn_CMD H2Cn_CMD 0 4 0x24 0x8 C2H_STA C2H_STA

0x40

C2Hn_DATA C2Hn_DATA 0 4 0x50 0x8 C2Hn_CMD C2Hn_CMD 0 4 0x54 0x8 HDMA AHB DMA HDMA

0x18090000

CON CON0

0x0

CON1

0x4

ISRC ISRC0

0x8

ISRC1

0x14

IDST IDST0

0xc

IDST1

0x18

ICNT ICNT0

0x10

ICNT1

0x1c

CSRC CSRC0

0x20

CSRC1

0x2c

CDST CDST0

0x24

CDST1

0x30

CCNT CCNT0

0x28

CCNT1

0x34

ISR ISR

0x38

DSR DSR

0x3c

ISCNT ISCNT0

0x40

ISCNT1

0x4c

IPNCNTD IPNCNTD0

0x44

IPNCNTD1

0x50

IADDR_BS IADDR_BS0

0x48

IADDR_BS1

0x54

CSCNT CSCNT0

0x58

CSCNT1

0x64

CPNCNTD CPNCNTD0

0x5c

CPNCNTD1

0x68

CADDR_BS CADDR_BS0

0x60

CADDR_BS1

0x6c

PACNT PACNT0

0x70

PACNT1

0x74

A2A_DMA AHB-to-AHB bridge with DMA A2A_DMA

0x18094000

CON CON0

0x0

CON1

0x1c

RESERVED31_15 15 17 AUTO_RELOAD 14 DISABLE 0x0 ENABLE 0x1 DMA_HW_EN 13 DISABLE 0x0 ENABLE 0x1 INT_EN 12 DISABLE 0x0 ENABLE 0x1 ON_THE_FLY On the fly transfer can be applied on DMA which source and destination addresses are at the different bus domain. 11 DISABLE 0x0 ENABLE 0x1 XFER_MODE Burst size 9 2 SINGLE 0x0 INCR4 0x1 INCR8 0x2 INCR16 0x3 HDREQ_SRC 7 2 SDMMC 0x0 SRC_INC 6 INCREMENT 0x0 FIXED 0x1 DST_INC 5 INCREMENT 0x0 FIXED 0x1 DMA_SW_CMD 3 2 NO_CMD 0x0 START_SW_DMA 0x1 PAUSE_SW_DMA 0x2 CANCEL_SW_DMA 0x3 XFER_WIDTH 1 2 BYTE 0x0 HALFWORD 0x1 WORD 0x2 RESERVED 0x3 DMA_MODE 0 HW_BLOCK_MODE 0x0 SW_MODE 0x1 ISRC ISRC0

0x4

ISRC1

0x20

A2A DMA initial source address register. IDST IDST0

0x8

IDST1

0x24

A2A DMA initial destination address register. ICNT ICNT0

0xc

ICNT1

0x28

RESERVED31_16 16 16 CNT DMA initial terminate count register for channel x. 0 16 CSRC CSRC0

0x10

CSRC1

0x2c

A2A DMA current source address register. CDST CDST0

0x14

CDST1

0x30

A2A DMA current destination address register. CCNT CCNT0

0x18

CCNT1

0x34

RESERVED31_16 16 16 CNT 0 16 INT_STS INT_STS

0x38

RESERVED31_4 4 28 AHB2_ERR_INT 3 NO_ERROR 0x0 ERROR 0x1 AHB1_ERR_INT 2 NO_ERROR 0x0 ERROR 0x1 CHANNEL1_INT Channel 1 Interrupt active, clear interrupt after write. 1 NOT_ACTIVE 0x0 ACTIVE 0x1 CHANNEL0_INT Channel 0 Interrupt active, clear interrupt after write. 0 NOT_ACTIVE 0x0 ACTIVE 0x1 DMA_STS DMA_STS

0x3c

RESERVED31_2 2 30 CHANNEL1_BUSY 1 FREE 0x0 BUSY 0x1 CHANNEL0_BUSY 0 FREE 0x0 BUSY 0x1 ERR_ADR ERR_ADR0

0x40

ERR_ADR1

0x48

ERR_OP ERR_OP0

0x44

ERR_OP1

0x4c

RESERVED31_1 1 31 DIR 0 READ 0x0 WRITE 0x1 LCNT LCNT0

0x50

LCNT1

0x54

RESERVED31_3 3 29 LOCK_CNT Bus lock counts at on-the-fly mode. 0 3 NEVER 0x0 16BITS 0x1 32BITS 0x2 64BITS 0x3 128BITS 0x4 256BITS 0x5 512BITS 0x6 1024BITS 0x7 DOMAIN DOMAIN

0x58

RESERVED31_4 4 28 CH1_DST_DOMAIN 3 AHB0 0x0 AHB1 0x1 CH1_SRC_DOMAIN 2 AHB0 0x0 AHB1 0x1 CH0_DST_DOMAIN 1 AHB0 0x0 AHB1 0x1 CH0_SRC_DOMAIN 0 AHB0 0x0 AHB1 0x1 UDC USB 2.0 Device Controller UDC

0x180a0000

DEV_CTL DEV_CTL

0x8

RESERVED 10 22 TEST_MODE 9 CSR_DONE 8 SOFT_POR 7 DEV_PHYBUS16_8 6 DEV_RESUME 5 DEV_SOFT_CN 4 DEV_SELF_PWR 3 DEV_RMTWKP 2 DEV_SPEED 0 2 HS High Speed 0x0 DEV_INFO DEV_INFO

0x10

RESERVED 23 9 DEV_SPEED 21 2 HS High Speed 0x0 FS Full Speed 0x3 VBUS_SYNC 20 DISCONNECTION 0x0 CONNECTION 0x1 DEV_ALTINTF 16 4 INTF_NUMBER 12 4 CFG_NUMBER 8 4 DEV_EN 7 DEV_ADDRESS 0 7 EN_INT EN_INT

0x14

RESERVED31_27 27 5 TEST_PKT 26 TEST_K 25 TEST_J 24 TEST_SE0_NAK 23 EN_IIN15_INTR 22 EN_BIN14_INTR 21 EN_BOUT13_INTR 20 EN_IIN12_INTR 19 EN_BIN11_INTR 18 EN_BOUT10_INTR 17 EN_IIN9_INTR 16 EN_BIN8_INTR 15 EN_BOUT7_INTR 14 EN_IIN6_INTR 13 EN_BIN5_INTR 12 EN_BOUT4_INTR 11 EN_IIN3_INTR 10 EN_BIN2_INTR 9 EN_BOUT1_INTR 8 RESERVED 7 EN_SUSP_INTR 6 EN_RSUME_INTR 5 EN_USBRST_INTR 4 EN_OUT0_INTR 3 EN_IN0_INTR 2 EN_SETUP_INTR 1 EN_SOF_INTR 0 INT2FLAG INT2FLAG

0x18

RESERVED31_27 27 5 TEST_PKT 26 TEST_K 25 TEST_J 24 TEST_SE0_NAK 23 IIN15_INTR 22 BIN14_INTR 21 BOUT13_INTR 20 IIN12_INTR 19 BIN11_INTR 18 BOUT10_INTR 17 IIN9_INTR 16 BIN8_INTR 15 BOUT7_INTR 14 IIN6_INTR 13 BIN5_INTR 12 BOUT4_INTR 11 IIN3_INTR 10 BIN2_INTR 9 BOUT1_INTR 8 RESERVED7 7 SUSP_INTR 6 RSUME_INTR 5 USBRST_INTR 4 OUT0_INTR 3 IN0_INTR 2 SETUP_INTR 1 SOF_INTR 0 INTCON INTCON

0x1c

RESERVED 3 29 INT0MODE 2 ACTIVE_LOW 0x0 ACTIVE_HIGH 0x1 INT0TYPE 1 LEVEL_TRIGGER 0x0 EDGE_TRIGGER 0x1 INT0EN 0 DISABLE 0x0 ENABLE 0x1 SETUP1 SETUP1

0x20

wValue 16 16 bRequest 8 8 GetStatus 0x0 ClearFeature 0x1 Reserved2 0x2 SetFeature 0x3 Reserved4 0x4 SetAddress 0x5 GetDescriptor 0x6 SetDescriptor 0x7 GetConfiguration 0x8 SetConfiguration 0x9 GetInterface 0xa SetInterface 0xb SyncFrame 0xc bmRequestTypeDir 7 Host2Device 0x0 Device2Host 0x1 bmRequestType 5 2 Standard 0x0 Class 0x1 Vendor 0x2 bmRequestTypeRecipient 0 5 Device 0x0 Interface 0x1 Endpoint 0x2 Other 0x3 SETUP2 SETUP2

0x24

wLength 16 16 wIndex 0 16 AHBCON AHBCON

0x28

RESERVED 4 28 MID 0 4 RX0STAT RX0STAT

0x30

RESERVED31_26 26 6 RX0OVF 25 RX0FULL 24 RESERVED23_19 19 5 RX0ACK 18 RX0ERR 17 RX0VOID 16 RESERVED15_11 11 5 RX0LEN 0 11 RX0CON RX0CON

0x34

RESERVED31_8 8 24 RX0ACKINTEN 7 RX0ERRINTEN 6 RX0VOIDINTEN 5 EP0EN 4 RX0NAK 3 RX0STALL 2 RX0CLR 1 RX0FFRC 0 RX0DMACTLO RX0DMACTLO

0x38

RESERVED31_1 1 31 DMA0OUTSTA 0 RX0DMAOUTLMADDR RX0DMAOUTLMADDR

0x3c

LM0OUTADDR DMA word aligned buffer address 0 32 TX0STAT TX0STAT

0x40

RESERVED31_19 19 13 TX0ACK 18 TX0ERR 17 TX0VOID 16 RESERVED15_11 11 5 TX0LEN 0 11 TX0CON TX0CON

0x44

RESERVED31_7 7 25 TX0ACKINTEN 6 TX0ERRINTEN 5 TX0VOIDINTEN 4 RESERVED3 3 TX0NAK 2 TX0STALL 1 TX0CLR 0 TX0BUF TX0BUF

0x48

RESERVED31_2 2 30 TX0URF 1 TX0FULL 0 TX0DMAINCTL TX0DMAINCTL

0x4c

RESERVED31_1 1 31 DMA0INSTA 0 TX0DMALM_IADDR TX0DMALM_IADDR

0x50

LM0INADDR DMA word aligned buffer address 0 32 RX_BLK_STAT RX1STAT

0x54

RX4STAT

0x8c

RX7STAT

0xc4

RX10STAT

0xfc

RX13STAT

0x134

RESERVED31_26 26 6 RXOVF 25 RXFULL 24 RESERVED23_20 20 4 RX_CF_INT 19 RXACK 18 RXERR 17 RXVOID 16 RESERVED15_11 11 5 RXCNT 0 11 RX_BLK_CON RX1CON

0x58

RX4CON

0x90

RX7CON

0xc8

RX10CON

0x100

RX13CON

0x138

RESERVED31_14 14 18 RXSTALL_AUTOCLR 13 RX_CF_INTE 12 RXENDP_NUM 8 4 RXACKINTEN 7 RXERRINTEN 6 RXVOIDINTEN 5 EPEN 4 RXNAK 3 RXSTALL 2 RXCLR 1 RXFFRC 0 RX_BLK_DMACTLO RX1DMACTLO

0x5c

RX4DMACTLO

0x94

RX7DMACTLO

0xcc

RX10DMACTLO

0x104

RX13DMACTLO

0x13c

RESERVED31_1 1 31 DMAOUTSTA 0 RX_BLK_DMAOUTLMADDR RX1DMAOUTLMADDR

0x60

RX4DMAOUTLMADDR

0x98

RX7DMAOUTLMADDR

0xd0

RX10DMAOUTLMADDR

0x108

RX13DMAOUTLMADDR

0x140

LMOUTADDR Address of word aligned buffer 0 32 TX_BLK_STAT TX2STAT

0x64

TX5STAT

0xc9

TX8STAT

0xd4

TX11STAT

0x10c

TX14STAT

0x144

RESERVED31_21 21 11 TX_CF_INT 20 TXDMA_DN 19 TXACK 18 TXERR 17 TXVOID 16 RESERVED15_11 11 5 TXLEN 0 11 TX_BLK_CON TX2CON

0x68

TX5CON

0xa0

TX8CON

0xd8

TX11CON

0x110

TX14CON

0x148

RESERVED31_14 14 18 TXSTALL_AUTOCLR 13 TX_CF_INTE 12 TXENDP_NUM 8 4 TXDMADN_EN 7 TXACKINTEN 6 TXERRINTEN 5 TXVOIDINTEN 4 TXEPEN 3 TXNAK 2 TXSTALL 1 TXCLR 0 TX_BLK_BUF TX2BUF

0x6c

TX5BUF

0xa4

TX8BUF

0xdc

TX11BUF

0x114

TX14BUF

0x14c

RESERVED31_4 4 28 TXDS1 3 TXDS0 2 TXURF 1 TXFULL 0 TX_BLK_DMAINCTL TX2DMAINCTL

0x70

TX5DMAINCTL

0xa8

TX8DMAINCTL

0xe0

TX11DMAINCTL

0x118

TX14DMAINCTL

0x150

RESERVED31_1 1 31 DMAINSTA 0 TX_BLK_DMALM_IADDR TX2DMALM_IADDR

0x74

TX5DMALM_IADDR

0xac

TX8DMALM_IADDR

0xe4

TX11DMALM_IADDR

0x11c

TX14DMALM_IADDR

0x154

LMINADDR DMA word aligned buffer address 0 32 TX_INT_STAT TX3STAT

0x78

TX6STAT

0xb0

TX9STAT

0xe8

TX12STAT

0x120

TX15STAT

0x158

RESERVED31_20 20 12 TX_CF_INT 19 TXACK 18 TXERR 17 TXVOID 16 RESERVED15_11 11 5 TXLEN 0 11 TX_INT_CON TX3CON

0x7c

TX6CON

0xb4

TX9CON

0xec

TX12CON

0x124

TX15CON

0x15c

RESERVED31_14 14 18 TXSTALL_AUTOCLR 13 TX_CF_INTE 12 TXENDP_NUM 8 4 RESERVED7 7 TXACKINTEN 6 TXERRINTEN 5 TXVOIDINTEN 4 TXEPEN 3 TXNAK 2 TXSTALL 1 TXCLR 0 TX_INT_BUF TX3BUF

0x80

TX6BUF

0xb8

TX9BUF

0xf0

TX12BUF

0x128

TX15BUF

0x160

RESERVED31_2 2 30 TXURF 1 TXFULL 0 TX_INT_DMAINCTL TX3DMAINCTL

0x84

TX6DMAINCTL

0xbc

TX9DMAINCTL

0xf4

TX12DMAINCTL

0x12c

TX15DMAINCTL

0x164

RESERVED31_1 1 31 DMAINSTA 0 TX_INT_DMALM_IADDR TX3DMALM_IADDR

0x88

TX6DMALM_IADDR

0xc0

TX9DMALM_IADDR

0xf8

TX12DMALM_IADDR

0x130

TX15DMALM_IADDR

0x168

LMINADDR DMA word aligned buffer address 0 32 UHC USB 2.0 Host Controller UHC

0x180a4000

SDRSTMC SDRSTMC Static/SDRAM Memory Controller SDRSTMC

0x180b0000

MCSDR_MODE MCSDR_MODE

0x100

MCSDR_ADDMAP MCSDR_ADDMAP

0x104

MCSDR_ADDCFG MCSDR_ADDCFG

0x108

MCSDR_BASIC MCSDR_BASIC

0x10c

MCSDR_T_REF MCSDR_T_REF

0x110

MCSDR_T_RFC MCSDR_T_RFC

0x114

MCSDR_T_MRD MCSDR_T_MRD

0x118

MCSDR_T_RP MCSDR_T_RP

0x120

MCSDR_T_RCD MCSDR_T_RCD

0x124

MCST0_T_CEWD MCST0_T_CEWD

0x200

MCST0_T_CE2WE MCST0_T_CE2WE

0x204

MCST0_WEWD MCST0_WEWD

0x208

MCST0_T_WE2CE MCST0_T_WE2CE

0x20c

MCST0_T_CEWDR MCST0_T_CEWDR

0x210

MCST0_T_CE2RD MCST0_T_CE2RD

0x214

MCST0_T_RDWD MCST0_T_RDWD

0x218

MCST0_T_RD2CE MCST0_T_RD2CE

0x21c

MCST0_BASIC MCST0_BASIC

0x220

MCST1_T_CEWD MCST1_T_CEWD

0x300

MCST1_T_CE2WE MCST1_T_CE2WE

0x304

MCST1_WEWD MCST1_WEWD

0x308

MCST1_T_WE2CE MCST1_T_WE2CE

0x30c

MCST1_T_CEWDR MCST1_T_CEWDR

0x310

MCST1_T_CE2RD MCST1_T_CE2RD

0x314

MCST1_T_RDWD MCST1_T_RDWD

0x318

MCST1_T_RD2CE MCST1_T_RD2CE

0x31c

MCST1_BASIC MCST1_BASIC

0x320

VIP VIP Video Input Processor VIP

0x180c0000

NANDC NAND Flash Controller NANDC

0x180e8000

FMCTL FMCTL

0x0

FMWAIT FMWAIT

0x4

FLCTL FLCTL

0x8

BCHCTL BCHCTL

0xc

BCHST BCHST

0xd0

FLASH_DATAn FLASH_DATAn 0 4 0x200 0x200 ADDRn ADDRn 0 4 0x204 0x200 FLASH_CMDn FLASH_CMDn 0 4 0x208 0x200 PAGE_BUF PAGE_BUF

0xa00

SPARE_BUF SPARE_BUF

0x1200

LCDC LCD Interface Controller LCDC

0x186e8000

LCDC_CTRL LCDC_CTRL

0x0

RESERVED15_14 14 2 ALPHA_24B 13 UVBUFEXCH 12 ALPHA 9 3 YMIX 8 MCU 7 RGB24B 6 START_EVEN 5 EVEN_EN 4 RGB_DUMMY 2 2 PARALLEL 0x0 RESERVED 0x1 SERIAL_UPS501 0x2 SERIAL_UPS502 0x3 ENABLE 1 DISABLE 0x0 ENABLE 0x1 STOP 0 MCU_CTRL MCU_CTRL

0x4

RESERVED15 15 ALPHA_BASE 8 7 RESERVED1 7 ALPHA_BUF_EN 6 LCD_RS 5 RESERVED0 2 3 BUFF_START 1 BYPASS 0 HOR_PERIOD HOR_PERIOD

0x8

VERT_PERIOD VERT_PERIOD

0xc

HOR_PW HOR_PW

0x10

VERT_PW VERT_PW

0x14

HOR_BP HOR_BP

0x18

VERT_BP VERT_BP

0x1c

HOR_ACT HOR_ACT

0x20

VERT_ACT VERT_ACT

0x24

LINE0_YADDR LINE0_YADDR

0x28

LINE0_UVADDR LINE0_UVADDR

0x2c

LINE1_YADDR LINE1_YADDR

0x30

LINE1_UVADDR LINE1_UVADDR

0x34

LINE2_YADDR LINE2_YADDR

0x38

LINE2_UVADDR LINE2_UVADDR

0x3c

LINE3_YADDR LINE3_YADDR

0x40

LINE3_UVADDR LINE3_UVADDR

0x44

START_X START_X

0x48

START_Y START_Y

0x4c

DELTA_X DELTA_X

0x50

DELTA_Y DELTA_Y

0x54

LCDC_INTR_MASK LCDC_INTR_MASK

0x58

ALPHA_ALX ALPHA_ALX

0x5c

ALPHA_ATY ALPHA_ATY

0x60

ALPHA_ARX ALPHA_ARX

0x64

ALPHA_ABY ALPHA_ABY

0x68

ALPHA_BLX ALPHA_BLX

0x6c

ALPHA_BTY ALPHA_BTY

0x70

ALPHA_BRX ALPHA_BRX

0x74

ALPHA_BBY ALPHA_BBY

0x78

LCDC_STA LCDC_STA

0x7c

LCD_COMMAND LCD_COMMAND

0x1000

LCD_DATA LCD_DATA

0x1004

LCD_BUFF LCD_BUFF

0x2000

HSADC High Speed ADC HSADC

0x186ec000

DATA DATA

0x0

CTRL CTRL

0x4

IER IER

0x8

ISR ISR

0xc

DWDMA DMA Controller DWDMA

0x186f0000

DWDMA_SARn DWDMA_SARn 0 4 0x0 0x58 Source address register DWDMA_DARn DWDMA_DARn 0 4 0x8 0x58 Destination address register DWDMA_LLPn DWDMA_LLPn 0 4 0x10 0x58 Linked List pointer register DWDMA_CTL_Ln DWDMA_CTL_Ln 0 4 0x18 0x58 RESERVED31_29 29 3 LLP_SRC_EN 28 LLP_DST_EN 27 SMS 25 2 DMS 23 2 TT_FC 20 3 MEM2MEM_DWDMA flow controller DWDMA_AHB_DMAC 0x0 MEM2PERI_DWDMA flow controller DWDMA_AHB_DMAC 0x1 PERI2MEM_DWDMA flow controller DWDMA_AHB_DMAC 0x2 PERI2PERI_DWDMA flow controller DWDMA_AHB_DMAC 0x3 PERI2MEM_PERI flow controller Peripheral 0x4 PERI2PERI_SRC_PERI flow controller Source Peripheral 0x5 MEM2PERI_PERI flow controller Peripheral 0x6 PERI2PERI_DST_PERI flow controller Destination Peripheral 0x7 RESERVED19 19 DST_SCATTER_EN 18 SRC_GATHER_EN 17 SRC_MSIZE Number of data items to be transferred (of width CTLx.SRC_TR_WIDTH or CTLx.DST_TR_WIDTH) 14 3 1 0x0 4 0x1 8 0x2 16 0x3 32 0x4 DST_MSIZE 11 3 1 0x0 4 0x1 8 0x2 16 0x3 32 0x4 SINC Source Address Increment. 9 2 INCREMENT 0x0 DECREMENT 0x1 FIXED2 0x2 FIXED3 0x3 DINC 7 2 INCREMENT 0x0 DECREMENT 0x1 FIXED2 0x2 FIXED3 0x3 SRC_TR_WIDTH 4 3 BYTE 0x0 HALFWORD 0x1 WORD 0x2 DST_TR_WIDTH 1 3 BYTE 0x0 HALFWORD 0x1 WORD 0x2 INT_EN 0 DWDMA_CTL_Hn DWDMA_CTL_Hn 0 4 0x1c 0x58 RESERVED31_13 13 19 DONE 12 BLOCK_TS 0 12 DWDMA_SSTATn DWDMA_SSTATn 0 4 0x20 0x58 DWDMA_DSTATn DWDMA_DSTATn 0 4 0x28 0x58 DWDMA_SSTATARn DWDMA_SSTATARn 0 4 0x30 0x58 DWDMA_DSTATARn DWDMA_DSTATARn 0 4 0x38 0x58 DWDMA_CFG_Ln DWDMA_CFG_Ln 0 4 0x40 0x58 RELOAD_DST 31 RELOAD_SRC 30 MAX_ABRST 20 10 SRC_HS_POL Source Handshaking Interface Polarity. 19 ACTIVE_HIGH 0x0 ACTIVE_LOW 0x1 DST_HS_POL Destination Handshaking Interface Polarity. 18 ACTIVE_HIGH 0x0 ACTIVE_LOW 0x1 LOCK_B 17 LOCK_CH 16 LOCK_B_L 14 2 LOCK_CH_L 12 2 HS_SEL_SRC 11 HW 0x0 SW 0x1 HS_SEL_DST 10 HW 0x0 SW 0x1 FIFO_EMPTY Indicates if there is data left in the channel FIFO. 9 NOT_EMPTY 0x0 EMPTY 0x1 CH_SUSP 8 SUSPEND 0x1 CH_PRIOR Channel priority. A priority of 7 is the highest priority, and 0 is the lowest. 5 3 RESERVED4_0 0 5 DWDMA_CFG_Hn DWDMA_CFG_Hn 0 4 0x44 0x58 DWDMA_SGRn DWDMA_SGRn 0 4 0x48 0x58 Source Gather Register DWDMA_DSRn DWDMA_DSRn 0 4 0x50 0x58 RAW_TFR RAW_TFR

0x2c0

RAW_BLOCK RAW_BLOCK

0x2c8

RAW_SRCTRAN RAW_SRCTRAN

0x2d0

RAW_DSTTRAN RAW_DSTTRAN

0x2d8

RAW_ERR RAW_ERR

0x2e0

STATUS_TFR STATUS_TFR

0x2e8

STATUS_BLOCK STATUS_BLOCK

0x2f0

STATUS_SRCTRAN STATUS_SRCTRAN

0x2f8

STATUS_DSTTRAN STATUS_DSTTRAN

0x300

STATUS_ERR STATUS_ERR

0x308

MASK_TFR MASK_TFR

0x310

MASK_BLOCK MASK_BLOCK

0x318

MASK_SRCTRAN MASK_SRCTRAN

0x320

MASK_DSTTRAN MASK_DSTTRAN

0x328

MASK_ERR MASK_ERR

0x330

CLEAR_TFR CLEAR_TFR

0x338

CLEAR_BLOCK CLEAR_BLOCK

0x340

CLEAR_SRCTRAN CLEAR_SRCTRAN

0x348

CLEAR_DSTTRAN CLEAR_DSTTRAN

0x350

CLEAR_ERR CLEAR_ERR

0x358

STATUS_INT STATUS_INT

0x360

REQ_SRC REQ_SRC

0x368

REQ_DST REQ_DST

0x370

S_REQ_SRC S_REQ_SRC

0x378

S_REQ_DST S_REQ_DST

0x380

L_REQ_SRC L_REQ_SRC

0x388

L_REQ_DST L_REQ_DST

0x390

DMA_CFG DMA_CFG

0x398

RESERVED31_1 1 31 DMA_EN Global DMA enable. 0 DISABLE 0x0 ENABLE 0x1 DMA_CHEN DMA_CHEN

0x3a0

Channel enable register. RESERVED_31_12 12 20 CHANNEL_EN_WR_EN Channel enable write enable. 8 4 CH0_EN_WR_EN 0x1 CH1_EN_WR_EN 0x2 CH2_EN_WR_EN 0x4 CH3_EN_WR_EN 0x8 RESERVED7_4 4 4 CHANNEL_EN 0 4 CH0_EN 0x1 CH1_EN 0x2 CH2_EN 0x4 CH3_EN 0x8 CACHE CACHE Controller CACHE

0xefff0000

DEVID DEVID

0x0

CACHE_EN 31 CACHEOP CACHEOP

0x4

ADDRESS 2 30 OPCODE 0 2 NOP 0x0 INVALIDATE_SINGLE_ENTRY 0x1 INVALIDATE_WAY 0x2 CACHELKDN CACHELKDN

0x8

RESERVED31_2 2 30 WAY_SELECT 0 2 LOCK_NONE 0x0 LOCK_WAY0 0x1 LOCK_WAY1 0x2 MEMMAPA MEMMAPA

0x10

MEMBASE 25 7 MAPSIZE 0 8 MAP_128MB 0xf8 MAP_64MB 0xfc MAP_32MB 0xfe MEMMAPB MEMMAPB

0x14

MEMBASE 25 7 MAPSIZE 0 8 MAP_128MB 0xf8 MAP_64MB 0xfc MAP_32MB 0xfe MEMMAPC MEMMAPC

0x18

MEMBASE 25 7 MAPSIZE 0 8 MAP_128MB 0xf8 MAP_64MB 0xfc MAP_32MB 0xfe MEMMAPD MEMMAPD

0x1c

MEMBASE 25 7 MAPSIZE 0 8 MAP_128MB 0xf8 MAP_64MB 0xfc MAP_32MB 0xfe PFCNTRA_CTRL PFCNTRA_CTRL

0x20

PFCNTRA PFCNTRA

0x24

PFCNTRB_CTRL PFCNTRB_CTRL

0x28

PFCNTRB PFCNTRB

0x2c

PWM PWM timer PWM 1

0x1802c000

0x1802c010

0x1802c020

0x1802c030

PWMTn_CNTR PWMTn_CNTR

0x0

TC Main PWM counter. Range 0 - ((2^32)-1) 0 32 PWMTn_HRC PWMTn_HRC

0x4

HR Hight reference/capture register 0 32 PWMTn_LRC PWMTn_LRC

0x8

TR PWM total reference/capture register 0 32 PWMTn_CTRL PWMTn_CTRL

0xc

RESERVED31_13 13 19 PRESCALE 9 4 1_2th 0x0 1_4th 0x1 1_8th 0x2 1_16th 0x3 1_32th 0x4 1_64th 0x5 1_128th 0x6 1_256th 0x7 1_512th 0x8 1_1024th 0x9 1_2048th 0xa 1_4096th 0xb 1_8192th 0xc 1_16384th 0xd 1_32768th 0xe 1_65536th 0xf CAPTURE_EN Capture mode enable 8 DISABLE 0x0 ENABLE 0x1 PWM_RST 7 RESET 0x1 INT_STS Interrupt status and clear bit. Write 1 to clear interrupt flag. 6 INT_EN PWM timer interrupt enable/disable. PWM timer will assert an interrupt when PWMTx_CNTR value is equal to the value of PWMTx_LRC or PWMTx_HRC. 5 DISABLE 0x0 ENABLE 0x1 SINGLE_MOD In single mode PWMTx_CNTR is not increased anymore after it reaches value equal to the PWMTx_LRC value. In periodic mode PWMTx_CNTR is restarted after it reaches value equal to the PWMTx_LRC value. 4 PERIODIC 0x0 SINGLE 0x1 PWM_OUT_EN PWM output enable/disable. 3 DISABLE 0x0 ENABLE 0x1 RESERVED2_1 1 2 PWM_EN PWM timer enable/disable. 0 DISABLE 0x0 ENABLE 0x1 TIMER Timer module TIMER 1

0x18000000

0x18000010

0x18000020

TMRnLR TMRnLR 0 1 n*0x10 TMRnCVR TMRnCVR 0 1 0x04+n*0x10 TMRnCON TMRnCON 0 1 0x08+n*0x10 UART UART UART 1

0x18004000

0x18008000

UARTn_RBR UARTn_RBR 0 2 0x0 0x0 UARTn_THR UARTn_THR 0 2 0x0 0x0 UARTn_DLL UARTn_DLL 0 2 0x0 0x0 UARTn_DLH UARTn_DLH 0 2 0x4 0x0 UARTn_IER UARTn_IER 0 2 0x4 0x0 UARTn_IIR UARTn_IIR 0 2 0x8 0x0 UARTn_FCR UARTn_FCR 0 2 0x8 0x0 UARTn_LCR UARTn_LCR 0 2 0xc 0x0 UARTn_MCR UARTn_MCR 0 2 0x10 0x0 UARTn_LSR UARTn_LSR 0 2 0x14 0x0 UARTn_MSR UARTn_MSR 0 2 0x18 0x0