/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * $Id$ * * Copyright © 2011 by Amaury Pouly * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef CLKCTRL_IMX233_H #define CLKCTRL_IMX233_H #include "config.h" #include "system.h" #include "cpu.h" #define HW_CLKCTRL_BASE 0x80040000 #define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0)) #define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS (1 << 18) #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP 20 #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20) #define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10)) #define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20)) #define HW_CLKCTRL_CPU__DIV_CPU_BP 0 #define HW_CLKCTRL_CPU__DIV_CPU_BM 0x3f #define HW_CLKCTRL_CPU__BUSY_REF_CPU (1 << 28) #define HW_CLKCTRL_HBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30)) #define HW_CLKCTRL_HBUS__DIV_BP 0 #define HW_CLKCTRL_HBUS__DIV_BM 0x1f #define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40)) #define HW_CLKCTRL_XBUS__DIV_BP 0 #define HW_CLKCTRL_XBUS__DIV_BM 0x3ff #define HW_CLKCTRL_XBUS__BUSY (1 << 31) #define HW_CLKCTRL_XTAL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50)) #define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26) #define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28) #define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30) #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) #define HW_CLKCTRL_PIX__DIV_BM 0xfff #define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) #define HW_CLKCTRL_SSP__DIV_BM 0x1ff #define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110)) #define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1) #define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5) #define HW_CLKCTRL_CLKSEQ__BYPASS_CPU (1 << 7) #define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0)) #define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0)) #define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1)) #define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2)) #define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3)) #define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f #define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) #define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) #define HW_CLKCTRL_RESET_CHIP 0x2 #define HW_CLKCTRL_RESET_DIG 0x1 enum imx233_clock_t { CLK_PIX, /* div, frac */ CLK_SSP, /* div, frac */ CLK_IO, /* div */ CLK_CPU, /* div, frac */ CLK_AHB /* div */ }; enum imx233_xtal_clkt_t { XTAL_FILT = 1 << 30, XTAL_DRI = 1 << 28, XTAL_TIMROT = 1 << 26, }; /* can use a mask of clocks */ void imx233_enable_xtal_clock(enum imx233_xtal_clkt_t xtal_clk, bool enable); /* only use it for non-fractional clocks (ie not for IO) */ void imx233_enable_clock(enum imx233_clock_t clk, bool enable); void imx233_set_clock_divisor(enum imx233_clock_t clk, int div); /* call with fracdiv=0 to disable it */ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass); void imx233_enable_usb_pll(bool enable); #endif /* CLKCTRL_IMX233_H */