/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 2.1.7 * XML versions: stmp3600:2.4.0 * * Copyright (C) 2013 by Amaury Pouly * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN__STMP3600__EMI__H__ #define __HEADERGEN__STMP3600__EMI__H__ #define REGS_EMI_BASE (0x80020000) #define REGS_EMI_VERSION "2.4.0" /** * Register: HW_EMI_CTRL * Address: 0 * SCT: yes */ #define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0)) #define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4)) #define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8)) #define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc)) #define BP_EMI_CTRL_SFTRST 31 #define BM_EMI_CTRL_SFTRST 0x80000000 #define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) #define BP_EMI_CTRL_CLKGATE 30 #define BM_EMI_CTRL_CLKGATE 0x40000000 #define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) #define BP_EMI_CTRL_CE3_MODE 3 #define BM_EMI_CTRL_CE3_MODE 0x8 #define BV_EMI_CTRL_CE3_MODE__STATIC 0x0 #define BV_EMI_CTRL_CE3_MODE__DRAM 0x1 #define BF_EMI_CTRL_CE3_MODE(v) (((v) << 3) & 0x8) #define BF_EMI_CTRL_CE3_MODE_V(v) ((BV_EMI_CTRL_CE3_MODE__##v << 3) & 0x8) #define BP_EMI_CTRL_CE2_MODE 2 #define BM_EMI_CTRL_CE2_MODE 0x4 #define BV_EMI_CTRL_CE2_MODE__STATIC 0x0 #define BV_EMI_CTRL_CE2_MODE__DRAM 0x1 #define BF_EMI_CTRL_CE2_MODE(v) (((v) << 2) & 0x4) #define BF_EMI_CTRL_CE2_MODE_V(v) ((BV_EMI_CTRL_CE2_MODE__##v << 2) & 0x4) #define BP_EMI_CTRL_CE1_MODE 1 #define BM_EMI_CTRL_CE1_MODE 0x2 #define BV_EMI_CTRL_CE1_MODE__STATIC 0x0 #define BV_EMI_CTRL_CE1_MODE__DRAM 0x1 #define BF_EMI_CTRL_CE1_MODE(v) (((v) << 1) & 0x2) #define BF_EMI_CTRL_CE1_MODE_V(v) ((BV_EMI_CTRL_CE1_MODE__##v << 1) & 0x2) #define BP_EMI_CTRL_CE0_MODE 0 #define BM_EMI_CTRL_CE0_MODE 0x1 #define BV_EMI_CTRL_CE0_MODE__STATIC 0x0 #define BV_EMI_CTRL_CE0_MODE__DRAM 0x1 #define BF_EMI_CTRL_CE0_MODE(v) (((v) << 0) & 0x1) #define BF_EMI_CTRL_CE0_MODE_V(v) ((BV_EMI_CTRL_CE0_MODE__##v << 0) & 0x1) /** * Register: HW_EMI_STAT * Address: 0x10 * SCT: no */ #define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10)) #define BP_EMI_STAT_DRAM_PRESENT 31 #define BM_EMI_STAT_DRAM_PRESENT 0x80000000 #define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000) #define BP_EMI_STAT_STATIC_PRESENT 30 #define BM_EMI_STAT_STATIC_PRESENT 0x40000000 #define BF_EMI_STAT_STATIC_PRESENT(v) (((v) << 30) & 0x40000000) #define BP_EMI_STAT_LARGE_DRAM_ENABLED 29 #define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 #define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000) #define BP_EMI_STAT_WRITE_BUFFER_DATA 1 #define BM_EMI_STAT_WRITE_BUFFER_DATA 0x2 #define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY 0x0 #define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY 0x1 #define BF_EMI_STAT_WRITE_BUFFER_DATA(v) (((v) << 1) & 0x2) #define BF_EMI_STAT_WRITE_BUFFER_DATA_V(v) ((BV_EMI_STAT_WRITE_BUFFER_DATA__##v << 1) & 0x2) #define BP_EMI_STAT_BUSY 0 #define BM_EMI_STAT_BUSY 0x1 #define BV_EMI_STAT_BUSY__NOT_BUSY 0x0 #define BV_EMI_STAT_BUSY__BUSY 0x1 #define BF_EMI_STAT_BUSY(v) (((v) << 0) & 0x1) #define BF_EMI_STAT_BUSY_V(v) ((BV_EMI_STAT_BUSY__##v << 0) & 0x1) /** * Register: HW_EMI_DEBUG * Address: 0x20 * SCT: no */ #define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20)) #define BP_EMI_DEBUG_STATIC_STATE 16 #define BM_EMI_DEBUG_STATIC_STATE 0x70000 #define BF_EMI_DEBUG_STATIC_STATE(v) (((v) << 16) & 0x70000) #define BP_EMI_DEBUG_DRAM_STATE 0 #define BM_EMI_DEBUG_DRAM_STATE 0x1f #define BF_EMI_DEBUG_DRAM_STATE(v) (((v) << 0) & 0x1f) /** * Register: HW_EMI_DRAMSTAT * Address: 0x80 * SCT: no */ #define HW_EMI_DRAMSTAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80)) #define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK 2 #define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK 0x4 #define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) (((v) << 2) & 0x4) #define BP_EMI_DRAMSTAT_BUSY 1 #define BM_EMI_DRAMSTAT_BUSY 0x2 #define BF_EMI_DRAMSTAT_BUSY(v) (((v) << 1) & 0x2) #define BP_EMI_DRAMSTAT_READY 0 #define BM_EMI_DRAMSTAT_READY 0x1 #define BF_EMI_DRAMSTAT_READY(v) (((v) << 0) & 0x1) /** * Register: HW_EMI_DRAMCTRL * Address: 0x90 * SCT: yes */ #define HW_EMI_DRAMCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x0)) #define HW_EMI_DRAMCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x4)) #define HW_EMI_DRAMCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x8)) #define HW_EMI_DRAMCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0xc)) #define BP_EMI_DRAMCTRL_EMICLK_DIVIDE 24 #define BM_EMI_DRAMCTRL_EMICLK_DIVIDE 0x7000000 #define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v) (((v) << 24) & 0x7000000) #define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE 23 #define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE 0x800000 #define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) (((v) << 23) & 0x800000) #define BP_EMI_DRAMCTRL_EMICLK_ENABLE 21 #define BM_EMI_DRAMCTRL_EMICLK_ENABLE 0x200000 #define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v) (((v) << 21) & 0x200000) #define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE 20 #define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE 0x100000 #define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v) (((v) << 20) & 0x100000) #define BP_EMI_DRAMCTRL_DRAM_TYPE 16 #define BM_EMI_DRAMCTRL_DRAM_TYPE 0xf0000 #define BF_EMI_DRAMCTRL_DRAM_TYPE(v) (((v) << 16) & 0xf0000) #define BP_EMI_DRAMCTRL_PRECHARGE 2 #define BM_EMI_DRAMCTRL_PRECHARGE 0x4 #define BF_EMI_DRAMCTRL_PRECHARGE(v) (((v) << 2) & 0x4) #define BP_EMI_DRAMCTRL_SELF_REFRESH 1 #define BM_EMI_DRAMCTRL_SELF_REFRESH 0x2 #define BF_EMI_DRAMCTRL_SELF_REFRESH(v) (((v) << 1) & 0x2) /** * Register: HW_EMI_DRAMADDR * Address: 0xa0 * SCT: yes */ #define HW_EMI_DRAMADDR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x0)) #define HW_EMI_DRAMADDR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x4)) #define HW_EMI_DRAMADDR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x8)) #define HW_EMI_DRAMADDR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0xc)) #define BP_EMI_DRAMADDR_MODE 8 #define BM_EMI_DRAMADDR_MODE 0x100 #define BV_EMI_DRAMADDR_MODE__RBC 0x0 #define BV_EMI_DRAMADDR_MODE__BRC 0x1 #define BF_EMI_DRAMADDR_MODE(v) (((v) << 8) & 0x100) #define BF_EMI_DRAMADDR_MODE_V(v) ((BV_EMI_DRAMADDR_MODE__##v << 8) & 0x100) #define BP_EMI_DRAMADDR_ROW_BITS 4 #define BM_EMI_DRAMADDR_ROW_BITS 0xf0 #define BF_EMI_DRAMADDR_ROW_BITS(v) (((v) << 4) & 0xf0) #define BP_EMI_DRAMADDR_COLUMN_BITS 0 #define BM_EMI_DRAMADDR_COLUMN_BITS 0xf #define BF_EMI_DRAMADDR_COLUMN_BITS(v) (((v) << 0) & 0xf) /** * Register: HW_EMI_DRAMMODE * Address: 0xb0 * SCT: no */ #define HW_EMI_DRAMMODE (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0)) #define BP_EMI_DRAMMODE_CAS_LATENCY 4 #define BM_EMI_DRAMMODE_CAS_LATENCY 0x70 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0 0x0 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1 0x1 #define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2 0x2 #define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3 0x3 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4 0x4 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5 0x5 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6 0x6 #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7 0x7 #define BF_EMI_DRAMMODE_CAS_LATENCY(v) (((v) << 4) & 0x70) #define BF_EMI_DRAMMODE_CAS_LATENCY_V(v) ((BV_EMI_DRAMMODE_CAS_LATENCY__##v << 4) & 0x70) /** * Register: HW_EMI_DRAMTIME * Address: 0xc0 * SCT: yes */ #define HW_EMI_DRAMTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x0)) #define HW_EMI_DRAMTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x4)) #define HW_EMI_DRAMTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x8)) #define HW_EMI_DRAMTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0xc)) #define BP_EMI_DRAMTIME_TRFC 24 #define BM_EMI_DRAMTIME_TRFC 0xf000000 #define BF_EMI_DRAMTIME_TRFC(v) (((v) << 24) & 0xf000000) #define BP_EMI_DRAMTIME_TRC 20 #define BM_EMI_DRAMTIME_TRC 0xf00000 #define BF_EMI_DRAMTIME_TRC(v) (((v) << 20) & 0xf00000) #define BP_EMI_DRAMTIME_TRAS 16 #define BM_EMI_DRAMTIME_TRAS 0xf0000 #define BF_EMI_DRAMTIME_TRAS(v) (((v) << 16) & 0xf0000) #define BP_EMI_DRAMTIME_TRCD 12 #define BM_EMI_DRAMTIME_TRCD 0xf000 #define BF_EMI_DRAMTIME_TRCD(v) (((v) << 12) & 0xf000) #define BP_EMI_DRAMTIME_TRP 8 #define BM_EMI_DRAMTIME_TRP 0x300 #define BF_EMI_DRAMTIME_TRP(v) (((v) << 8) & 0x300) #define BP_EMI_DRAMTIME_TXSR 4 #define BM_EMI_DRAMTIME_TXSR 0xf0 #define BF_EMI_DRAMTIME_TXSR(v) (((v) << 4) & 0xf0) #define BP_EMI_DRAMTIME_REFRESH_COUNTER 0 #define BM_EMI_DRAMTIME_REFRESH_COUNTER 0xf #define BF_EMI_DRAMTIME_REFRESH_COUNTER(v) (((v) << 0) & 0xf) /** * Register: HW_EMI_DRAMTIME2 * Address: 0xd0 * SCT: yes */ #define HW_EMI_DRAMTIME2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x0)) #define HW_EMI_DRAMTIME2_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x4)) #define HW_EMI_DRAMTIME2_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x8)) #define HW_EMI_DRAMTIME2_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0xc)) #define BP_EMI_DRAMTIME2_PRECHARGE_COUNT 0 #define BM_EMI_DRAMTIME2_PRECHARGE_COUNT 0xffff #define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v) (((v) << 0) & 0xffff) /** * Register: HW_EMI_STATICCTRL * Address: 0x100 * SCT: yes */ #define HW_EMI_STATICCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x0)) #define HW_EMI_STATICCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x4)) #define HW_EMI_STATICCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x8)) #define HW_EMI_STATICCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0xc)) #define BP_EMI_STATICCTRL_MEM_WIDTH 2 #define BM_EMI_STATICCTRL_MEM_WIDTH 0x4 #define BF_EMI_STATICCTRL_MEM_WIDTH(v) (((v) << 2) & 0x4) #define BP_EMI_STATICCTRL_WRITE_PROTECT 1 #define BM_EMI_STATICCTRL_WRITE_PROTECT 0x2 #define BF_EMI_STATICCTRL_WRITE_PROTECT(v) (((v) << 1) & 0x2) #define BP_EMI_STATICCTRL_RESET_OUT 0 #define BM_EMI_STATICCTRL_RESET_OUT 0x1 #define BF_EMI_STATICCTRL_RESET_OUT(v) (((v) << 0) & 0x1) /** * Register: HW_EMI_STATICTIME * Address: 0x110 * SCT: yes */ #define HW_EMI_STATICTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x0)) #define HW_EMI_STATICTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x4)) #define HW_EMI_STATICTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x8)) #define HW_EMI_STATICTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0xc)) #define BP_EMI_STATICTIME_THZ 24 #define BM_EMI_STATICTIME_THZ 0xf000000 #define BF_EMI_STATICTIME_THZ(v) (((v) << 24) & 0xf000000) #define BP_EMI_STATICTIME_TDH 16 #define BM_EMI_STATICTIME_TDH 0xf0000 #define BF_EMI_STATICTIME_TDH(v) (((v) << 16) & 0xf0000) #define BP_EMI_STATICTIME_TDS 8 #define BM_EMI_STATICTIME_TDS 0xf00 #define BF_EMI_STATICTIME_TDS(v) (((v) << 8) & 0xf00) #define BP_EMI_STATICTIME_TAS 0 #define BM_EMI_STATICTIME_TAS 0xf #define BF_EMI_STATICTIME_TAS(v) (((v) << 0) & 0xf) #endif /* __HEADERGEN__STMP3600__EMI__H__ */