/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 2.1.8 * XML versions: stmp3600:2.3.0 * * Copyright (C) 2013 by Amaury Pouly * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN__STMP3600__TIMROT__H__ #define __HEADERGEN__STMP3600__TIMROT__H__ #define REGS_TIMROT_BASE (0x80068000) #define REGS_TIMROT_VERSION "2.3.0" /** * Register: HW_TIMROT_ROTCTRL * Address: 0 * SCT: yes */ #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) #define BP_TIMROT_ROTCTRL_SFTRST 31 #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) #define BP_TIMROT_ROTCTRL_CLKGATE 30 #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) #define BP_TIMROT_ROTCTRL_STATE 22 #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) #define BP_TIMROT_ROTCTRL_DIVIDER 16 #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) #define BP_TIMROT_ROTCTRL_RELATIVE 12 #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) #define BP_TIMROT_ROTCTRL_POLARITY_B 9 #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) #define BP_TIMROT_ROTCTRL_POLARITY_A 8 #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) #define BP_TIMROT_ROTCTRL_SELECT_B 4 #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) #define BP_TIMROT_ROTCTRL_SELECT_A 0 #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) /** * Register: HW_TIMROT_ROTCOUNT * Address: 0x10 * SCT: no */ #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) #define BP_TIMROT_ROTCOUNT_UPDOWN 0 #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) /** * Register: HW_TIMROT_TIMCTRL3 * Address: 0x80 * SCT: yes */ #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) #define BP_TIMROT_TIMCTRL3_IRQ 15 #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) #define BP_TIMROT_TIMCTRL3_POLARITY 8 #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) #define BP_TIMROT_TIMCTRL3_UPDATE 7 #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) #define BP_TIMROT_TIMCTRL3_RELOAD 6 #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) #define BP_TIMROT_TIMCTRL3_PRESCALE 4 #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) #define BP_TIMROT_TIMCTRL3_SELECT 0 #define BM_TIMROT_TIMCTRL3_SELECT 0xf #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) /** * Register: HW_TIMROT_TIMCOUNT3 * Address: 0x90 * SCT: no */ #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) /** * Register: HW_TIMROT_TIMCOUNTn * Address: 0x30+n*0x20 * SCT: no */ #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) /** * Register: HW_TIMROT_TIMCTRLn * Address: 0x20+n*0x20 * SCT: yes */ #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) #define BP_TIMROT_TIMCTRLn_IRQ 15 #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) #define BP_TIMROT_TIMCTRLn_POLARITY 8 #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) #define BP_TIMROT_TIMCTRLn_UPDATE 7 #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) #define BP_TIMROT_TIMCTRLn_RELOAD 6 #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) #define BP_TIMROT_TIMCTRLn_PRESCALE 4 #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) #define BP_TIMROT_TIMCTRLn_SELECT 0 #define BM_TIMROT_TIMCTRLn_SELECT 0xf #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) #endif /* __HEADERGEN__STMP3600__TIMROT__H__ */