/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * x1000 version: 1.0 * x1000 authors: Aidan MacDonald * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_MSC_H__ #define __HEADERGEN_MSC_H__ #include "macro.h" #define REG_MSC_CTRL(_n1) jz_reg(MSC_CTRL(_n1)) #define JA_MSC_CTRL(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x0) #define JT_MSC_CTRL(_n1) JIO_32_RW #define JN_MSC_CTRL(_n1) MSC_CTRL #define JI_MSC_CTRL(_n1) (_n1) #define BP_MSC_CTRL_CLOCK 0 #define BM_MSC_CTRL_CLOCK 0x3 #define BV_MSC_CTRL_CLOCK__DO_NOTHING 0x0 #define BV_MSC_CTRL_CLOCK__STOP 0x1 #define BV_MSC_CTRL_CLOCK__START 0x2 #define BF_MSC_CTRL_CLOCK(v) (((v) & 0x3) << 0) #define BFM_MSC_CTRL_CLOCK(v) BM_MSC_CTRL_CLOCK #define BF_MSC_CTRL_CLOCK_V(e) BF_MSC_CTRL_CLOCK(BV_MSC_CTRL_CLOCK__##e) #define BFM_MSC_CTRL_CLOCK_V(v) BM_MSC_CTRL_CLOCK #define BP_MSC_CTRL_SEND_CCSD 15 #define BM_MSC_CTRL_SEND_CCSD 0x8000 #define BF_MSC_CTRL_SEND_CCSD(v) (((v) & 0x1) << 15) #define BFM_MSC_CTRL_SEND_CCSD(v) BM_MSC_CTRL_SEND_CCSD #define BF_MSC_CTRL_SEND_CCSD_V(e) BF_MSC_CTRL_SEND_CCSD(BV_MSC_CTRL_SEND_CCSD__##e) #define BFM_MSC_CTRL_SEND_CCSD_V(v) BM_MSC_CTRL_SEND_CCSD #define BP_MSC_CTRL_SEND_AS_CCSD 14 #define BM_MSC_CTRL_SEND_AS_CCSD 0x4000 #define BF_MSC_CTRL_SEND_AS_CCSD(v) (((v) & 0x1) << 14) #define BFM_MSC_CTRL_SEND_AS_CCSD(v) BM_MSC_CTRL_SEND_AS_CCSD #define BF_MSC_CTRL_SEND_AS_CCSD_V(e) BF_MSC_CTRL_SEND_AS_CCSD(BV_MSC_CTRL_SEND_AS_CCSD__##e) #define BFM_MSC_CTRL_SEND_AS_CCSD_V(v) BM_MSC_CTRL_SEND_AS_CCSD #define BP_MSC_CTRL_EXIT_MULTIPLE 7 #define BM_MSC_CTRL_EXIT_MULTIPLE 0x80 #define BF_MSC_CTRL_EXIT_MULTIPLE(v) (((v) & 0x1) << 7) #define BFM_MSC_CTRL_EXIT_MULTIPLE(v) BM_MSC_CTRL_EXIT_MULTIPLE #define BF_MSC_CTRL_EXIT_MULTIPLE_V(e) BF_MSC_CTRL_EXIT_MULTIPLE(BV_MSC_CTRL_EXIT_MULTIPLE__##e) #define BFM_MSC_CTRL_EXIT_MULTIPLE_V(v) BM_MSC_CTRL_EXIT_MULTIPLE #define BP_MSC_CTRL_EXIT_TRANSFER 6 #define BM_MSC_CTRL_EXIT_TRANSFER 0x40 #define BF_MSC_CTRL_EXIT_TRANSFER(v) (((v) & 0x1) << 6) #define BFM_MSC_CTRL_EXIT_TRANSFER(v) BM_MSC_CTRL_EXIT_TRANSFER #define BF_MSC_CTRL_EXIT_TRANSFER_V(e) BF_MSC_CTRL_EXIT_TRANSFER(BV_MSC_CTRL_EXIT_TRANSFER__##e) #define BFM_MSC_CTRL_EXIT_TRANSFER_V(v) BM_MSC_CTRL_EXIT_TRANSFER #define BP_MSC_CTRL_START_READ_WAIT 5 #define BM_MSC_CTRL_START_READ_WAIT 0x20 #define BF_MSC_CTRL_START_READ_WAIT(v) (((v) & 0x1) << 5) #define BFM_MSC_CTRL_START_READ_WAIT(v) BM_MSC_CTRL_START_READ_WAIT #define BF_MSC_CTRL_START_READ_WAIT_V(e) BF_MSC_CTRL_START_READ_WAIT(BV_MSC_CTRL_START_READ_WAIT__##e) #define BFM_MSC_CTRL_START_READ_WAIT_V(v) BM_MSC_CTRL_START_READ_WAIT #define BP_MSC_CTRL_STOP_READ_WAIT 4 #define BM_MSC_CTRL_STOP_READ_WAIT 0x10 #define BF_MSC_CTRL_STOP_READ_WAIT(v) (((v) & 0x1) << 4) #define BFM_MSC_CTRL_STOP_READ_WAIT(v) BM_MSC_CTRL_STOP_READ_WAIT #define BF_MSC_CTRL_STOP_READ_WAIT_V(e) BF_MSC_CTRL_STOP_READ_WAIT(BV_MSC_CTRL_STOP_READ_WAIT__##e) #define BFM_MSC_CTRL_STOP_READ_WAIT_V(v) BM_MSC_CTRL_STOP_READ_WAIT #define BP_MSC_CTRL_RESET 3 #define BM_MSC_CTRL_RESET 0x8 #define BF_MSC_CTRL_RESET(v) (((v) & 0x1) << 3) #define BFM_MSC_CTRL_RESET(v) BM_MSC_CTRL_RESET #define BF_MSC_CTRL_RESET_V(e) BF_MSC_CTRL_RESET(BV_MSC_CTRL_RESET__##e) #define BFM_MSC_CTRL_RESET_V(v) BM_MSC_CTRL_RESET #define BP_MSC_CTRL_START_OP 2 #define BM_MSC_CTRL_START_OP 0x4 #define BF_MSC_CTRL_START_OP(v) (((v) & 0x1) << 2) #define BFM_MSC_CTRL_START_OP(v) BM_MSC_CTRL_START_OP #define BF_MSC_CTRL_START_OP_V(e) BF_MSC_CTRL_START_OP(BV_MSC_CTRL_START_OP__##e) #define BFM_MSC_CTRL_START_OP_V(v) BM_MSC_CTRL_START_OP #define REG_MSC_STAT(_n1) jz_reg(MSC_STAT(_n1)) #define JA_MSC_STAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4) #define JT_MSC_STAT(_n1) JIO_32_RW #define JN_MSC_STAT(_n1) MSC_STAT #define JI_MSC_STAT(_n1) (_n1) #define BP_MSC_STAT_PINS 24 #define BM_MSC_STAT_PINS 0x1f000000 #define BF_MSC_STAT_PINS(v) (((v) & 0x1f) << 24) #define BFM_MSC_STAT_PINS(v) BM_MSC_STAT_PINS #define BF_MSC_STAT_PINS_V(e) BF_MSC_STAT_PINS(BV_MSC_STAT_PINS__##e) #define BFM_MSC_STAT_PINS_V(v) BM_MSC_STAT_PINS #define BP_MSC_STAT_CRC_WRITE_ERROR 2 #define BM_MSC_STAT_CRC_WRITE_ERROR 0xc #define BV_MSC_STAT_CRC_WRITE_ERROR__NONE 0x0 #define BV_MSC_STAT_CRC_WRITE_ERROR__BADDATA 0x1 #define BV_MSC_STAT_CRC_WRITE_ERROR__NOCRC 0x2 #define BF_MSC_STAT_CRC_WRITE_ERROR(v) (((v) & 0x3) << 2) #define BFM_MSC_STAT_CRC_WRITE_ERROR(v) BM_MSC_STAT_CRC_WRITE_ERROR #define BF_MSC_STAT_CRC_WRITE_ERROR_V(e) BF_MSC_STAT_CRC_WRITE_ERROR(BV_MSC_STAT_CRC_WRITE_ERROR__##e) #define BFM_MSC_STAT_CRC_WRITE_ERROR_V(v) BM_MSC_STAT_CRC_WRITE_ERROR #define BP_MSC_STAT_AUTO_CMD12_DONE 31 #define BM_MSC_STAT_AUTO_CMD12_DONE 0x80000000 #define BF_MSC_STAT_AUTO_CMD12_DONE(v) (((v) & 0x1) << 31) #define BFM_MSC_STAT_AUTO_CMD12_DONE(v) BM_MSC_STAT_AUTO_CMD12_DONE #define BF_MSC_STAT_AUTO_CMD12_DONE_V(e) BF_MSC_STAT_AUTO_CMD12_DONE(BV_MSC_STAT_AUTO_CMD12_DONE__##e) #define BFM_MSC_STAT_AUTO_CMD12_DONE_V(v) BM_MSC_STAT_AUTO_CMD12_DONE #define BP_MSC_STAT_BCE 20 #define BM_MSC_STAT_BCE 0x100000 #define BF_MSC_STAT_BCE(v) (((v) & 0x1) << 20) #define BFM_MSC_STAT_BCE(v) BM_MSC_STAT_BCE #define BF_MSC_STAT_BCE_V(e) BF_MSC_STAT_BCE(BV_MSC_STAT_BCE__##e) #define BFM_MSC_STAT_BCE_V(v) BM_MSC_STAT_BCE #define BP_MSC_STAT_BDE 19 #define BM_MSC_STAT_BDE 0x80000 #define BF_MSC_STAT_BDE(v) (((v) & 0x1) << 19) #define BFM_MSC_STAT_BDE(v) BM_MSC_STAT_BDE #define BF_MSC_STAT_BDE_V(e) BF_MSC_STAT_BDE(BV_MSC_STAT_BDE__##e) #define BFM_MSC_STAT_BDE_V(v) BM_MSC_STAT_BDE #define BP_MSC_STAT_BAE 18 #define BM_MSC_STAT_BAE 0x40000 #define BF_MSC_STAT_BAE(v) (((v) & 0x1) << 18) #define BFM_MSC_STAT_BAE(v) BM_MSC_STAT_BAE #define BF_MSC_STAT_BAE_V(e) BF_MSC_STAT_BAE(BV_MSC_STAT_BAE__##e) #define BFM_MSC_STAT_BAE_V(v) BM_MSC_STAT_BAE #define BP_MSC_STAT_BAR 17 #define BM_MSC_STAT_BAR 0x20000 #define BF_MSC_STAT_BAR(v) (((v) & 0x1) << 17) #define BFM_MSC_STAT_BAR(v) BM_MSC_STAT_BAR #define BF_MSC_STAT_BAR_V(e) BF_MSC_STAT_BAR(BV_MSC_STAT_BAR__##e) #define BFM_MSC_STAT_BAR_V(v) BM_MSC_STAT_BAR #define BP_MSC_STAT_DMAEND 16 #define BM_MSC_STAT_DMAEND 0x10000 #define BF_MSC_STAT_DMAEND(v) (((v) & 0x1) << 16) #define BFM_MSC_STAT_DMAEND(v) BM_MSC_STAT_DMAEND #define BF_MSC_STAT_DMAEND_V(e) BF_MSC_STAT_DMAEND(BV_MSC_STAT_DMAEND__##e) #define BFM_MSC_STAT_DMAEND_V(v) BM_MSC_STAT_DMAEND #define BP_MSC_STAT_IS_RESETTING 15 #define BM_MSC_STAT_IS_RESETTING 0x8000 #define BF_MSC_STAT_IS_RESETTING(v) (((v) & 0x1) << 15) #define BFM_MSC_STAT_IS_RESETTING(v) BM_MSC_STAT_IS_RESETTING #define BF_MSC_STAT_IS_RESETTING_V(e) BF_MSC_STAT_IS_RESETTING(BV_MSC_STAT_IS_RESETTING__##e) #define BFM_MSC_STAT_IS_RESETTING_V(v) BM_MSC_STAT_IS_RESETTING #define BP_MSC_STAT_SDIO_INT_ACTIVE 14 #define BM_MSC_STAT_SDIO_INT_ACTIVE 0x4000 #define BF_MSC_STAT_SDIO_INT_ACTIVE(v) (((v) & 0x1) << 14) #define BFM_MSC_STAT_SDIO_INT_ACTIVE(v) BM_MSC_STAT_SDIO_INT_ACTIVE #define BF_MSC_STAT_SDIO_INT_ACTIVE_V(e) BF_MSC_STAT_SDIO_INT_ACTIVE(BV_MSC_STAT_SDIO_INT_ACTIVE__##e) #define BFM_MSC_STAT_SDIO_INT_ACTIVE_V(v) BM_MSC_STAT_SDIO_INT_ACTIVE #define BP_MSC_STAT_PROG_DONE 13 #define BM_MSC_STAT_PROG_DONE 0x2000 #define BF_MSC_STAT_PROG_DONE(v) (((v) & 0x1) << 13) #define BFM_MSC_STAT_PROG_DONE(v) BM_MSC_STAT_PROG_DONE #define BF_MSC_STAT_PROG_DONE_V(e) BF_MSC_STAT_PROG_DONE(BV_MSC_STAT_PROG_DONE__##e) #define BFM_MSC_STAT_PROG_DONE_V(v) BM_MSC_STAT_PROG_DONE #define BP_MSC_STAT_DATA_TRAN_DONE 12 #define BM_MSC_STAT_DATA_TRAN_DONE 0x1000 #define BF_MSC_STAT_DATA_TRAN_DONE(v) (((v) & 0x1) << 12) #define BFM_MSC_STAT_DATA_TRAN_DONE(v) BM_MSC_STAT_DATA_TRAN_DONE #define BF_MSC_STAT_DATA_TRAN_DONE_V(e) BF_MSC_STAT_DATA_TRAN_DONE(BV_MSC_STAT_DATA_TRAN_DONE__##e) #define BFM_MSC_STAT_DATA_TRAN_DONE_V(v) BM_MSC_STAT_DATA_TRAN_DONE #define BP_MSC_STAT_END_CMD_RES 11 #define BM_MSC_STAT_END_CMD_RES 0x800 #define BF_MSC_STAT_END_CMD_RES(v) (((v) & 0x1) << 11) #define BFM_MSC_STAT_END_CMD_RES(v) BM_MSC_STAT_END_CMD_RES #define BF_MSC_STAT_END_CMD_RES_V(e) BF_MSC_STAT_END_CMD_RES(BV_MSC_STAT_END_CMD_RES__##e) #define BFM_MSC_STAT_END_CMD_RES_V(v) BM_MSC_STAT_END_CMD_RES #define BP_MSC_STAT_DATA_FIFO_AFULL 10 #define BM_MSC_STAT_DATA_FIFO_AFULL 0x400 #define BF_MSC_STAT_DATA_FIFO_AFULL(v) (((v) & 0x1) << 10) #define BFM_MSC_STAT_DATA_FIFO_AFULL(v) BM_MSC_STAT_DATA_FIFO_AFULL #define BF_MSC_STAT_DATA_FIFO_AFULL_V(e) BF_MSC_STAT_DATA_FIFO_AFULL(BV_MSC_STAT_DATA_FIFO_AFULL__##e) #define BFM_MSC_STAT_DATA_FIFO_AFULL_V(v) BM_MSC_STAT_DATA_FIFO_AFULL #define BP_MSC_STAT_IS_READ_WAIT 9 #define BM_MSC_STAT_IS_READ_WAIT 0x200 #define BF_MSC_STAT_IS_READ_WAIT(v) (((v) & 0x1) << 9) #define BFM_MSC_STAT_IS_READ_WAIT(v) BM_MSC_STAT_IS_READ_WAIT #define BF_MSC_STAT_IS_READ_WAIT_V(e) BF_MSC_STAT_IS_READ_WAIT(BV_MSC_STAT_IS_READ_WAIT__##e) #define BFM_MSC_STAT_IS_READ_WAIT_V(v) BM_MSC_STAT_IS_READ_WAIT #define BP_MSC_STAT_CLOCK_EN 8 #define BM_MSC_STAT_CLOCK_EN 0x100 #define BF_MSC_STAT_CLOCK_EN(v) (((v) & 0x1) << 8) #define BFM_MSC_STAT_CLOCK_EN(v) BM_MSC_STAT_CLOCK_EN #define BF_MSC_STAT_CLOCK_EN_V(e) BF_MSC_STAT_CLOCK_EN(BV_MSC_STAT_CLOCK_EN__##e) #define BFM_MSC_STAT_CLOCK_EN_V(v) BM_MSC_STAT_CLOCK_EN #define BP_MSC_STAT_DATA_FIFO_FULL 7 #define BM_MSC_STAT_DATA_FIFO_FULL 0x80 #define BF_MSC_STAT_DATA_FIFO_FULL(v) (((v) & 0x1) << 7) #define BFM_MSC_STAT_DATA_FIFO_FULL(v) BM_MSC_STAT_DATA_FIFO_FULL #define BF_MSC_STAT_DATA_FIFO_FULL_V(e) BF_MSC_STAT_DATA_FIFO_FULL(BV_MSC_STAT_DATA_FIFO_FULL__##e) #define BFM_MSC_STAT_DATA_FIFO_FULL_V(v) BM_MSC_STAT_DATA_FIFO_FULL #define BP_MSC_STAT_DATA_FIFO_EMPTY 6 #define BM_MSC_STAT_DATA_FIFO_EMPTY 0x40 #define BF_MSC_STAT_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 6) #define BFM_MSC_STAT_DATA_FIFO_EMPTY(v) BM_MSC_STAT_DATA_FIFO_EMPTY #define BF_MSC_STAT_DATA_FIFO_EMPTY_V(e) BF_MSC_STAT_DATA_FIFO_EMPTY(BV_MSC_STAT_DATA_FIFO_EMPTY__##e) #define BFM_MSC_STAT_DATA_FIFO_EMPTY_V(v) BM_MSC_STAT_DATA_FIFO_EMPTY #define BP_MSC_STAT_CRC_RES_ERROR 5 #define BM_MSC_STAT_CRC_RES_ERROR 0x20 #define BF_MSC_STAT_CRC_RES_ERROR(v) (((v) & 0x1) << 5) #define BFM_MSC_STAT_CRC_RES_ERROR(v) BM_MSC_STAT_CRC_RES_ERROR #define BF_MSC_STAT_CRC_RES_ERROR_V(e) BF_MSC_STAT_CRC_RES_ERROR(BV_MSC_STAT_CRC_RES_ERROR__##e) #define BFM_MSC_STAT_CRC_RES_ERROR_V(v) BM_MSC_STAT_CRC_RES_ERROR #define BP_MSC_STAT_CRC_READ_ERROR 4 #define BM_MSC_STAT_CRC_READ_ERROR 0x10 #define BF_MSC_STAT_CRC_READ_ERROR(v) (((v) & 0x1) << 4) #define BFM_MSC_STAT_CRC_READ_ERROR(v) BM_MSC_STAT_CRC_READ_ERROR #define BF_MSC_STAT_CRC_READ_ERROR_V(e) BF_MSC_STAT_CRC_READ_ERROR(BV_MSC_STAT_CRC_READ_ERROR__##e) #define BFM_MSC_STAT_CRC_READ_ERROR_V(v) BM_MSC_STAT_CRC_READ_ERROR #define BP_MSC_STAT_TIME_OUT_RES 1 #define BM_MSC_STAT_TIME_OUT_RES 0x2 #define BF_MSC_STAT_TIME_OUT_RES(v) (((v) & 0x1) << 1) #define BFM_MSC_STAT_TIME_OUT_RES(v) BM_MSC_STAT_TIME_OUT_RES #define BF_MSC_STAT_TIME_OUT_RES_V(e) BF_MSC_STAT_TIME_OUT_RES(BV_MSC_STAT_TIME_OUT_RES__##e) #define BFM_MSC_STAT_TIME_OUT_RES_V(v) BM_MSC_STAT_TIME_OUT_RES #define BP_MSC_STAT_TIME_OUT_READ 0 #define BM_MSC_STAT_TIME_OUT_READ 0x1 #define BF_MSC_STAT_TIME_OUT_READ(v) (((v) & 0x1) << 0) #define BFM_MSC_STAT_TIME_OUT_READ(v) BM_MSC_STAT_TIME_OUT_READ #define BF_MSC_STAT_TIME_OUT_READ_V(e) BF_MSC_STAT_TIME_OUT_READ(BV_MSC_STAT_TIME_OUT_READ__##e) #define BFM_MSC_STAT_TIME_OUT_READ_V(v) BM_MSC_STAT_TIME_OUT_READ #define REG_MSC_CMDAT(_n1) jz_reg(MSC_CMDAT(_n1)) #define JA_MSC_CMDAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0xc) #define JT_MSC_CMDAT(_n1) JIO_32_RW #define JN_MSC_CMDAT(_n1) MSC_CMDAT #define JI_MSC_CMDAT(_n1) (_n1) #define BP_MSC_CMDAT_RTRG 14 #define BM_MSC_CMDAT_RTRG 0xc000 #define BV_MSC_CMDAT_RTRG__GE16 0x0 #define BV_MSC_CMDAT_RTRG__GE32 0x1 #define BV_MSC_CMDAT_RTRG__GE64 0x2 #define BV_MSC_CMDAT_RTRG__GE96 0x3 #define BF_MSC_CMDAT_RTRG(v) (((v) & 0x3) << 14) #define BFM_MSC_CMDAT_RTRG(v) BM_MSC_CMDAT_RTRG #define BF_MSC_CMDAT_RTRG_V(e) BF_MSC_CMDAT_RTRG(BV_MSC_CMDAT_RTRG__##e) #define BFM_MSC_CMDAT_RTRG_V(v) BM_MSC_CMDAT_RTRG #define BP_MSC_CMDAT_TTRG 12 #define BM_MSC_CMDAT_TTRG 0x3000 #define BV_MSC_CMDAT_TTRG__LE16 0x0 #define BV_MSC_CMDAT_TTRG__LE32 0x1 #define BV_MSC_CMDAT_TTRG__LE64 0x2 #define BV_MSC_CMDAT_TTRG__LE96 0x3 #define BF_MSC_CMDAT_TTRG(v) (((v) & 0x3) << 12) #define BFM_MSC_CMDAT_TTRG(v) BM_MSC_CMDAT_TTRG #define BF_MSC_CMDAT_TTRG_V(e) BF_MSC_CMDAT_TTRG(BV_MSC_CMDAT_TTRG__##e) #define BFM_MSC_CMDAT_TTRG_V(v) BM_MSC_CMDAT_TTRG #define BP_MSC_CMDAT_BUS_WIDTH 9 #define BM_MSC_CMDAT_BUS_WIDTH 0x600 #define BV_MSC_CMDAT_BUS_WIDTH__1BIT 0x0 #define BV_MSC_CMDAT_BUS_WIDTH__4BIT 0x2 #define BV_MSC_CMDAT_BUS_WIDTH__8BIT 0x3 #define BF_MSC_CMDAT_BUS_WIDTH(v) (((v) & 0x3) << 9) #define BFM_MSC_CMDAT_BUS_WIDTH(v) BM_MSC_CMDAT_BUS_WIDTH #define BF_MSC_CMDAT_BUS_WIDTH_V(e) BF_MSC_CMDAT_BUS_WIDTH(BV_MSC_CMDAT_BUS_WIDTH__##e) #define BFM_MSC_CMDAT_BUS_WIDTH_V(v) BM_MSC_CMDAT_BUS_WIDTH #define BP_MSC_CMDAT_RESP_FMT 0 #define BM_MSC_CMDAT_RESP_FMT 0x7 #define BF_MSC_CMDAT_RESP_FMT(v) (((v) & 0x7) << 0) #define BFM_MSC_CMDAT_RESP_FMT(v) BM_MSC_CMDAT_RESP_FMT #define BF_MSC_CMDAT_RESP_FMT_V(e) BF_MSC_CMDAT_RESP_FMT(BV_MSC_CMDAT_RESP_FMT__##e) #define BFM_MSC_CMDAT_RESP_FMT_V(v) BM_MSC_CMDAT_RESP_FMT #define BP_MSC_CMDAT_CCS_EXPECTED 31 #define BM_MSC_CMDAT_CCS_EXPECTED 0x80000000 #define BF_MSC_CMDAT_CCS_EXPECTED(v) (((v) & 0x1) << 31) #define BFM_MSC_CMDAT_CCS_EXPECTED(v) BM_MSC_CMDAT_CCS_EXPECTED #define BF_MSC_CMDAT_CCS_EXPECTED_V(e) BF_MSC_CMDAT_CCS_EXPECTED(BV_MSC_CMDAT_CCS_EXPECTED__##e) #define BFM_MSC_CMDAT_CCS_EXPECTED_V(v) BM_MSC_CMDAT_CCS_EXPECTED #define BP_MSC_CMDAT_READ_CEATA 30 #define BM_MSC_CMDAT_READ_CEATA 0x40000000 #define BF_MSC_CMDAT_READ_CEATA(v) (((v) & 0x1) << 30) #define BFM_MSC_CMDAT_READ_CEATA(v) BM_MSC_CMDAT_READ_CEATA #define BF_MSC_CMDAT_READ_CEATA_V(e) BF_MSC_CMDAT_READ_CEATA(BV_MSC_CMDAT_READ_CEATA__##e) #define BFM_MSC_CMDAT_READ_CEATA_V(v) BM_MSC_CMDAT_READ_CEATA #define BP_MSC_CMDAT_DIS_BOOT 27 #define BM_MSC_CMDAT_DIS_BOOT 0x8000000 #define BF_MSC_CMDAT_DIS_BOOT(v) (((v) & 0x1) << 27) #define BFM_MSC_CMDAT_DIS_BOOT(v) BM_MSC_CMDAT_DIS_BOOT #define BF_MSC_CMDAT_DIS_BOOT_V(e) BF_MSC_CMDAT_DIS_BOOT(BV_MSC_CMDAT_DIS_BOOT__##e) #define BFM_MSC_CMDAT_DIS_BOOT_V(v) BM_MSC_CMDAT_DIS_BOOT #define BP_MSC_CMDAT_EXP_BOOT_ACK 25 #define BM_MSC_CMDAT_EXP_BOOT_ACK 0x2000000 #define BF_MSC_CMDAT_EXP_BOOT_ACK(v) (((v) & 0x1) << 25) #define BFM_MSC_CMDAT_EXP_BOOT_ACK(v) BM_MSC_CMDAT_EXP_BOOT_ACK #define BF_MSC_CMDAT_EXP_BOOT_ACK_V(e) BF_MSC_CMDAT_EXP_BOOT_ACK(BV_MSC_CMDAT_EXP_BOOT_ACK__##e) #define BFM_MSC_CMDAT_EXP_BOOT_ACK_V(v) BM_MSC_CMDAT_EXP_BOOT_ACK #define BP_MSC_CMDAT_BOOT_MODE 24 #define BM_MSC_CMDAT_BOOT_MODE 0x1000000 #define BF_MSC_CMDAT_BOOT_MODE(v) (((v) & 0x1) << 24) #define BFM_MSC_CMDAT_BOOT_MODE(v) BM_MSC_CMDAT_BOOT_MODE #define BF_MSC_CMDAT_BOOT_MODE_V(e) BF_MSC_CMDAT_BOOT_MODE(BV_MSC_CMDAT_BOOT_MODE__##e) #define BFM_MSC_CMDAT_BOOT_MODE_V(v) BM_MSC_CMDAT_BOOT_MODE #define BP_MSC_CMDAT_SDIO_PRDT 17 #define BM_MSC_CMDAT_SDIO_PRDT 0x20000 #define BF_MSC_CMDAT_SDIO_PRDT(v) (((v) & 0x1) << 17) #define BFM_MSC_CMDAT_SDIO_PRDT(v) BM_MSC_CMDAT_SDIO_PRDT #define BF_MSC_CMDAT_SDIO_PRDT_V(e) BF_MSC_CMDAT_SDIO_PRDT(BV_MSC_CMDAT_SDIO_PRDT__##e) #define BFM_MSC_CMDAT_SDIO_PRDT_V(v) BM_MSC_CMDAT_SDIO_PRDT #define BP_MSC_CMDAT_AUTO_CMD12 16 #define BM_MSC_CMDAT_AUTO_CMD12 0x10000 #define BF_MSC_CMDAT_AUTO_CMD12(v) (((v) & 0x1) << 16) #define BFM_MSC_CMDAT_AUTO_CMD12(v) BM_MSC_CMDAT_AUTO_CMD12 #define BF_MSC_CMDAT_AUTO_CMD12_V(e) BF_MSC_CMDAT_AUTO_CMD12(BV_MSC_CMDAT_AUTO_CMD12__##e) #define BFM_MSC_CMDAT_AUTO_CMD12_V(v) BM_MSC_CMDAT_AUTO_CMD12 #define BP_MSC_CMDAT_IO_ABORT 11 #define BM_MSC_CMDAT_IO_ABORT 0x800 #define BF_MSC_CMDAT_IO_ABORT(v) (((v) & 0x1) << 11) #define BFM_MSC_CMDAT_IO_ABORT(v) BM_MSC_CMDAT_IO_ABORT #define BF_MSC_CMDAT_IO_ABORT_V(e) BF_MSC_CMDAT_IO_ABORT(BV_MSC_CMDAT_IO_ABORT__##e) #define BFM_MSC_CMDAT_IO_ABORT_V(v) BM_MSC_CMDAT_IO_ABORT #define BP_MSC_CMDAT_INIT 7 #define BM_MSC_CMDAT_INIT 0x80 #define BF_MSC_CMDAT_INIT(v) (((v) & 0x1) << 7) #define BFM_MSC_CMDAT_INIT(v) BM_MSC_CMDAT_INIT #define BF_MSC_CMDAT_INIT_V(e) BF_MSC_CMDAT_INIT(BV_MSC_CMDAT_INIT__##e) #define BFM_MSC_CMDAT_INIT_V(v) BM_MSC_CMDAT_INIT #define BP_MSC_CMDAT_BUSY 6 #define BM_MSC_CMDAT_BUSY 0x40 #define BF_MSC_CMDAT_BUSY(v) (((v) & 0x1) << 6) #define BFM_MSC_CMDAT_BUSY(v) BM_MSC_CMDAT_BUSY #define BF_MSC_CMDAT_BUSY_V(e) BF_MSC_CMDAT_BUSY(BV_MSC_CMDAT_BUSY__##e) #define BFM_MSC_CMDAT_BUSY_V(v) BM_MSC_CMDAT_BUSY #define BP_MSC_CMDAT_STREAM_BLOCK 5 #define BM_MSC_CMDAT_STREAM_BLOCK 0x20 #define BF_MSC_CMDAT_STREAM_BLOCK(v) (((v) & 0x1) << 5) #define BFM_MSC_CMDAT_STREAM_BLOCK(v) BM_MSC_CMDAT_STREAM_BLOCK #define BF_MSC_CMDAT_STREAM_BLOCK_V(e) BF_MSC_CMDAT_STREAM_BLOCK(BV_MSC_CMDAT_STREAM_BLOCK__##e) #define BFM_MSC_CMDAT_STREAM_BLOCK_V(v) BM_MSC_CMDAT_STREAM_BLOCK #define BP_MSC_CMDAT_WRITE_READ 4 #define BM_MSC_CMDAT_WRITE_READ 0x10 #define BF_MSC_CMDAT_WRITE_READ(v) (((v) & 0x1) << 4) #define BFM_MSC_CMDAT_WRITE_READ(v) BM_MSC_CMDAT_WRITE_READ #define BF_MSC_CMDAT_WRITE_READ_V(e) BF_MSC_CMDAT_WRITE_READ(BV_MSC_CMDAT_WRITE_READ__##e) #define BFM_MSC_CMDAT_WRITE_READ_V(v) BM_MSC_CMDAT_WRITE_READ #define BP_MSC_CMDAT_DATA_EN 3 #define BM_MSC_CMDAT_DATA_EN 0x8 #define BF_MSC_CMDAT_DATA_EN(v) (((v) & 0x1) << 3) #define BFM_MSC_CMDAT_DATA_EN(v) BM_MSC_CMDAT_DATA_EN #define BF_MSC_CMDAT_DATA_EN_V(e) BF_MSC_CMDAT_DATA_EN(BV_MSC_CMDAT_DATA_EN__##e) #define BFM_MSC_CMDAT_DATA_EN_V(v) BM_MSC_CMDAT_DATA_EN #define REG_MSC_IMASK(_n1) jz_reg(MSC_IMASK(_n1)) #define JA_MSC_IMASK(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x24) #define JT_MSC_IMASK(_n1) JIO_32_RW #define JN_MSC_IMASK(_n1) MSC_IMASK #define JI_MSC_IMASK(_n1) (_n1) #define BP_MSC_IMASK_PINS 24 #define BM_MSC_IMASK_PINS 0x1f000000 #define BF_MSC_IMASK_PINS(v) (((v) & 0x1f) << 24) #define BFM_MSC_IMASK_PINS(v) BM_MSC_IMASK_PINS #define BF_MSC_IMASK_PINS_V(e) BF_MSC_IMASK_PINS(BV_MSC_IMASK_PINS__##e) #define BFM_MSC_IMASK_PINS_V(v) BM_MSC_IMASK_PINS #define BP_MSC_IMASK_DMA_DATA_DONE 31 #define BM_MSC_IMASK_DMA_DATA_DONE 0x80000000 #define BF_MSC_IMASK_DMA_DATA_DONE(v) (((v) & 0x1) << 31) #define BFM_MSC_IMASK_DMA_DATA_DONE(v) BM_MSC_IMASK_DMA_DATA_DONE #define BF_MSC_IMASK_DMA_DATA_DONE_V(e) BF_MSC_IMASK_DMA_DATA_DONE(BV_MSC_IMASK_DMA_DATA_DONE__##e) #define BFM_MSC_IMASK_DMA_DATA_DONE_V(v) BM_MSC_IMASK_DMA_DATA_DONE #define BP_MSC_IMASK_WR_ALL_DONE 23 #define BM_MSC_IMASK_WR_ALL_DONE 0x800000 #define BF_MSC_IMASK_WR_ALL_DONE(v) (((v) & 0x1) << 23) #define BFM_MSC_IMASK_WR_ALL_DONE(v) BM_MSC_IMASK_WR_ALL_DONE #define BF_MSC_IMASK_WR_ALL_DONE_V(e) BF_MSC_IMASK_WR_ALL_DONE(BV_MSC_IMASK_WR_ALL_DONE__##e) #define BFM_MSC_IMASK_WR_ALL_DONE_V(v) BM_MSC_IMASK_WR_ALL_DONE #define BP_MSC_IMASK_BCE 20 #define BM_MSC_IMASK_BCE 0x100000 #define BF_MSC_IMASK_BCE(v) (((v) & 0x1) << 20) #define BFM_MSC_IMASK_BCE(v) BM_MSC_IMASK_BCE #define BF_MSC_IMASK_BCE_V(e) BF_MSC_IMASK_BCE(BV_MSC_IMASK_BCE__##e) #define BFM_MSC_IMASK_BCE_V(v) BM_MSC_IMASK_BCE #define BP_MSC_IMASK_BDE 19 #define BM_MSC_IMASK_BDE 0x80000 #define BF_MSC_IMASK_BDE(v) (((v) & 0x1) << 19) #define BFM_MSC_IMASK_BDE(v) BM_MSC_IMASK_BDE #define BF_MSC_IMASK_BDE_V(e) BF_MSC_IMASK_BDE(BV_MSC_IMASK_BDE__##e) #define BFM_MSC_IMASK_BDE_V(v) BM_MSC_IMASK_BDE #define BP_MSC_IMASK_BAE 18 #define BM_MSC_IMASK_BAE 0x40000 #define BF_MSC_IMASK_BAE(v) (((v) & 0x1) << 18) #define BFM_MSC_IMASK_BAE(v) BM_MSC_IMASK_BAE #define BF_MSC_IMASK_BAE_V(e) BF_MSC_IMASK_BAE(BV_MSC_IMASK_BAE__##e) #define BFM_MSC_IMASK_BAE_V(v) BM_MSC_IMASK_BAE #define BP_MSC_IMASK_BAR 17 #define BM_MSC_IMASK_BAR 0x20000 #define BF_MSC_IMASK_BAR(v) (((v) & 0x1) << 17) #define BFM_MSC_IMASK_BAR(v) BM_MSC_IMASK_BAR #define BF_MSC_IMASK_BAR_V(e) BF_MSC_IMASK_BAR(BV_MSC_IMASK_BAR__##e) #define BFM_MSC_IMASK_BAR_V(v) BM_MSC_IMASK_BAR #define BP_MSC_IMASK_DMAEND 16 #define BM_MSC_IMASK_DMAEND 0x10000 #define BF_MSC_IMASK_DMAEND(v) (((v) & 0x1) << 16) #define BFM_MSC_IMASK_DMAEND(v) BM_MSC_IMASK_DMAEND #define BF_MSC_IMASK_DMAEND_V(e) BF_MSC_IMASK_DMAEND(BV_MSC_IMASK_DMAEND__##e) #define BFM_MSC_IMASK_DMAEND_V(v) BM_MSC_IMASK_DMAEND #define BP_MSC_IMASK_AUTO_CMD12_DONE 15 #define BM_MSC_IMASK_AUTO_CMD12_DONE 0x8000 #define BF_MSC_IMASK_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) #define BFM_MSC_IMASK_AUTO_CMD12_DONE(v) BM_MSC_IMASK_AUTO_CMD12_DONE #define BF_MSC_IMASK_AUTO_CMD12_DONE_V(e) BF_MSC_IMASK_AUTO_CMD12_DONE(BV_MSC_IMASK_AUTO_CMD12_DONE__##e) #define BFM_MSC_IMASK_AUTO_CMD12_DONE_V(v) BM_MSC_IMASK_AUTO_CMD12_DONE #define BP_MSC_IMASK_DATA_FIFO_FULL 14 #define BM_MSC_IMASK_DATA_FIFO_FULL 0x4000 #define BF_MSC_IMASK_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) #define BFM_MSC_IMASK_DATA_FIFO_FULL(v) BM_MSC_IMASK_DATA_FIFO_FULL #define BF_MSC_IMASK_DATA_FIFO_FULL_V(e) BF_MSC_IMASK_DATA_FIFO_FULL(BV_MSC_IMASK_DATA_FIFO_FULL__##e) #define BFM_MSC_IMASK_DATA_FIFO_FULL_V(v) BM_MSC_IMASK_DATA_FIFO_FULL #define BP_MSC_IMASK_DATA_FIFO_EMPTY 13 #define BM_MSC_IMASK_DATA_FIFO_EMPTY 0x2000 #define BF_MSC_IMASK_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) #define BFM_MSC_IMASK_DATA_FIFO_EMPTY(v) BM_MSC_IMASK_DATA_FIFO_EMPTY #define BF_MSC_IMASK_DATA_FIFO_EMPTY_V(e) BF_MSC_IMASK_DATA_FIFO_EMPTY(BV_MSC_IMASK_DATA_FIFO_EMPTY__##e) #define BFM_MSC_IMASK_DATA_FIFO_EMPTY_V(v) BM_MSC_IMASK_DATA_FIFO_EMPTY #define BP_MSC_IMASK_CRC_RES_ERROR 12 #define BM_MSC_IMASK_CRC_RES_ERROR 0x1000 #define BF_MSC_IMASK_CRC_RES_ERROR(v) (((v) & 0x1) << 12) #define BFM_MSC_IMASK_CRC_RES_ERROR(v) BM_MSC_IMASK_CRC_RES_ERROR #define BF_MSC_IMASK_CRC_RES_ERROR_V(e) BF_MSC_IMASK_CRC_RES_ERROR(BV_MSC_IMASK_CRC_RES_ERROR__##e) #define BFM_MSC_IMASK_CRC_RES_ERROR_V(v) BM_MSC_IMASK_CRC_RES_ERROR #define BP_MSC_IMASK_CRC_READ_ERROR 11 #define BM_MSC_IMASK_CRC_READ_ERROR 0x800 #define BF_MSC_IMASK_CRC_READ_ERROR(v) (((v) & 0x1) << 11) #define BFM_MSC_IMASK_CRC_READ_ERROR(v) BM_MSC_IMASK_CRC_READ_ERROR #define BF_MSC_IMASK_CRC_READ_ERROR_V(e) BF_MSC_IMASK_CRC_READ_ERROR(BV_MSC_IMASK_CRC_READ_ERROR__##e) #define BFM_MSC_IMASK_CRC_READ_ERROR_V(v) BM_MSC_IMASK_CRC_READ_ERROR #define BP_MSC_IMASK_CRC_WRITE_ERROR 10 #define BM_MSC_IMASK_CRC_WRITE_ERROR 0x400 #define BF_MSC_IMASK_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) #define BFM_MSC_IMASK_CRC_WRITE_ERROR(v) BM_MSC_IMASK_CRC_WRITE_ERROR #define BF_MSC_IMASK_CRC_WRITE_ERROR_V(e) BF_MSC_IMASK_CRC_WRITE_ERROR(BV_MSC_IMASK_CRC_WRITE_ERROR__##e) #define BFM_MSC_IMASK_CRC_WRITE_ERROR_V(v) BM_MSC_IMASK_CRC_WRITE_ERROR #define BP_MSC_IMASK_TIME_OUT_RES 9 #define BM_MSC_IMASK_TIME_OUT_RES 0x200 #define BF_MSC_IMASK_TIME_OUT_RES(v) (((v) & 0x1) << 9) #define BFM_MSC_IMASK_TIME_OUT_RES(v) BM_MSC_IMASK_TIME_OUT_RES #define BF_MSC_IMASK_TIME_OUT_RES_V(e) BF_MSC_IMASK_TIME_OUT_RES(BV_MSC_IMASK_TIME_OUT_RES__##e) #define BFM_MSC_IMASK_TIME_OUT_RES_V(v) BM_MSC_IMASK_TIME_OUT_RES #define BP_MSC_IMASK_TIME_OUT_READ 8 #define BM_MSC_IMASK_TIME_OUT_READ 0x100 #define BF_MSC_IMASK_TIME_OUT_READ(v) (((v) & 0x1) << 8) #define BFM_MSC_IMASK_TIME_OUT_READ(v) BM_MSC_IMASK_TIME_OUT_READ #define BF_MSC_IMASK_TIME_OUT_READ_V(e) BF_MSC_IMASK_TIME_OUT_READ(BV_MSC_IMASK_TIME_OUT_READ__##e) #define BFM_MSC_IMASK_TIME_OUT_READ_V(v) BM_MSC_IMASK_TIME_OUT_READ #define BP_MSC_IMASK_SDIO 7 #define BM_MSC_IMASK_SDIO 0x80 #define BF_MSC_IMASK_SDIO(v) (((v) & 0x1) << 7) #define BFM_MSC_IMASK_SDIO(v) BM_MSC_IMASK_SDIO #define BF_MSC_IMASK_SDIO_V(e) BF_MSC_IMASK_SDIO(BV_MSC_IMASK_SDIO__##e) #define BFM_MSC_IMASK_SDIO_V(v) BM_MSC_IMASK_SDIO #define BP_MSC_IMASK_TXFIFO_WR_REQ 6 #define BM_MSC_IMASK_TXFIFO_WR_REQ 0x40 #define BF_MSC_IMASK_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) #define BFM_MSC_IMASK_TXFIFO_WR_REQ(v) BM_MSC_IMASK_TXFIFO_WR_REQ #define BF_MSC_IMASK_TXFIFO_WR_REQ_V(e) BF_MSC_IMASK_TXFIFO_WR_REQ(BV_MSC_IMASK_TXFIFO_WR_REQ__##e) #define BFM_MSC_IMASK_TXFIFO_WR_REQ_V(v) BM_MSC_IMASK_TXFIFO_WR_REQ #define BP_MSC_IMASK_RXFIFO_RD_REQ 5 #define BM_MSC_IMASK_RXFIFO_RD_REQ 0x20 #define BF_MSC_IMASK_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) #define BFM_MSC_IMASK_RXFIFO_RD_REQ(v) BM_MSC_IMASK_RXFIFO_RD_REQ #define BF_MSC_IMASK_RXFIFO_RD_REQ_V(e) BF_MSC_IMASK_RXFIFO_RD_REQ(BV_MSC_IMASK_RXFIFO_RD_REQ__##e) #define BFM_MSC_IMASK_RXFIFO_RD_REQ_V(v) BM_MSC_IMASK_RXFIFO_RD_REQ #define BP_MSC_IMASK_END_CMD_RES 2 #define BM_MSC_IMASK_END_CMD_RES 0x4 #define BF_MSC_IMASK_END_CMD_RES(v) (((v) & 0x1) << 2) #define BFM_MSC_IMASK_END_CMD_RES(v) BM_MSC_IMASK_END_CMD_RES #define BF_MSC_IMASK_END_CMD_RES_V(e) BF_MSC_IMASK_END_CMD_RES(BV_MSC_IMASK_END_CMD_RES__##e) #define BFM_MSC_IMASK_END_CMD_RES_V(v) BM_MSC_IMASK_END_CMD_RES #define BP_MSC_IMASK_PROG_DONE 1 #define BM_MSC_IMASK_PROG_DONE 0x2 #define BF_MSC_IMASK_PROG_DONE(v) (((v) & 0x1) << 1) #define BFM_MSC_IMASK_PROG_DONE(v) BM_MSC_IMASK_PROG_DONE #define BF_MSC_IMASK_PROG_DONE_V(e) BF_MSC_IMASK_PROG_DONE(BV_MSC_IMASK_PROG_DONE__##e) #define BFM_MSC_IMASK_PROG_DONE_V(v) BM_MSC_IMASK_PROG_DONE #define BP_MSC_IMASK_DATA_TRAN_DONE 0 #define BM_MSC_IMASK_DATA_TRAN_DONE 0x1 #define BF_MSC_IMASK_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) #define BFM_MSC_IMASK_DATA_TRAN_DONE(v) BM_MSC_IMASK_DATA_TRAN_DONE #define BF_MSC_IMASK_DATA_TRAN_DONE_V(e) BF_MSC_IMASK_DATA_TRAN_DONE(BV_MSC_IMASK_DATA_TRAN_DONE__##e) #define BFM_MSC_IMASK_DATA_TRAN_DONE_V(v) BM_MSC_IMASK_DATA_TRAN_DONE #define REG_MSC_IFLAG(_n1) jz_reg(MSC_IFLAG(_n1)) #define JA_MSC_IFLAG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x28) #define JT_MSC_IFLAG(_n1) JIO_32_RW #define JN_MSC_IFLAG(_n1) MSC_IFLAG #define JI_MSC_IFLAG(_n1) (_n1) #define BP_MSC_IFLAG_PINS 24 #define BM_MSC_IFLAG_PINS 0x1f000000 #define BF_MSC_IFLAG_PINS(v) (((v) & 0x1f) << 24) #define BFM_MSC_IFLAG_PINS(v) BM_MSC_IFLAG_PINS #define BF_MSC_IFLAG_PINS_V(e) BF_MSC_IFLAG_PINS(BV_MSC_IFLAG_PINS__##e) #define BFM_MSC_IFLAG_PINS_V(v) BM_MSC_IFLAG_PINS #define BP_MSC_IFLAG_DMA_DATA_DONE 31 #define BM_MSC_IFLAG_DMA_DATA_DONE 0x80000000 #define BF_MSC_IFLAG_DMA_DATA_DONE(v) (((v) & 0x1) << 31) #define BFM_MSC_IFLAG_DMA_DATA_DONE(v) BM_MSC_IFLAG_DMA_DATA_DONE #define BF_MSC_IFLAG_DMA_DATA_DONE_V(e) BF_MSC_IFLAG_DMA_DATA_DONE(BV_MSC_IFLAG_DMA_DATA_DONE__##e) #define BFM_MSC_IFLAG_DMA_DATA_DONE_V(v) BM_MSC_IFLAG_DMA_DATA_DONE #define BP_MSC_IFLAG_WR_ALL_DONE 23 #define BM_MSC_IFLAG_WR_ALL_DONE 0x800000 #define BF_MSC_IFLAG_WR_ALL_DONE(v) (((v) & 0x1) << 23) #define BFM_MSC_IFLAG_WR_ALL_DONE(v) BM_MSC_IFLAG_WR_ALL_DONE #define BF_MSC_IFLAG_WR_ALL_DONE_V(e) BF_MSC_IFLAG_WR_ALL_DONE(BV_MSC_IFLAG_WR_ALL_DONE__##e) #define BFM_MSC_IFLAG_WR_ALL_DONE_V(v) BM_MSC_IFLAG_WR_ALL_DONE #define BP_MSC_IFLAG_BCE 20 #define BM_MSC_IFLAG_BCE 0x100000 #define BF_MSC_IFLAG_BCE(v) (((v) & 0x1) << 20) #define BFM_MSC_IFLAG_BCE(v) BM_MSC_IFLAG_BCE #define BF_MSC_IFLAG_BCE_V(e) BF_MSC_IFLAG_BCE(BV_MSC_IFLAG_BCE__##e) #define BFM_MSC_IFLAG_BCE_V(v) BM_MSC_IFLAG_BCE #define BP_MSC_IFLAG_BDE 19 #define BM_MSC_IFLAG_BDE 0x80000 #define BF_MSC_IFLAG_BDE(v) (((v) & 0x1) << 19) #define BFM_MSC_IFLAG_BDE(v) BM_MSC_IFLAG_BDE #define BF_MSC_IFLAG_BDE_V(e) BF_MSC_IFLAG_BDE(BV_MSC_IFLAG_BDE__##e) #define BFM_MSC_IFLAG_BDE_V(v) BM_MSC_IFLAG_BDE #define BP_MSC_IFLAG_BAE 18 #define BM_MSC_IFLAG_BAE 0x40000 #define BF_MSC_IFLAG_BAE(v) (((v) & 0x1) << 18) #define BFM_MSC_IFLAG_BAE(v) BM_MSC_IFLAG_BAE #define BF_MSC_IFLAG_BAE_V(e) BF_MSC_IFLAG_BAE(BV_MSC_IFLAG_BAE__##e) #define BFM_MSC_IFLAG_BAE_V(v) BM_MSC_IFLAG_BAE #define BP_MSC_IFLAG_BAR 17 #define BM_MSC_IFLAG_BAR 0x20000 #define BF_MSC_IFLAG_BAR(v) (((v) & 0x1) << 17) #define BFM_MSC_IFLAG_BAR(v) BM_MSC_IFLAG_BAR #define BF_MSC_IFLAG_BAR_V(e) BF_MSC_IFLAG_BAR(BV_MSC_IFLAG_BAR__##e) #define BFM_MSC_IFLAG_BAR_V(v) BM_MSC_IFLAG_BAR #define BP_MSC_IFLAG_DMAEND 16 #define BM_MSC_IFLAG_DMAEND 0x10000 #define BF_MSC_IFLAG_DMAEND(v) (((v) & 0x1) << 16) #define BFM_MSC_IFLAG_DMAEND(v) BM_MSC_IFLAG_DMAEND #define BF_MSC_IFLAG_DMAEND_V(e) BF_MSC_IFLAG_DMAEND(BV_MSC_IFLAG_DMAEND__##e) #define BFM_MSC_IFLAG_DMAEND_V(v) BM_MSC_IFLAG_DMAEND #define BP_MSC_IFLAG_AUTO_CMD12_DONE 15 #define BM_MSC_IFLAG_AUTO_CMD12_DONE 0x8000 #define BF_MSC_IFLAG_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) #define BFM_MSC_IFLAG_AUTO_CMD12_DONE(v) BM_MSC_IFLAG_AUTO_CMD12_DONE #define BF_MSC_IFLAG_AUTO_CMD12_DONE_V(e) BF_MSC_IFLAG_AUTO_CMD12_DONE(BV_MSC_IFLAG_AUTO_CMD12_DONE__##e) #define BFM_MSC_IFLAG_AUTO_CMD12_DONE_V(v) BM_MSC_IFLAG_AUTO_CMD12_DONE #define BP_MSC_IFLAG_DATA_FIFO_FULL 14 #define BM_MSC_IFLAG_DATA_FIFO_FULL 0x4000 #define BF_MSC_IFLAG_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) #define BFM_MSC_IFLAG_DATA_FIFO_FULL(v) BM_MSC_IFLAG_DATA_FIFO_FULL #define BF_MSC_IFLAG_DATA_FIFO_FULL_V(e) BF_MSC_IFLAG_DATA_FIFO_FULL(BV_MSC_IFLAG_DATA_FIFO_FULL__##e) #define BFM_MSC_IFLAG_DATA_FIFO_FULL_V(v) BM_MSC_IFLAG_DATA_FIFO_FULL #define BP_MSC_IFLAG_DATA_FIFO_EMPTY 13 #define BM_MSC_IFLAG_DATA_FIFO_EMPTY 0x2000 #define BF_MSC_IFLAG_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY #define BF_MSC_IFLAG_DATA_FIFO_EMPTY_V(e) BF_MSC_IFLAG_DATA_FIFO_EMPTY(BV_MSC_IFLAG_DATA_FIFO_EMPTY__##e) #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY_V(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY #define BP_MSC_IFLAG_CRC_RES_ERROR 12 #define BM_MSC_IFLAG_CRC_RES_ERROR 0x1000 #define BF_MSC_IFLAG_CRC_RES_ERROR(v) (((v) & 0x1) << 12) #define BFM_MSC_IFLAG_CRC_RES_ERROR(v) BM_MSC_IFLAG_CRC_RES_ERROR #define BF_MSC_IFLAG_CRC_RES_ERROR_V(e) BF_MSC_IFLAG_CRC_RES_ERROR(BV_MSC_IFLAG_CRC_RES_ERROR__##e) #define BFM_MSC_IFLAG_CRC_RES_ERROR_V(v) BM_MSC_IFLAG_CRC_RES_ERROR #define BP_MSC_IFLAG_CRC_READ_ERROR 11 #define BM_MSC_IFLAG_CRC_READ_ERROR 0x800 #define BF_MSC_IFLAG_CRC_READ_ERROR(v) (((v) & 0x1) << 11) #define BFM_MSC_IFLAG_CRC_READ_ERROR(v) BM_MSC_IFLAG_CRC_READ_ERROR #define BF_MSC_IFLAG_CRC_READ_ERROR_V(e) BF_MSC_IFLAG_CRC_READ_ERROR(BV_MSC_IFLAG_CRC_READ_ERROR__##e) #define BFM_MSC_IFLAG_CRC_READ_ERROR_V(v) BM_MSC_IFLAG_CRC_READ_ERROR #define BP_MSC_IFLAG_CRC_WRITE_ERROR 10 #define BM_MSC_IFLAG_CRC_WRITE_ERROR 0x400 #define BF_MSC_IFLAG_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) #define BFM_MSC_IFLAG_CRC_WRITE_ERROR(v) BM_MSC_IFLAG_CRC_WRITE_ERROR #define BF_MSC_IFLAG_CRC_WRITE_ERROR_V(e) BF_MSC_IFLAG_CRC_WRITE_ERROR(BV_MSC_IFLAG_CRC_WRITE_ERROR__##e) #define BFM_MSC_IFLAG_CRC_WRITE_ERROR_V(v) BM_MSC_IFLAG_CRC_WRITE_ERROR #define BP_MSC_IFLAG_TIME_OUT_RES 9 #define BM_MSC_IFLAG_TIME_OUT_RES 0x200 #define BF_MSC_IFLAG_TIME_OUT_RES(v) (((v) & 0x1) << 9) #define BFM_MSC_IFLAG_TIME_OUT_RES(v) BM_MSC_IFLAG_TIME_OUT_RES #define BF_MSC_IFLAG_TIME_OUT_RES_V(e) BF_MSC_IFLAG_TIME_OUT_RES(BV_MSC_IFLAG_TIME_OUT_RES__##e) #define BFM_MSC_IFLAG_TIME_OUT_RES_V(v) BM_MSC_IFLAG_TIME_OUT_RES #define BP_MSC_IFLAG_TIME_OUT_READ 8 #define BM_MSC_IFLAG_TIME_OUT_READ 0x100 #define BF_MSC_IFLAG_TIME_OUT_READ(v) (((v) & 0x1) << 8) #define BFM_MSC_IFLAG_TIME_OUT_READ(v) BM_MSC_IFLAG_TIME_OUT_READ #define BF_MSC_IFLAG_TIME_OUT_READ_V(e) BF_MSC_IFLAG_TIME_OUT_READ(BV_MSC_IFLAG_TIME_OUT_READ__##e) #define BFM_MSC_IFLAG_TIME_OUT_READ_V(v) BM_MSC_IFLAG_TIME_OUT_READ #define BP_MSC_IFLAG_SDIO 7 #define BM_MSC_IFLAG_SDIO 0x80 #define BF_MSC_IFLAG_SDIO(v) (((v) & 0x1) << 7) #define BFM_MSC_IFLAG_SDIO(v) BM_MSC_IFLAG_SDIO #define BF_MSC_IFLAG_SDIO_V(e) BF_MSC_IFLAG_SDIO(BV_MSC_IFLAG_SDIO__##e) #define BFM_MSC_IFLAG_SDIO_V(v) BM_MSC_IFLAG_SDIO #define BP_MSC_IFLAG_TXFIFO_WR_REQ 6 #define BM_MSC_IFLAG_TXFIFO_WR_REQ 0x40 #define BF_MSC_IFLAG_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) #define BFM_MSC_IFLAG_TXFIFO_WR_REQ(v) BM_MSC_IFLAG_TXFIFO_WR_REQ #define BF_MSC_IFLAG_TXFIFO_WR_REQ_V(e) BF_MSC_IFLAG_TXFIFO_WR_REQ(BV_MSC_IFLAG_TXFIFO_WR_REQ__##e) #define BFM_MSC_IFLAG_TXFIFO_WR_REQ_V(v) BM_MSC_IFLAG_TXFIFO_WR_REQ #define BP_MSC_IFLAG_RXFIFO_RD_REQ 5 #define BM_MSC_IFLAG_RXFIFO_RD_REQ 0x20 #define BF_MSC_IFLAG_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) #define BFM_MSC_IFLAG_RXFIFO_RD_REQ(v) BM_MSC_IFLAG_RXFIFO_RD_REQ #define BF_MSC_IFLAG_RXFIFO_RD_REQ_V(e) BF_MSC_IFLAG_RXFIFO_RD_REQ(BV_MSC_IFLAG_RXFIFO_RD_REQ__##e) #define BFM_MSC_IFLAG_RXFIFO_RD_REQ_V(v) BM_MSC_IFLAG_RXFIFO_RD_REQ #define BP_MSC_IFLAG_END_CMD_RES 2 #define BM_MSC_IFLAG_END_CMD_RES 0x4 #define BF_MSC_IFLAG_END_CMD_RES(v) (((v) & 0x1) << 2) #define BFM_MSC_IFLAG_END_CMD_RES(v) BM_MSC_IFLAG_END_CMD_RES #define BF_MSC_IFLAG_END_CMD_RES_V(e) BF_MSC_IFLAG_END_CMD_RES(BV_MSC_IFLAG_END_CMD_RES__##e) #define BFM_MSC_IFLAG_END_CMD_RES_V(v) BM_MSC_IFLAG_END_CMD_RES #define BP_MSC_IFLAG_PROG_DONE 1 #define BM_MSC_IFLAG_PROG_DONE 0x2 #define BF_MSC_IFLAG_PROG_DONE(v) (((v) & 0x1) << 1) #define BFM_MSC_IFLAG_PROG_DONE(v) BM_MSC_IFLAG_PROG_DONE #define BF_MSC_IFLAG_PROG_DONE_V(e) BF_MSC_IFLAG_PROG_DONE(BV_MSC_IFLAG_PROG_DONE__##e) #define BFM_MSC_IFLAG_PROG_DONE_V(v) BM_MSC_IFLAG_PROG_DONE #define BP_MSC_IFLAG_DATA_TRAN_DONE 0 #define BM_MSC_IFLAG_DATA_TRAN_DONE 0x1 #define BF_MSC_IFLAG_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) #define BFM_MSC_IFLAG_DATA_TRAN_DONE(v) BM_MSC_IFLAG_DATA_TRAN_DONE #define BF_MSC_IFLAG_DATA_TRAN_DONE_V(e) BF_MSC_IFLAG_DATA_TRAN_DONE(BV_MSC_IFLAG_DATA_TRAN_DONE__##e) #define BFM_MSC_IFLAG_DATA_TRAN_DONE_V(v) BM_MSC_IFLAG_DATA_TRAN_DONE #define REG_MSC_LPM(_n1) jz_reg(MSC_LPM(_n1)) #define JA_MSC_LPM(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x40) #define JT_MSC_LPM(_n1) JIO_32_RW #define JN_MSC_LPM(_n1) MSC_LPM #define JI_MSC_LPM(_n1) (_n1) #define BP_MSC_LPM_DRV_SEL 30 #define BM_MSC_LPM_DRV_SEL 0xc0000000 #define BV_MSC_LPM_DRV_SEL__FALL_EDGE 0x0 #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_1NS 0x1 #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_QTR_PHASE 0x2 #define BF_MSC_LPM_DRV_SEL(v) (((v) & 0x3) << 30) #define BFM_MSC_LPM_DRV_SEL(v) BM_MSC_LPM_DRV_SEL #define BF_MSC_LPM_DRV_SEL_V(e) BF_MSC_LPM_DRV_SEL(BV_MSC_LPM_DRV_SEL__##e) #define BFM_MSC_LPM_DRV_SEL_V(v) BM_MSC_LPM_DRV_SEL #define BP_MSC_LPM_SMP_SEL 28 #define BM_MSC_LPM_SMP_SEL 0x30000000 #define BV_MSC_LPM_SMP_SEL__RISE_EDGE 0x0 #define BV_MSC_LPM_SMP_SEL__RISE_EDGE_DELAYED 0x1 #define BF_MSC_LPM_SMP_SEL(v) (((v) & 0x3) << 28) #define BFM_MSC_LPM_SMP_SEL(v) BM_MSC_LPM_SMP_SEL #define BF_MSC_LPM_SMP_SEL_V(e) BF_MSC_LPM_SMP_SEL(BV_MSC_LPM_SMP_SEL__##e) #define BFM_MSC_LPM_SMP_SEL_V(v) BM_MSC_LPM_SMP_SEL #define BP_MSC_LPM_ENABLE 0 #define BM_MSC_LPM_ENABLE 0x1 #define BF_MSC_LPM_ENABLE(v) (((v) & 0x1) << 0) #define BFM_MSC_LPM_ENABLE(v) BM_MSC_LPM_ENABLE #define BF_MSC_LPM_ENABLE_V(e) BF_MSC_LPM_ENABLE(BV_MSC_LPM_ENABLE__##e) #define BFM_MSC_LPM_ENABLE_V(v) BM_MSC_LPM_ENABLE #define REG_MSC_DMAC(_n1) jz_reg(MSC_DMAC(_n1)) #define JA_MSC_DMAC(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x44) #define JT_MSC_DMAC(_n1) JIO_32_RW #define JN_MSC_DMAC(_n1) MSC_DMAC #define JI_MSC_DMAC(_n1) (_n1) #define BP_MSC_DMAC_ADDR_OFFSET 5 #define BM_MSC_DMAC_ADDR_OFFSET 0x60 #define BF_MSC_DMAC_ADDR_OFFSET(v) (((v) & 0x3) << 5) #define BFM_MSC_DMAC_ADDR_OFFSET(v) BM_MSC_DMAC_ADDR_OFFSET #define BF_MSC_DMAC_ADDR_OFFSET_V(e) BF_MSC_DMAC_ADDR_OFFSET(BV_MSC_DMAC_ADDR_OFFSET__##e) #define BFM_MSC_DMAC_ADDR_OFFSET_V(v) BM_MSC_DMAC_ADDR_OFFSET #define BP_MSC_DMAC_INCR 2 #define BM_MSC_DMAC_INCR 0xc #define BF_MSC_DMAC_INCR(v) (((v) & 0x3) << 2) #define BFM_MSC_DMAC_INCR(v) BM_MSC_DMAC_INCR #define BF_MSC_DMAC_INCR_V(e) BF_MSC_DMAC_INCR(BV_MSC_DMAC_INCR__##e) #define BFM_MSC_DMAC_INCR_V(v) BM_MSC_DMAC_INCR #define BP_MSC_DMAC_MODE_SEL 7 #define BM_MSC_DMAC_MODE_SEL 0x80 #define BF_MSC_DMAC_MODE_SEL(v) (((v) & 0x1) << 7) #define BFM_MSC_DMAC_MODE_SEL(v) BM_MSC_DMAC_MODE_SEL #define BF_MSC_DMAC_MODE_SEL_V(e) BF_MSC_DMAC_MODE_SEL(BV_MSC_DMAC_MODE_SEL__##e) #define BFM_MSC_DMAC_MODE_SEL_V(v) BM_MSC_DMAC_MODE_SEL #define BP_MSC_DMAC_ALIGN_EN 4 #define BM_MSC_DMAC_ALIGN_EN 0x10 #define BF_MSC_DMAC_ALIGN_EN(v) (((v) & 0x1) << 4) #define BFM_MSC_DMAC_ALIGN_EN(v) BM_MSC_DMAC_ALIGN_EN #define BF_MSC_DMAC_ALIGN_EN_V(e) BF_MSC_DMAC_ALIGN_EN(BV_MSC_DMAC_ALIGN_EN__##e) #define BFM_MSC_DMAC_ALIGN_EN_V(v) BM_MSC_DMAC_ALIGN_EN #define BP_MSC_DMAC_DMASEL 1 #define BM_MSC_DMAC_DMASEL 0x2 #define BF_MSC_DMAC_DMASEL(v) (((v) & 0x1) << 1) #define BFM_MSC_DMAC_DMASEL(v) BM_MSC_DMAC_DMASEL #define BF_MSC_DMAC_DMASEL_V(e) BF_MSC_DMAC_DMASEL(BV_MSC_DMAC_DMASEL__##e) #define BFM_MSC_DMAC_DMASEL_V(v) BM_MSC_DMAC_DMASEL #define BP_MSC_DMAC_ENABLE 0 #define BM_MSC_DMAC_ENABLE 0x1 #define BF_MSC_DMAC_ENABLE(v) (((v) & 0x1) << 0) #define BFM_MSC_DMAC_ENABLE(v) BM_MSC_DMAC_ENABLE #define BF_MSC_DMAC_ENABLE_V(e) BF_MSC_DMAC_ENABLE(BV_MSC_DMAC_ENABLE__##e) #define BFM_MSC_DMAC_ENABLE_V(v) BM_MSC_DMAC_ENABLE #define REG_MSC_CTRL2(_n1) jz_reg(MSC_CTRL2(_n1)) #define JA_MSC_CTRL2(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x58) #define JT_MSC_CTRL2(_n1) JIO_32_RW #define JN_MSC_CTRL2(_n1) MSC_CTRL2 #define JI_MSC_CTRL2(_n1) (_n1) #define BP_MSC_CTRL2_PIN_INT_POLARITY 24 #define BM_MSC_CTRL2_PIN_INT_POLARITY 0x1f000000 #define BF_MSC_CTRL2_PIN_INT_POLARITY(v) (((v) & 0x1f) << 24) #define BFM_MSC_CTRL2_PIN_INT_POLARITY(v) BM_MSC_CTRL2_PIN_INT_POLARITY #define BF_MSC_CTRL2_PIN_INT_POLARITY_V(e) BF_MSC_CTRL2_PIN_INT_POLARITY(BV_MSC_CTRL2_PIN_INT_POLARITY__##e) #define BFM_MSC_CTRL2_PIN_INT_POLARITY_V(v) BM_MSC_CTRL2_PIN_INT_POLARITY #define BP_MSC_CTRL2_SPEED 0 #define BM_MSC_CTRL2_SPEED 0x7 #define BV_MSC_CTRL2_SPEED__DEFAULT 0x0 #define BV_MSC_CTRL2_SPEED__HIGHSPEED 0x1 #define BV_MSC_CTRL2_SPEED__SDR12 0x2 #define BV_MSC_CTRL2_SPEED__SDR25 0x3 #define BV_MSC_CTRL2_SPEED__SDR50 0x4 #define BF_MSC_CTRL2_SPEED(v) (((v) & 0x7) << 0) #define BFM_MSC_CTRL2_SPEED(v) BM_MSC_CTRL2_SPEED #define BF_MSC_CTRL2_SPEED_V(e) BF_MSC_CTRL2_SPEED(BV_MSC_CTRL2_SPEED__##e) #define BFM_MSC_CTRL2_SPEED_V(v) BM_MSC_CTRL2_SPEED #define BP_MSC_CTRL2_STPRM 4 #define BM_MSC_CTRL2_STPRM 0x10 #define BF_MSC_CTRL2_STPRM(v) (((v) & 0x1) << 4) #define BFM_MSC_CTRL2_STPRM(v) BM_MSC_CTRL2_STPRM #define BF_MSC_CTRL2_STPRM_V(e) BF_MSC_CTRL2_STPRM(BV_MSC_CTRL2_STPRM__##e) #define BFM_MSC_CTRL2_STPRM_V(v) BM_MSC_CTRL2_STPRM #define REG_MSC_CLKRT(_n1) jz_reg(MSC_CLKRT(_n1)) #define JA_MSC_CLKRT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x8) #define JT_MSC_CLKRT(_n1) JIO_32_RW #define JN_MSC_CLKRT(_n1) MSC_CLKRT #define JI_MSC_CLKRT(_n1) (_n1) #define REG_MSC_RESTO(_n1) jz_reg(MSC_RESTO(_n1)) #define JA_MSC_RESTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x10) #define JT_MSC_RESTO(_n1) JIO_32_RW #define JN_MSC_RESTO(_n1) MSC_RESTO #define JI_MSC_RESTO(_n1) (_n1) #define REG_MSC_RDTO(_n1) jz_reg(MSC_RDTO(_n1)) #define JA_MSC_RDTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x14) #define JT_MSC_RDTO(_n1) JIO_32_RW #define JN_MSC_RDTO(_n1) MSC_RDTO #define JI_MSC_RDTO(_n1) (_n1) #define REG_MSC_BLKLEN(_n1) jz_reg(MSC_BLKLEN(_n1)) #define JA_MSC_BLKLEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x18) #define JT_MSC_BLKLEN(_n1) JIO_32_RW #define JN_MSC_BLKLEN(_n1) MSC_BLKLEN #define JI_MSC_BLKLEN(_n1) (_n1) #define REG_MSC_NOB(_n1) jz_reg(MSC_NOB(_n1)) #define JA_MSC_NOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x1c) #define JT_MSC_NOB(_n1) JIO_32_RW #define JN_MSC_NOB(_n1) MSC_NOB #define JI_MSC_NOB(_n1) (_n1) #define REG_MSC_SNOB(_n1) jz_reg(MSC_SNOB(_n1)) #define JA_MSC_SNOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x20) #define JT_MSC_SNOB(_n1) JIO_32_RW #define JN_MSC_SNOB(_n1) MSC_SNOB #define JI_MSC_SNOB(_n1) (_n1) #define REG_MSC_CMD(_n1) jz_reg(MSC_CMD(_n1)) #define JA_MSC_CMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x2c) #define JT_MSC_CMD(_n1) JIO_32_RW #define JN_MSC_CMD(_n1) MSC_CMD #define JI_MSC_CMD(_n1) (_n1) #define REG_MSC_ARG(_n1) jz_reg(MSC_ARG(_n1)) #define JA_MSC_ARG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x30) #define JT_MSC_ARG(_n1) JIO_32_RW #define JN_MSC_ARG(_n1) MSC_ARG #define JI_MSC_ARG(_n1) (_n1) #define REG_MSC_RES(_n1) jz_reg(MSC_RES(_n1)) #define JA_MSC_RES(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x34) #define JT_MSC_RES(_n1) JIO_32_RW #define JN_MSC_RES(_n1) MSC_RES #define JI_MSC_RES(_n1) (_n1) #define REG_MSC_RXFIFO(_n1) jz_reg(MSC_RXFIFO(_n1)) #define JA_MSC_RXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x38) #define JT_MSC_RXFIFO(_n1) JIO_32_RW #define JN_MSC_RXFIFO(_n1) MSC_RXFIFO #define JI_MSC_RXFIFO(_n1) (_n1) #define REG_MSC_TXFIFO(_n1) jz_reg(MSC_TXFIFO(_n1)) #define JA_MSC_TXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x3c) #define JT_MSC_TXFIFO(_n1) JIO_32_RW #define JN_MSC_TXFIFO(_n1) MSC_TXFIFO #define JI_MSC_TXFIFO(_n1) (_n1) #define REG_MSC_DMANDA(_n1) jz_reg(MSC_DMANDA(_n1)) #define JA_MSC_DMANDA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x48) #define JT_MSC_DMANDA(_n1) JIO_32_RW #define JN_MSC_DMANDA(_n1) MSC_DMANDA #define JI_MSC_DMANDA(_n1) (_n1) #define REG_MSC_DMADA(_n1) jz_reg(MSC_DMADA(_n1)) #define JA_MSC_DMADA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4c) #define JT_MSC_DMADA(_n1) JIO_32_RW #define JN_MSC_DMADA(_n1) MSC_DMADA #define JI_MSC_DMADA(_n1) (_n1) #define REG_MSC_DMALEN(_n1) jz_reg(MSC_DMALEN(_n1)) #define JA_MSC_DMALEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x50) #define JT_MSC_DMALEN(_n1) JIO_32_RW #define JN_MSC_DMALEN(_n1) MSC_DMALEN #define JI_MSC_DMALEN(_n1) (_n1) #define REG_MSC_DMACMD(_n1) jz_reg(MSC_DMACMD(_n1)) #define JA_MSC_DMACMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x54) #define JT_MSC_DMACMD(_n1) JIO_32_RW #define JN_MSC_DMACMD(_n1) MSC_DMACMD #define JI_MSC_DMACMD(_n1) (_n1) #define REG_MSC_RTCNT(_n1) jz_reg(MSC_RTCNT(_n1)) #define JA_MSC_RTCNT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x5c) #define JT_MSC_RTCNT(_n1) JIO_32_RW #define JN_MSC_RTCNT(_n1) MSC_RTCNT #define JI_MSC_RTCNT(_n1) (_n1) #endif /* __HEADERGEN_MSC_H__*/