/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * stmp3700 version: 2.4.0 * stmp3700 authors: Amaury Pouly * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_STMP3700_DIGCTL_H__ #define __HEADERGEN_STMP3700_DIGCTL_H__ #define HW_DIGCTL_CTRL HW(DIGCTL_CTRL) #define HWA_DIGCTL_CTRL (0x8001c000 + 0x0) #define HWT_DIGCTL_CTRL HWIO_32_RW #define HWN_DIGCTL_CTRL DIGCTL_CTRL #define HWI_DIGCTL_CTRL #define HW_DIGCTL_CTRL_SET HW(DIGCTL_CTRL_SET) #define HWA_DIGCTL_CTRL_SET (HWA_DIGCTL_CTRL + 0x4) #define HWT_DIGCTL_CTRL_SET HWIO_32_WO #define HWN_DIGCTL_CTRL_SET DIGCTL_CTRL #define HWI_DIGCTL_CTRL_SET #define HW_DIGCTL_CTRL_CLR HW(DIGCTL_CTRL_CLR) #define HWA_DIGCTL_CTRL_CLR (HWA_DIGCTL_CTRL + 0x8) #define HWT_DIGCTL_CTRL_CLR HWIO_32_WO #define HWN_DIGCTL_CTRL_CLR DIGCTL_CTRL #define HWI_DIGCTL_CTRL_CLR #define HW_DIGCTL_CTRL_TOG HW(DIGCTL_CTRL_TOG) #define HWA_DIGCTL_CTRL_TOG (HWA_DIGCTL_CTRL + 0xc) #define HWT_DIGCTL_CTRL_TOG HWIO_32_WO #define HWN_DIGCTL_CTRL_TOG DIGCTL_CTRL #define HWI_DIGCTL_CTRL_TOG #define BP_DIGCTL_CTRL_TRAP_IRQ 29 #define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 #define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) & 0x1) << 29) #define BFM_DIGCTL_CTRL_TRAP_IRQ(v) BM_DIGCTL_CTRL_TRAP_IRQ #define BF_DIGCTL_CTRL_TRAP_IRQ_V(e) BF_DIGCTL_CTRL_TRAP_IRQ(BV_DIGCTL_CTRL_TRAP_IRQ__##e) #define BFM_DIGCTL_CTRL_TRAP_IRQ_V(v) BM_DIGCTL_CTRL_TRAP_IRQ #define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 #define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) & 0x1) << 23) #define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN(v) BM_DIGCTL_CTRL_DCP_BIST_CLKEN #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN_V(e) BF_DIGCTL_CTRL_DCP_BIST_CLKEN(BV_DIGCTL_CTRL_DCP_BIST_CLKEN__##e) #define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN_V(v) BM_DIGCTL_CTRL_DCP_BIST_CLKEN #define BP_DIGCTL_CTRL_DCP_BIST_START 22 #define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 #define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) & 0x1) << 22) #define BFM_DIGCTL_CTRL_DCP_BIST_START(v) BM_DIGCTL_CTRL_DCP_BIST_START #define BF_DIGCTL_CTRL_DCP_BIST_START_V(e) BF_DIGCTL_CTRL_DCP_BIST_START(BV_DIGCTL_CTRL_DCP_BIST_START__##e) #define BFM_DIGCTL_CTRL_DCP_BIST_START_V(v) BM_DIGCTL_CTRL_DCP_BIST_START #define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 #define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) & 0x1) << 21) #define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN(v) BM_DIGCTL_CTRL_ARM_BIST_CLKEN #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN_V(e) BF_DIGCTL_CTRL_ARM_BIST_CLKEN(BV_DIGCTL_CTRL_ARM_BIST_CLKEN__##e) #define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN_V(v) BM_DIGCTL_CTRL_ARM_BIST_CLKEN #define BP_DIGCTL_CTRL_USB_TESTMODE 20 #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) & 0x1) << 20) #define BFM_DIGCTL_CTRL_USB_TESTMODE(v) BM_DIGCTL_CTRL_USB_TESTMODE #define BF_DIGCTL_CTRL_USB_TESTMODE_V(e) BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e) #define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v) BM_DIGCTL_CTRL_USB_TESTMODE #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) & 0x1) << 19) #define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE #define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e) BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e) #define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) & 0x1) << 18) #define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e) BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e) #define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE #define BP_DIGCTL_CTRL_ARM_BIST_START 17 #define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 #define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) & 0x1) << 17) #define BFM_DIGCTL_CTRL_ARM_BIST_START(v) BM_DIGCTL_CTRL_ARM_BIST_START #define BF_DIGCTL_CTRL_ARM_BIST_START_V(e) BF_DIGCTL_CTRL_ARM_BIST_START(BV_DIGCTL_CTRL_ARM_BIST_START__##e) #define BFM_DIGCTL_CTRL_ARM_BIST_START_V(v) BM_DIGCTL_CTRL_ARM_BIST_START #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) & 0x1) << 16) #define BFM_DIGCTL_CTRL_UART_LOOPBACK(v) BM_DIGCTL_CTRL_UART_LOOPBACK #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e) BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e) #define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v) BM_DIGCTL_CTRL_UART_LOOPBACK #define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 #define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 #define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) & 0x1) << 15) #define BFM_DIGCTL_CTRL_SAIF_LOOPBACK(v) BM_DIGCTL_CTRL_SAIF_LOOPBACK #define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(e) BF_DIGCTL_CTRL_SAIF_LOOPBACK(BV_DIGCTL_CTRL_SAIF_LOOPBACK__##e) #define BFM_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) BM_DIGCTL_CTRL_SAIF_LOOPBACK #define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 #define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) & 0x3) << 13) #define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(e) BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##e) #define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL #define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 #define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) & 0x1) << 12) #define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) BM_DIGCTL_CTRL_SAIF_CLKMST_SEL #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(e) BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##e) #define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) BM_DIGCTL_CTRL_SAIF_CLKMST_SEL #define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 #define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) & 0x1) << 11) #define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(e) BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(BV_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL__##e) #define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(v) BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL #define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 #define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) & 0x1) << 6) #define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG(v) BM_DIGCTL_CTRL_USE_SERIAL_JTAG #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(e) BF_DIGCTL_CTRL_USE_SERIAL_JTAG(BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##e) #define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) BM_DIGCTL_CTRL_USE_SERIAL_JTAG #define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 #define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 #define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) & 0x1) << 5) #define BFM_DIGCTL_CTRL_TRAP_IN_RANGE(v) BM_DIGCTL_CTRL_TRAP_IN_RANGE #define BF_DIGCTL_CTRL_TRAP_IN_RANGE_V(e) BF_DIGCTL_CTRL_TRAP_IN_RANGE(BV_DIGCTL_CTRL_TRAP_IN_RANGE__##e) #define BFM_DIGCTL_CTRL_TRAP_IN_RANGE_V(v) BM_DIGCTL_CTRL_TRAP_IN_RANGE #define BP_DIGCTL_CTRL_TRAP_ENABLE 4 #define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 #define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) & 0x1) << 4) #define BFM_DIGCTL_CTRL_TRAP_ENABLE(v) BM_DIGCTL_CTRL_TRAP_ENABLE #define BF_DIGCTL_CTRL_TRAP_ENABLE_V(e) BF_DIGCTL_CTRL_TRAP_ENABLE(BV_DIGCTL_CTRL_TRAP_ENABLE__##e) #define BFM_DIGCTL_CTRL_TRAP_ENABLE_V(v) BM_DIGCTL_CTRL_TRAP_ENABLE #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v) BM_DIGCTL_CTRL_DEBUG_DISABLE #define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e) BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e) #define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v) BM_DIGCTL_CTRL_DEBUG_DISABLE #define BP_DIGCTL_CTRL_USB_CLKGATE 2 #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_CTRL_USB_CLKGATE(v) BM_DIGCTL_CTRL_USB_CLKGATE #define BF_DIGCTL_CTRL_USB_CLKGATE_V(e) BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e) #define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v) BM_DIGCTL_CTRL_USB_CLKGATE #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_CTRL_JTAG_SHIELD(v) BM_DIGCTL_CTRL_JTAG_SHIELD #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e) BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e) #define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v) BM_DIGCTL_CTRL_JTAG_SHIELD #define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 #define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 #define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_CTRL_LATCH_ENTROPY(v) BM_DIGCTL_CTRL_LATCH_ENTROPY #define BF_DIGCTL_CTRL_LATCH_ENTROPY_V(e) BF_DIGCTL_CTRL_LATCH_ENTROPY(BV_DIGCTL_CTRL_LATCH_ENTROPY__##e) #define BFM_DIGCTL_CTRL_LATCH_ENTROPY_V(v) BM_DIGCTL_CTRL_LATCH_ENTROPY #define HW_DIGCTL_STATUS HW(DIGCTL_STATUS) #define HWA_DIGCTL_STATUS (0x8001c000 + 0x10) #define HWT_DIGCTL_STATUS HWIO_32_RW #define HWN_DIGCTL_STATUS DIGCTL_STATUS #define HWI_DIGCTL_STATUS #define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 #define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 #define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) & 0x1) << 31) #define BFM_DIGCTL_STATUS_USB_HS_PRESENT(v) BM_DIGCTL_STATUS_USB_HS_PRESENT #define BF_DIGCTL_STATUS_USB_HS_PRESENT_V(e) BF_DIGCTL_STATUS_USB_HS_PRESENT(BV_DIGCTL_STATUS_USB_HS_PRESENT__##e) #define BFM_DIGCTL_STATUS_USB_HS_PRESENT_V(v) BM_DIGCTL_STATUS_USB_HS_PRESENT #define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 #define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 #define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) & 0x1) << 30) #define BFM_DIGCTL_STATUS_USB_OTG_PRESENT(v) BM_DIGCTL_STATUS_USB_OTG_PRESENT #define BF_DIGCTL_STATUS_USB_OTG_PRESENT_V(e) BF_DIGCTL_STATUS_USB_OTG_PRESENT(BV_DIGCTL_STATUS_USB_OTG_PRESENT__##e) #define BFM_DIGCTL_STATUS_USB_OTG_PRESENT_V(v) BM_DIGCTL_STATUS_USB_OTG_PRESENT #define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 #define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 #define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) & 0x1) << 29) #define BFM_DIGCTL_STATUS_USB_HOST_PRESENT(v) BM_DIGCTL_STATUS_USB_HOST_PRESENT #define BF_DIGCTL_STATUS_USB_HOST_PRESENT_V(e) BF_DIGCTL_STATUS_USB_HOST_PRESENT(BV_DIGCTL_STATUS_USB_HOST_PRESENT__##e) #define BFM_DIGCTL_STATUS_USB_HOST_PRESENT_V(v) BM_DIGCTL_STATUS_USB_HOST_PRESENT #define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 #define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) & 0x1) << 28) #define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) BM_DIGCTL_STATUS_USB_DEVICE_PRESENT #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(e) BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(BV_DIGCTL_STATUS_USB_DEVICE_PRESENT__##e) #define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(v) BM_DIGCTL_STATUS_USB_DEVICE_PRESENT #define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 #define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 #define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) & 0x1) << 10) #define BFM_DIGCTL_STATUS_DCP_BIST_FAIL(v) BM_DIGCTL_STATUS_DCP_BIST_FAIL #define BF_DIGCTL_STATUS_DCP_BIST_FAIL_V(e) BF_DIGCTL_STATUS_DCP_BIST_FAIL(BV_DIGCTL_STATUS_DCP_BIST_FAIL__##e) #define BFM_DIGCTL_STATUS_DCP_BIST_FAIL_V(v) BM_DIGCTL_STATUS_DCP_BIST_FAIL #define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 #define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 #define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) & 0x1) << 9) #define BFM_DIGCTL_STATUS_DCP_BIST_PASS(v) BM_DIGCTL_STATUS_DCP_BIST_PASS #define BF_DIGCTL_STATUS_DCP_BIST_PASS_V(e) BF_DIGCTL_STATUS_DCP_BIST_PASS(BV_DIGCTL_STATUS_DCP_BIST_PASS__##e) #define BFM_DIGCTL_STATUS_DCP_BIST_PASS_V(v) BM_DIGCTL_STATUS_DCP_BIST_PASS #define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 #define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 #define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) & 0x1) << 8) #define BFM_DIGCTL_STATUS_DCP_BIST_DONE(v) BM_DIGCTL_STATUS_DCP_BIST_DONE #define BF_DIGCTL_STATUS_DCP_BIST_DONE_V(e) BF_DIGCTL_STATUS_DCP_BIST_DONE(BV_DIGCTL_STATUS_DCP_BIST_DONE__##e) #define BFM_DIGCTL_STATUS_DCP_BIST_DONE_V(v) BM_DIGCTL_STATUS_DCP_BIST_DONE #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) & 0x1) << 4) #define BFM_DIGCTL_STATUS_JTAG_IN_USE(v) BM_DIGCTL_STATUS_JTAG_IN_USE #define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e) BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e) #define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v) BM_DIGCTL_STATUS_JTAG_IN_USE #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) & 0x7) << 1) #define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v) BM_DIGCTL_STATUS_PACKAGE_TYPE #define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e) BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e) #define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v) BM_DIGCTL_STATUS_PACKAGE_TYPE #define BP_DIGCTL_STATUS_WRITTEN 0 #define BM_DIGCTL_STATUS_WRITTEN 0x1 #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_STATUS_WRITTEN(v) BM_DIGCTL_STATUS_WRITTEN #define BF_DIGCTL_STATUS_WRITTEN_V(e) BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e) #define BFM_DIGCTL_STATUS_WRITTEN_V(v) BM_DIGCTL_STATUS_WRITTEN #define HW_DIGCTL_HCLKCOUNT HW(DIGCTL_HCLKCOUNT) #define HWA_DIGCTL_HCLKCOUNT (0x8001c000 + 0x20) #define HWT_DIGCTL_HCLKCOUNT HWIO_32_RW #define HWN_DIGCTL_HCLKCOUNT DIGCTL_HCLKCOUNT #define HWI_DIGCTL_HCLKCOUNT #define BP_DIGCTL_HCLKCOUNT_COUNT 0 #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_HCLKCOUNT_COUNT(v) BM_DIGCTL_HCLKCOUNT_COUNT #define BF_DIGCTL_HCLKCOUNT_COUNT_V(e) BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e) #define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT #define HW_DIGCTL_RAMCTRL HW(DIGCTL_RAMCTRL) #define HWA_DIGCTL_RAMCTRL (0x8001c000 + 0x30) #define HWT_DIGCTL_RAMCTRL HWIO_32_RW #define HWN_DIGCTL_RAMCTRL DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL #define HW_DIGCTL_RAMCTRL_SET HW(DIGCTL_RAMCTRL_SET) #define HWA_DIGCTL_RAMCTRL_SET (HWA_DIGCTL_RAMCTRL + 0x4) #define HWT_DIGCTL_RAMCTRL_SET HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_SET DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_SET #define HW_DIGCTL_RAMCTRL_CLR HW(DIGCTL_RAMCTRL_CLR) #define HWA_DIGCTL_RAMCTRL_CLR (HWA_DIGCTL_RAMCTRL + 0x8) #define HWT_DIGCTL_RAMCTRL_CLR HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_CLR DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_CLR #define HW_DIGCTL_RAMCTRL_TOG HW(DIGCTL_RAMCTRL_TOG) #define HWA_DIGCTL_RAMCTRL_TOG (HWA_DIGCTL_RAMCTRL + 0xc) #define HWT_DIGCTL_RAMCTRL_TOG HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_TOG DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_TOG #define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 #define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 #define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) & 0xf) << 8) #define BFM_DIGCTL_RAMCTRL_SPEED_SELECT(v) BM_DIGCTL_RAMCTRL_SPEED_SELECT #define BF_DIGCTL_RAMCTRL_SPEED_SELECT_V(e) BF_DIGCTL_RAMCTRL_SPEED_SELECT(BV_DIGCTL_RAMCTRL_SPEED_SELECT__##e) #define BFM_DIGCTL_RAMCTRL_SPEED_SELECT_V(v) BM_DIGCTL_RAMCTRL_SPEED_SELECT #define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 #define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(e) BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(BV_DIGCTL_RAMCTRL_RAM_REPAIR_EN__##e) #define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(v) BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN #define HW_DIGCTL_RAMREPAIR HW(DIGCTL_RAMREPAIR) #define HWA_DIGCTL_RAMREPAIR (0x8001c000 + 0x40) #define HWT_DIGCTL_RAMREPAIR HWIO_32_RW #define HWN_DIGCTL_RAMREPAIR DIGCTL_RAMREPAIR #define HWI_DIGCTL_RAMREPAIR #define HW_DIGCTL_RAMREPAIR_SET HW(DIGCTL_RAMREPAIR_SET) #define HWA_DIGCTL_RAMREPAIR_SET (HWA_DIGCTL_RAMREPAIR + 0x4) #define HWT_DIGCTL_RAMREPAIR_SET HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR_SET DIGCTL_RAMREPAIR #define HWI_DIGCTL_RAMREPAIR_SET #define HW_DIGCTL_RAMREPAIR_CLR HW(DIGCTL_RAMREPAIR_CLR) #define HWA_DIGCTL_RAMREPAIR_CLR (HWA_DIGCTL_RAMREPAIR + 0x8) #define HWT_DIGCTL_RAMREPAIR_CLR HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR_CLR DIGCTL_RAMREPAIR #define HWI_DIGCTL_RAMREPAIR_CLR #define HW_DIGCTL_RAMREPAIR_TOG HW(DIGCTL_RAMREPAIR_TOG) #define HWA_DIGCTL_RAMREPAIR_TOG (HWA_DIGCTL_RAMREPAIR + 0xc) #define HWT_DIGCTL_RAMREPAIR_TOG HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR_TOG DIGCTL_RAMREPAIR #define HWI_DIGCTL_RAMREPAIR_TOG #define BP_DIGCTL_RAMREPAIR_ADDR 0 #define BM_DIGCTL_RAMREPAIR_ADDR 0xffff #define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_RAMREPAIR_ADDR(v) BM_DIGCTL_RAMREPAIR_ADDR #define BF_DIGCTL_RAMREPAIR_ADDR_V(e) BF_DIGCTL_RAMREPAIR_ADDR(BV_DIGCTL_RAMREPAIR_ADDR__##e) #define BFM_DIGCTL_RAMREPAIR_ADDR_V(v) BM_DIGCTL_RAMREPAIR_ADDR #define HW_DIGCTL_ROMCTRL HW(DIGCTL_ROMCTRL) #define HWA_DIGCTL_ROMCTRL (0x8001c000 + 0x50) #define HWT_DIGCTL_ROMCTRL HWIO_32_RW #define HWN_DIGCTL_ROMCTRL DIGCTL_ROMCTRL #define HWI_DIGCTL_ROMCTRL #define HW_DIGCTL_ROMCTRL_SET HW(DIGCTL_ROMCTRL_SET) #define HWA_DIGCTL_ROMCTRL_SET (HWA_DIGCTL_ROMCTRL + 0x4) #define HWT_DIGCTL_ROMCTRL_SET HWIO_32_WO #define HWN_DIGCTL_ROMCTRL_SET DIGCTL_ROMCTRL #define HWI_DIGCTL_ROMCTRL_SET #define HW_DIGCTL_ROMCTRL_CLR HW(DIGCTL_ROMCTRL_CLR) #define HWA_DIGCTL_ROMCTRL_CLR (HWA_DIGCTL_ROMCTRL + 0x8) #define HWT_DIGCTL_ROMCTRL_CLR HWIO_32_WO #define HWN_DIGCTL_ROMCTRL_CLR DIGCTL_ROMCTRL #define HWI_DIGCTL_ROMCTRL_CLR #define HW_DIGCTL_ROMCTRL_TOG HW(DIGCTL_ROMCTRL_TOG) #define HWA_DIGCTL_ROMCTRL_TOG (HWA_DIGCTL_ROMCTRL + 0xc) #define HWT_DIGCTL_ROMCTRL_TOG HWIO_32_WO #define HWN_DIGCTL_ROMCTRL_TOG DIGCTL_ROMCTRL #define HWI_DIGCTL_ROMCTRL_TOG #define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 #define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf #define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) & 0xf) << 0) #define BFM_DIGCTL_ROMCTRL_RD_MARGIN(v) BM_DIGCTL_ROMCTRL_RD_MARGIN #define BF_DIGCTL_ROMCTRL_RD_MARGIN_V(e) BF_DIGCTL_ROMCTRL_RD_MARGIN(BV_DIGCTL_ROMCTRL_RD_MARGIN__##e) #define BFM_DIGCTL_ROMCTRL_RD_MARGIN_V(v) BM_DIGCTL_ROMCTRL_RD_MARGIN #define HW_DIGCTL_WRITEONCE HW(DIGCTL_WRITEONCE) #define HWA_DIGCTL_WRITEONCE (0x8001c000 + 0x60) #define HWT_DIGCTL_WRITEONCE HWIO_32_RW #define HWN_DIGCTL_WRITEONCE DIGCTL_WRITEONCE #define HWI_DIGCTL_WRITEONCE #define BP_DIGCTL_WRITEONCE_BITS 0 #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_WRITEONCE_BITS(v) BM_DIGCTL_WRITEONCE_BITS #define BF_DIGCTL_WRITEONCE_BITS_V(e) BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e) #define BFM_DIGCTL_WRITEONCE_BITS_V(v) BM_DIGCTL_WRITEONCE_BITS #define HW_DIGCTL_ENTROPY HW(DIGCTL_ENTROPY) #define HWA_DIGCTL_ENTROPY (0x8001c000 + 0x90) #define HWT_DIGCTL_ENTROPY HWIO_32_RW #define HWN_DIGCTL_ENTROPY DIGCTL_ENTROPY #define HWI_DIGCTL_ENTROPY #define BP_DIGCTL_ENTROPY_VALUE 0 #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_ENTROPY_VALUE(v) BM_DIGCTL_ENTROPY_VALUE #define BF_DIGCTL_ENTROPY_VALUE_V(e) BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e) #define BFM_DIGCTL_ENTROPY_VALUE_V(v) BM_DIGCTL_ENTROPY_VALUE #define HW_DIGCTL_ENTROPY_LATCHED HW(DIGCTL_ENTROPY_LATCHED) #define HWA_DIGCTL_ENTROPY_LATCHED (0x8001c000 + 0xa0) #define HWT_DIGCTL_ENTROPY_LATCHED HWIO_32_RW #define HWN_DIGCTL_ENTROPY_LATCHED DIGCTL_ENTROPY_LATCHED #define HWI_DIGCTL_ENTROPY_LATCHED #define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 #define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff #define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_ENTROPY_LATCHED_VALUE(v) BM_DIGCTL_ENTROPY_LATCHED_VALUE #define BF_DIGCTL_ENTROPY_LATCHED_VALUE_V(e) BF_DIGCTL_ENTROPY_LATCHED_VALUE(BV_DIGCTL_ENTROPY_LATCHED_VALUE__##e) #define BFM_DIGCTL_ENTROPY_LATCHED_VALUE_V(v) BM_DIGCTL_ENTROPY_LATCHED_VALUE #define HW_DIGCTL_SJTAGDBG HW(DIGCTL_SJTAGDBG) #define HWA_DIGCTL_SJTAGDBG (0x8001c000 + 0xb0) #define HWT_DIGCTL_SJTAGDBG HWIO_32_RW #define HWN_DIGCTL_SJTAGDBG DIGCTL_SJTAGDBG #define HWI_DIGCTL_SJTAGDBG #define HW_DIGCTL_SJTAGDBG_SET HW(DIGCTL_SJTAGDBG_SET) #define HWA_DIGCTL_SJTAGDBG_SET (HWA_DIGCTL_SJTAGDBG + 0x4) #define HWT_DIGCTL_SJTAGDBG_SET HWIO_32_WO #define HWN_DIGCTL_SJTAGDBG_SET DIGCTL_SJTAGDBG #define HWI_DIGCTL_SJTAGDBG_SET #define HW_DIGCTL_SJTAGDBG_CLR HW(DIGCTL_SJTAGDBG_CLR) #define HWA_DIGCTL_SJTAGDBG_CLR (HWA_DIGCTL_SJTAGDBG + 0x8) #define HWT_DIGCTL_SJTAGDBG_CLR HWIO_32_WO #define HWN_DIGCTL_SJTAGDBG_CLR DIGCTL_SJTAGDBG #define HWI_DIGCTL_SJTAGDBG_CLR #define HW_DIGCTL_SJTAGDBG_TOG HW(DIGCTL_SJTAGDBG_TOG) #define HWA_DIGCTL_SJTAGDBG_TOG (HWA_DIGCTL_SJTAGDBG + 0xc) #define HWT_DIGCTL_SJTAGDBG_TOG HWIO_32_WO #define HWN_DIGCTL_SJTAGDBG_TOG DIGCTL_SJTAGDBG #define HWI_DIGCTL_SJTAGDBG_TOG #define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 #define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) & 0x7ff) << 16) #define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE(v) BM_DIGCTL_SJTAGDBG_SJTAG_STATE #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_STATE__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_STATE #define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 #define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) & 0x1) << 10) #define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDO #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_TDO(BV_DIGCTL_SJTAGDBG_SJTAG_TDO__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDO #define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 #define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) & 0x1) << 9) #define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDI #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_TDI(BV_DIGCTL_SJTAGDBG_SJTAG_TDI__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDI #define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 #define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) & 0x1) << 8) #define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE(v) BM_DIGCTL_SJTAGDBG_SJTAG_MODE #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_MODE(BV_DIGCTL_SJTAGDBG_SJTAG_MODE__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_MODE #define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 #define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) & 0xf) << 4) #define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(e) BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(BV_DIGCTL_SJTAGDBG_DELAYED_ACTIVE__##e) #define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(v) BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE #define BP_DIGCTL_SJTAGDBG_ACTIVE 3 #define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 #define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_SJTAGDBG_ACTIVE(v) BM_DIGCTL_SJTAGDBG_ACTIVE #define BF_DIGCTL_SJTAGDBG_ACTIVE_V(e) BF_DIGCTL_SJTAGDBG_ACTIVE(BV_DIGCTL_SJTAGDBG_ACTIVE__##e) #define BFM_DIGCTL_SJTAGDBG_ACTIVE_V(v) BM_DIGCTL_SJTAGDBG_ACTIVE #define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 #define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE__##e) #define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE #define HW_DIGCTL_MICROSECONDS HW(DIGCTL_MICROSECONDS) #define HWA_DIGCTL_MICROSECONDS (0x8001c000 + 0xc0) #define HWT_DIGCTL_MICROSECONDS HWIO_32_RW #define HWN_DIGCTL_MICROSECONDS DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS #define HW_DIGCTL_MICROSECONDS_SET HW(DIGCTL_MICROSECONDS_SET) #define HWA_DIGCTL_MICROSECONDS_SET (HWA_DIGCTL_MICROSECONDS + 0x4) #define HWT_DIGCTL_MICROSECONDS_SET HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_SET DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_SET #define HW_DIGCTL_MICROSECONDS_CLR HW(DIGCTL_MICROSECONDS_CLR) #define HWA_DIGCTL_MICROSECONDS_CLR (HWA_DIGCTL_MICROSECONDS + 0x8) #define HWT_DIGCTL_MICROSECONDS_CLR HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_CLR DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_CLR #define HW_DIGCTL_MICROSECONDS_TOG HW(DIGCTL_MICROSECONDS_TOG) #define HWA_DIGCTL_MICROSECONDS_TOG (HWA_DIGCTL_MICROSECONDS + 0xc) #define HWT_DIGCTL_MICROSECONDS_TOG HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_TOG DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_TOG #define BP_DIGCTL_MICROSECONDS_VALUE 0 #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_MICROSECONDS_VALUE(v) BM_DIGCTL_MICROSECONDS_VALUE #define BF_DIGCTL_MICROSECONDS_VALUE_V(e) BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e) #define BFM_DIGCTL_MICROSECONDS_VALUE_V(v) BM_DIGCTL_MICROSECONDS_VALUE #define HW_DIGCTL_DBGRD HW(DIGCTL_DBGRD) #define HWA_DIGCTL_DBGRD (0x8001c000 + 0xd0) #define HWT_DIGCTL_DBGRD HWIO_32_RW #define HWN_DIGCTL_DBGRD DIGCTL_DBGRD #define HWI_DIGCTL_DBGRD #define BP_DIGCTL_DBGRD_COMPLEMENT 0 #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DBGRD_COMPLEMENT(v) BM_DIGCTL_DBGRD_COMPLEMENT #define BF_DIGCTL_DBGRD_COMPLEMENT_V(e) BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e) #define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v) BM_DIGCTL_DBGRD_COMPLEMENT #define HW_DIGCTL_DBG HW(DIGCTL_DBG) #define HWA_DIGCTL_DBG (0x8001c000 + 0xe0) #define HWT_DIGCTL_DBG HWIO_32_RW #define HWN_DIGCTL_DBG DIGCTL_DBG #define HWI_DIGCTL_DBG #define BP_DIGCTL_DBG_VALUE 0 #define BM_DIGCTL_DBG_VALUE 0xffffffff #define BF_DIGCTL_DBG_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DBG_VALUE(v) BM_DIGCTL_DBG_VALUE #define BF_DIGCTL_DBG_VALUE_V(e) BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e) #define BFM_DIGCTL_DBG_VALUE_V(v) BM_DIGCTL_DBG_VALUE #define HW_DIGCTL_OCRAM_BIST_CSR HW(DIGCTL_OCRAM_BIST_CSR) #define HWA_DIGCTL_OCRAM_BIST_CSR (0x8001c000 + 0xf0) #define HWT_DIGCTL_OCRAM_BIST_CSR HWIO_32_RW #define HWN_DIGCTL_OCRAM_BIST_CSR DIGCTL_OCRAM_BIST_CSR #define HWI_DIGCTL_OCRAM_BIST_CSR #define HW_DIGCTL_OCRAM_BIST_CSR_SET HW(DIGCTL_OCRAM_BIST_CSR_SET) #define HWA_DIGCTL_OCRAM_BIST_CSR_SET (HWA_DIGCTL_OCRAM_BIST_CSR + 0x4) #define HWT_DIGCTL_OCRAM_BIST_CSR_SET HWIO_32_WO #define HWN_DIGCTL_OCRAM_BIST_CSR_SET DIGCTL_OCRAM_BIST_CSR #define HWI_DIGCTL_OCRAM_BIST_CSR_SET #define HW_DIGCTL_OCRAM_BIST_CSR_CLR HW(DIGCTL_OCRAM_BIST_CSR_CLR) #define HWA_DIGCTL_OCRAM_BIST_CSR_CLR (HWA_DIGCTL_OCRAM_BIST_CSR + 0x8) #define HWT_DIGCTL_OCRAM_BIST_CSR_CLR HWIO_32_WO #define HWN_DIGCTL_OCRAM_BIST_CSR_CLR DIGCTL_OCRAM_BIST_CSR #define HWI_DIGCTL_OCRAM_BIST_CSR_CLR #define HW_DIGCTL_OCRAM_BIST_CSR_TOG HW(DIGCTL_OCRAM_BIST_CSR_TOG) #define HWA_DIGCTL_OCRAM_BIST_CSR_TOG (HWA_DIGCTL_OCRAM_BIST_CSR + 0xc) #define HWT_DIGCTL_OCRAM_BIST_CSR_TOG HWIO_32_WO #define HWN_DIGCTL_OCRAM_BIST_CSR_TOG DIGCTL_OCRAM_BIST_CSR #define HWI_DIGCTL_OCRAM_BIST_CSR_TOG #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) & 0x1) << 9) #define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(e) BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) & 0x1) << 8) #define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(e) BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(BV_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN #define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 #define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL(v) BM_DIGCTL_OCRAM_BIST_CSR_FAIL #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL_V(e) BF_DIGCTL_OCRAM_BIST_CSR_FAIL(BV_DIGCTL_OCRAM_BIST_CSR_FAIL__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL_V(v) BM_DIGCTL_OCRAM_BIST_CSR_FAIL #define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 #define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 #define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_OCRAM_BIST_CSR_PASS(v) BM_DIGCTL_OCRAM_BIST_CSR_PASS #define BF_DIGCTL_OCRAM_BIST_CSR_PASS_V(e) BF_DIGCTL_OCRAM_BIST_CSR_PASS(BV_DIGCTL_OCRAM_BIST_CSR_PASS__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_PASS_V(v) BM_DIGCTL_OCRAM_BIST_CSR_PASS #define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 #define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 #define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_OCRAM_BIST_CSR_DONE(v) BM_DIGCTL_OCRAM_BIST_CSR_DONE #define BF_DIGCTL_OCRAM_BIST_CSR_DONE_V(e) BF_DIGCTL_OCRAM_BIST_CSR_DONE(BV_DIGCTL_OCRAM_BIST_CSR_DONE__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_DONE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_DONE #define BP_DIGCTL_OCRAM_BIST_CSR_START 0 #define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 #define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_OCRAM_BIST_CSR_START(v) BM_DIGCTL_OCRAM_BIST_CSR_START #define BF_DIGCTL_OCRAM_BIST_CSR_START_V(e) BF_DIGCTL_OCRAM_BIST_CSR_START(BV_DIGCTL_OCRAM_BIST_CSR_START__##e) #define BFM_DIGCTL_OCRAM_BIST_CSR_START_V(v) BM_DIGCTL_OCRAM_BIST_CSR_START #define HW_DIGCTL_OCRAM_STATUS0 HW(DIGCTL_OCRAM_STATUS0) #define HWA_DIGCTL_OCRAM_STATUS0 (0x8001c000 + 0x110) #define HWT_DIGCTL_OCRAM_STATUS0 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS0 DIGCTL_OCRAM_STATUS0 #define HWI_DIGCTL_OCRAM_STATUS0 #define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 #define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(e) BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(BV_DIGCTL_OCRAM_STATUS0_FAILDATA00__##e) #define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(v) BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 #define HW_DIGCTL_OCRAM_STATUS1 HW(DIGCTL_OCRAM_STATUS1) #define HWA_DIGCTL_OCRAM_STATUS1 (0x8001c000 + 0x120) #define HWT_DIGCTL_OCRAM_STATUS1 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS1 DIGCTL_OCRAM_STATUS1 #define HWI_DIGCTL_OCRAM_STATUS1 #define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 #define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(e) BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(BV_DIGCTL_OCRAM_STATUS1_FAILDATA01__##e) #define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(v) BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 #define HW_DIGCTL_OCRAM_STATUS2 HW(DIGCTL_OCRAM_STATUS2) #define HWA_DIGCTL_OCRAM_STATUS2 (0x8001c000 + 0x130) #define HWT_DIGCTL_OCRAM_STATUS2 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS2 DIGCTL_OCRAM_STATUS2 #define HWI_DIGCTL_OCRAM_STATUS2 #define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 #define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(e) BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(BV_DIGCTL_OCRAM_STATUS2_FAILDATA10__##e) #define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(v) BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 #define HW_DIGCTL_OCRAM_STATUS3 HW(DIGCTL_OCRAM_STATUS3) #define HWA_DIGCTL_OCRAM_STATUS3 (0x8001c000 + 0x140) #define HWT_DIGCTL_OCRAM_STATUS3 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS3 DIGCTL_OCRAM_STATUS3 #define HWI_DIGCTL_OCRAM_STATUS3 #define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 #define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(e) BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(BV_DIGCTL_OCRAM_STATUS3_FAILDATA11__##e) #define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(v) BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 #define HW_DIGCTL_OCRAM_STATUS4 HW(DIGCTL_OCRAM_STATUS4) #define HWA_DIGCTL_OCRAM_STATUS4 (0x8001c000 + 0x150) #define HWT_DIGCTL_OCRAM_STATUS4 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS4 DIGCTL_OCRAM_STATUS4 #define HWI_DIGCTL_OCRAM_STATUS4 #define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 #define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(e) BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(BV_DIGCTL_OCRAM_STATUS4_FAILDATA20__##e) #define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(v) BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 #define HW_DIGCTL_OCRAM_STATUS5 HW(DIGCTL_OCRAM_STATUS5) #define HWA_DIGCTL_OCRAM_STATUS5 (0x8001c000 + 0x160) #define HWT_DIGCTL_OCRAM_STATUS5 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS5 DIGCTL_OCRAM_STATUS5 #define HWI_DIGCTL_OCRAM_STATUS5 #define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 #define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(e) BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(BV_DIGCTL_OCRAM_STATUS5_FAILDATA21__##e) #define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(v) BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 #define HW_DIGCTL_OCRAM_STATUS6 HW(DIGCTL_OCRAM_STATUS6) #define HWA_DIGCTL_OCRAM_STATUS6 (0x8001c000 + 0x170) #define HWT_DIGCTL_OCRAM_STATUS6 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS6 DIGCTL_OCRAM_STATUS6 #define HWI_DIGCTL_OCRAM_STATUS6 #define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 #define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(e) BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(BV_DIGCTL_OCRAM_STATUS6_FAILDATA30__##e) #define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(v) BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 #define HW_DIGCTL_OCRAM_STATUS7 HW(DIGCTL_OCRAM_STATUS7) #define HWA_DIGCTL_OCRAM_STATUS7 (0x8001c000 + 0x180) #define HWT_DIGCTL_OCRAM_STATUS7 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS7 DIGCTL_OCRAM_STATUS7 #define HWI_DIGCTL_OCRAM_STATUS7 #define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 #define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(e) BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(BV_DIGCTL_OCRAM_STATUS7_FAILDATA31__##e) #define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(v) BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 #define HW_DIGCTL_OCRAM_STATUS8 HW(DIGCTL_OCRAM_STATUS8) #define HWA_DIGCTL_OCRAM_STATUS8 (0x8001c000 + 0x190) #define HWT_DIGCTL_OCRAM_STATUS8 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS8 DIGCTL_OCRAM_STATUS8 #define HWI_DIGCTL_OCRAM_STATUS8 #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xffff0000 #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(e) BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(BV_DIGCTL_OCRAM_STATUS8_FAILADDR01__##e) #define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0xffff #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(e) BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(BV_DIGCTL_OCRAM_STATUS8_FAILADDR00__##e) #define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 #define HW_DIGCTL_OCRAM_STATUS9 HW(DIGCTL_OCRAM_STATUS9) #define HWA_DIGCTL_OCRAM_STATUS9 (0x8001c000 + 0x1a0) #define HWT_DIGCTL_OCRAM_STATUS9 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS9 DIGCTL_OCRAM_STATUS9 #define HWI_DIGCTL_OCRAM_STATUS9 #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xffff0000 #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(e) BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(BV_DIGCTL_OCRAM_STATUS9_FAILADDR11__##e) #define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0xffff #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(e) BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(BV_DIGCTL_OCRAM_STATUS9_FAILADDR10__##e) #define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 #define HW_DIGCTL_OCRAM_STATUS10 HW(DIGCTL_OCRAM_STATUS10) #define HWA_DIGCTL_OCRAM_STATUS10 (0x8001c000 + 0x1b0) #define HWT_DIGCTL_OCRAM_STATUS10 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS10 DIGCTL_OCRAM_STATUS10 #define HWI_DIGCTL_OCRAM_STATUS10 #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xffff0000 #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(e) BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(BV_DIGCTL_OCRAM_STATUS10_FAILADDR21__##e) #define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0xffff #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(e) BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(BV_DIGCTL_OCRAM_STATUS10_FAILADDR20__##e) #define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 #define HW_DIGCTL_OCRAM_STATUS11 HW(DIGCTL_OCRAM_STATUS11) #define HWA_DIGCTL_OCRAM_STATUS11 (0x8001c000 + 0x1c0) #define HWT_DIGCTL_OCRAM_STATUS11 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS11 DIGCTL_OCRAM_STATUS11 #define HWI_DIGCTL_OCRAM_STATUS11 #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xffff0000 #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(e) BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(BV_DIGCTL_OCRAM_STATUS11_FAILADDR31__##e) #define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0xffff #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(e) BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(BV_DIGCTL_OCRAM_STATUS11_FAILADDR30__##e) #define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 #define HW_DIGCTL_OCRAM_STATUS12 HW(DIGCTL_OCRAM_STATUS12) #define HWA_DIGCTL_OCRAM_STATUS12 (0x8001c000 + 0x1d0) #define HWT_DIGCTL_OCRAM_STATUS12 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS12 DIGCTL_OCRAM_STATUS12 #define HWI_DIGCTL_OCRAM_STATUS12 #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x1f000000 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) & 0x1f) << 24) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE11__##e) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x1f0000 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) & 0x1f) << 16) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE10__##e) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x1f00 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) & 0x1f) << 8) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE01__##e) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x1f #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) & 0x1f) << 0) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE00__##e) #define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 #define HW_DIGCTL_OCRAM_STATUS13 HW(DIGCTL_OCRAM_STATUS13) #define HWA_DIGCTL_OCRAM_STATUS13 (0x8001c000 + 0x1e0) #define HWT_DIGCTL_OCRAM_STATUS13 HWIO_32_RW #define HWN_DIGCTL_OCRAM_STATUS13 DIGCTL_OCRAM_STATUS13 #define HWI_DIGCTL_OCRAM_STATUS13 #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x1f000000 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) & 0x1f) << 24) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE31__##e) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x1f0000 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) & 0x1f) << 16) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE30__##e) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x1f00 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) & 0x1f) << 8) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE21__##e) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x1f #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) & 0x1f) << 0) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE20__##e) #define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 #define HW_DIGCTL_SCRATCH0 HW(DIGCTL_SCRATCH0) #define HWA_DIGCTL_SCRATCH0 (0x8001c000 + 0x290) #define HWT_DIGCTL_SCRATCH0 HWIO_32_RW #define HWN_DIGCTL_SCRATCH0 DIGCTL_SCRATCH0 #define HWI_DIGCTL_SCRATCH0 #define BP_DIGCTL_SCRATCH0_PTR 0 #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SCRATCH0_PTR(v) BM_DIGCTL_SCRATCH0_PTR #define BF_DIGCTL_SCRATCH0_PTR_V(e) BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e) #define BFM_DIGCTL_SCRATCH0_PTR_V(v) BM_DIGCTL_SCRATCH0_PTR #define HW_DIGCTL_SCRATCH1 HW(DIGCTL_SCRATCH1) #define HWA_DIGCTL_SCRATCH1 (0x8001c000 + 0x2a0) #define HWT_DIGCTL_SCRATCH1 HWIO_32_RW #define HWN_DIGCTL_SCRATCH1 DIGCTL_SCRATCH1 #define HWI_DIGCTL_SCRATCH1 #define BP_DIGCTL_SCRATCH1_PTR 0 #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SCRATCH1_PTR(v) BM_DIGCTL_SCRATCH1_PTR #define BF_DIGCTL_SCRATCH1_PTR_V(e) BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e) #define BFM_DIGCTL_SCRATCH1_PTR_V(v) BM_DIGCTL_SCRATCH1_PTR #define HW_DIGCTL_ARMCACHE HW(DIGCTL_ARMCACHE) #define HWA_DIGCTL_ARMCACHE (0x8001c000 + 0x2b0) #define HWT_DIGCTL_ARMCACHE HWIO_32_RW #define HWN_DIGCTL_ARMCACHE DIGCTL_ARMCACHE #define HWI_DIGCTL_ARMCACHE #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) & 0x3) << 8) #define BFM_DIGCTL_ARMCACHE_CACHE_SS(v) BM_DIGCTL_ARMCACHE_CACHE_SS #define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e) BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e) #define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v) BM_DIGCTL_ARMCACHE_CACHE_SS #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) & 0x3) << 4) #define BFM_DIGCTL_ARMCACHE_DTAG_SS(v) BM_DIGCTL_ARMCACHE_DTAG_SS #define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e) BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e) #define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v) BM_DIGCTL_ARMCACHE_DTAG_SS #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) & 0x3) << 0) #define BFM_DIGCTL_ARMCACHE_ITAG_SS(v) BM_DIGCTL_ARMCACHE_ITAG_SS #define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e) BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e) #define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v) BM_DIGCTL_ARMCACHE_ITAG_SS #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW HW(DIGCTL_DEBUG_TRAP_ADDR_LOW) #define HWA_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x8001c000 + 0x2c0) #define HWT_DIGCTL_DEBUG_TRAP_ADDR_LOW HWIO_32_RW #define HWN_DIGCTL_DEBUG_TRAP_ADDR_LOW DIGCTL_DEBUG_TRAP_ADDR_LOW #define HWI_DIGCTL_DEBUG_TRAP_ADDR_LOW #define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 #define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(e) BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR__##e) #define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(v) BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH HW(DIGCTL_DEBUG_TRAP_ADDR_HIGH) #define HWA_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x8001c000 + 0x2d0) #define HWT_DIGCTL_DEBUG_TRAP_ADDR_HIGH HWIO_32_RW #define HWN_DIGCTL_DEBUG_TRAP_ADDR_HIGH DIGCTL_DEBUG_TRAP_ADDR_HIGH #define HWI_DIGCTL_DEBUG_TRAP_ADDR_HIGH #define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 #define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(e) BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR__##e) #define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(v) BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR #define HW_DIGCTL_SGTL HW(DIGCTL_SGTL) #define HWA_DIGCTL_SGTL (0x8001c000 + 0x300) #define HWT_DIGCTL_SGTL HWIO_32_RW #define HWN_DIGCTL_SGTL DIGCTL_SGTL #define HWI_DIGCTL_SGTL #define BP_DIGCTL_SGTL_COPYRIGHT 0 #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SGTL_COPYRIGHT(v) BM_DIGCTL_SGTL_COPYRIGHT #define BF_DIGCTL_SGTL_COPYRIGHT_V(e) BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e) #define BFM_DIGCTL_SGTL_COPYRIGHT_V(v) BM_DIGCTL_SGTL_COPYRIGHT #define HW_DIGCTL_CHIPID HW(DIGCTL_CHIPID) #define HWA_DIGCTL_CHIPID (0x8001c000 + 0x310) #define HWT_DIGCTL_CHIPID HWIO_32_RW #define HWN_DIGCTL_CHIPID DIGCTL_CHIPID #define HWI_DIGCTL_CHIPID #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v) BM_DIGCTL_CHIPID_PRODUCT_CODE #define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e) BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e) #define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE #define BP_DIGCTL_CHIPID_REVISION 0 #define BM_DIGCTL_CHIPID_REVISION 0xff #define BF_DIGCTL_CHIPID_REVISION(v) (((v) & 0xff) << 0) #define BFM_DIGCTL_CHIPID_REVISION(v) BM_DIGCTL_CHIPID_REVISION #define BF_DIGCTL_CHIPID_REVISION_V(e) BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e) #define BFM_DIGCTL_CHIPID_REVISION_V(v) BM_DIGCTL_CHIPID_REVISION #define HW_DIGCTL_AHB_STATS_SELECT HW(DIGCTL_AHB_STATS_SELECT) #define HWA_DIGCTL_AHB_STATS_SELECT (0x8001c000 + 0x330) #define HWT_DIGCTL_AHB_STATS_SELECT HWIO_32_RW #define HWN_DIGCTL_AHB_STATS_SELECT DIGCTL_AHB_STATS_SELECT #define HWI_DIGCTL_AHB_STATS_SELECT #define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 #define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) & 0xf) << 24) #define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##e) #define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT #define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 #define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 #define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) & 0xf) << 16) #define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##e) #define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT #define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 #define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 #define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) & 0xf) << 8) #define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##e) #define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT #define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 #define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) & 0xf) << 0) #define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##e) #define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW(DIGCTL_L0_AHB_ACTIVE_CYCLES) #define HWA_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x8001c000 + 0x340) #define HWT_DIGCTL_L0_AHB_ACTIVE_CYCLES HWIO_32_RW #define HWN_DIGCTL_L0_AHB_ACTIVE_CYCLES DIGCTL_L0_AHB_ACTIVE_CYCLES #define HWI_DIGCTL_L0_AHB_ACTIVE_CYCLES #define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 #define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT__##e) #define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT #define HW_DIGCTL_L0_AHB_DATA_STALLED HW(DIGCTL_L0_AHB_DATA_STALLED) #define HWA_DIGCTL_L0_AHB_DATA_STALLED (0x8001c000 + 0x350) #define HWT_DIGCTL_L0_AHB_DATA_STALLED HWIO_32_RW #define HWN_DIGCTL_L0_AHB_DATA_STALLED DIGCTL_L0_AHB_DATA_STALLED #define HWI_DIGCTL_L0_AHB_DATA_STALLED #define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 #define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L0_AHB_DATA_STALLED_COUNT__##e) #define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT #define HW_DIGCTL_L0_AHB_DATA_CYCLES HW(DIGCTL_L0_AHB_DATA_CYCLES) #define HWA_DIGCTL_L0_AHB_DATA_CYCLES (0x8001c000 + 0x360) #define HWT_DIGCTL_L0_AHB_DATA_CYCLES HWIO_32_RW #define HWN_DIGCTL_L0_AHB_DATA_CYCLES DIGCTL_L0_AHB_DATA_CYCLES #define HWI_DIGCTL_L0_AHB_DATA_CYCLES #define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 #define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L0_AHB_DATA_CYCLES_COUNT__##e) #define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES HW(DIGCTL_L1_AHB_ACTIVE_CYCLES) #define HWA_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x8001c000 + 0x370) #define HWT_DIGCTL_L1_AHB_ACTIVE_CYCLES HWIO_32_RW #define HWN_DIGCTL_L1_AHB_ACTIVE_CYCLES DIGCTL_L1_AHB_ACTIVE_CYCLES #define HWI_DIGCTL_L1_AHB_ACTIVE_CYCLES #define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 #define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT__##e) #define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT #define HW_DIGCTL_L1_AHB_DATA_STALLED HW(DIGCTL_L1_AHB_DATA_STALLED) #define HWA_DIGCTL_L1_AHB_DATA_STALLED (0x8001c000 + 0x380) #define HWT_DIGCTL_L1_AHB_DATA_STALLED HWIO_32_RW #define HWN_DIGCTL_L1_AHB_DATA_STALLED DIGCTL_L1_AHB_DATA_STALLED #define HWI_DIGCTL_L1_AHB_DATA_STALLED #define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 #define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L1_AHB_DATA_STALLED_COUNT__##e) #define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT #define HW_DIGCTL_L1_AHB_DATA_CYCLES HW(DIGCTL_L1_AHB_DATA_CYCLES) #define HWA_DIGCTL_L1_AHB_DATA_CYCLES (0x8001c000 + 0x390) #define HWT_DIGCTL_L1_AHB_DATA_CYCLES HWIO_32_RW #define HWN_DIGCTL_L1_AHB_DATA_CYCLES DIGCTL_L1_AHB_DATA_CYCLES #define HWI_DIGCTL_L1_AHB_DATA_CYCLES #define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 #define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L1_AHB_DATA_CYCLES_COUNT__##e) #define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES HW(DIGCTL_L2_AHB_ACTIVE_CYCLES) #define HWA_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x8001c000 + 0x3a0) #define HWT_DIGCTL_L2_AHB_ACTIVE_CYCLES HWIO_32_RW #define HWN_DIGCTL_L2_AHB_ACTIVE_CYCLES DIGCTL_L2_AHB_ACTIVE_CYCLES #define HWI_DIGCTL_L2_AHB_ACTIVE_CYCLES #define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 #define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT__##e) #define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT #define HW_DIGCTL_L2_AHB_DATA_STALLED HW(DIGCTL_L2_AHB_DATA_STALLED) #define HWA_DIGCTL_L2_AHB_DATA_STALLED (0x8001c000 + 0x3b0) #define HWT_DIGCTL_L2_AHB_DATA_STALLED HWIO_32_RW #define HWN_DIGCTL_L2_AHB_DATA_STALLED DIGCTL_L2_AHB_DATA_STALLED #define HWI_DIGCTL_L2_AHB_DATA_STALLED #define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 #define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L2_AHB_DATA_STALLED_COUNT__##e) #define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT #define HW_DIGCTL_L2_AHB_DATA_CYCLES HW(DIGCTL_L2_AHB_DATA_CYCLES) #define HWA_DIGCTL_L2_AHB_DATA_CYCLES (0x8001c000 + 0x3c0) #define HWT_DIGCTL_L2_AHB_DATA_CYCLES HWIO_32_RW #define HWN_DIGCTL_L2_AHB_DATA_CYCLES DIGCTL_L2_AHB_DATA_CYCLES #define HWI_DIGCTL_L2_AHB_DATA_CYCLES #define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 #define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L2_AHB_DATA_CYCLES_COUNT__##e) #define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES HW(DIGCTL_L3_AHB_ACTIVE_CYCLES) #define HWA_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x8001c000 + 0x3d0) #define HWT_DIGCTL_L3_AHB_ACTIVE_CYCLES HWIO_32_RW #define HWN_DIGCTL_L3_AHB_ACTIVE_CYCLES DIGCTL_L3_AHB_ACTIVE_CYCLES #define HWI_DIGCTL_L3_AHB_ACTIVE_CYCLES #define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 #define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT__##e) #define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT #define HW_DIGCTL_L3_AHB_DATA_STALLED HW(DIGCTL_L3_AHB_DATA_STALLED) #define HWA_DIGCTL_L3_AHB_DATA_STALLED (0x8001c000 + 0x3e0) #define HWT_DIGCTL_L3_AHB_DATA_STALLED HWIO_32_RW #define HWN_DIGCTL_L3_AHB_DATA_STALLED DIGCTL_L3_AHB_DATA_STALLED #define HWI_DIGCTL_L3_AHB_DATA_STALLED #define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 #define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L3_AHB_DATA_STALLED_COUNT__##e) #define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT #define HW_DIGCTL_L3_AHB_DATA_CYCLES HW(DIGCTL_L3_AHB_DATA_CYCLES) #define HWA_DIGCTL_L3_AHB_DATA_CYCLES (0x8001c000 + 0x3f0) #define HWT_DIGCTL_L3_AHB_DATA_CYCLES HWIO_32_RW #define HWN_DIGCTL_L3_AHB_DATA_CYCLES DIGCTL_L3_AHB_DATA_CYCLES #define HWI_DIGCTL_L3_AHB_DATA_CYCLES #define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 #define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L3_AHB_DATA_CYCLES_COUNT__##e) #define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT #define HW_DIGCTL_MPTEn_LOC(_n1) HW(DIGCTL_MPTEn_LOC(_n1)) #define HWA_DIGCTL_MPTEn_LOC(_n1) (0x8001c000 + 0x400 + (_n1) * 0x10) #define HWT_DIGCTL_MPTEn_LOC(_n1) HWIO_32_RW #define HWN_DIGCTL_MPTEn_LOC(_n1) DIGCTL_MPTEn_LOC #define HWI_DIGCTL_MPTEn_LOC(_n1) (_n1) #define BP_DIGCTL_MPTEn_LOC_LOC 0 #define BM_DIGCTL_MPTEn_LOC_LOC 0xfff #define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) & 0xfff) << 0) #define BFM_DIGCTL_MPTEn_LOC_LOC(v) BM_DIGCTL_MPTEn_LOC_LOC #define BF_DIGCTL_MPTEn_LOC_LOC_V(e) BF_DIGCTL_MPTEn_LOC_LOC(BV_DIGCTL_MPTEn_LOC_LOC__##e) #define BFM_DIGCTL_MPTEn_LOC_LOC_V(v) BM_DIGCTL_MPTEn_LOC_LOC #define HW_DIGCTL_EMICLK_DELAY HW(DIGCTL_EMICLK_DELAY) #define HWA_DIGCTL_EMICLK_DELAY (0x8001c000 + 0x480) #define HWT_DIGCTL_EMICLK_DELAY HWIO_32_RW #define HWN_DIGCTL_EMICLK_DELAY DIGCTL_EMICLK_DELAY #define HWI_DIGCTL_EMICLK_DELAY #define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 #define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) & 0x1f) << 0) #define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) BM_DIGCTL_EMICLK_DELAY_NUM_TAPS #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(e) BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(BV_DIGCTL_EMICLK_DELAY_NUM_TAPS__##e) #define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(v) BM_DIGCTL_EMICLK_DELAY_NUM_TAPS #endif /* __HEADERGEN_STMP3700_DIGCTL_H__*/