/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * x1000 version: 1.0 * x1000 authors: Aidan MacDonald * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_TCU_H__ #define __HEADERGEN_TCU_H__ #include "macro.h" #define REG_TCU_STATUS jz_reg(TCU_STATUS) #define JA_TCU_STATUS (0xb0002000 + 0xf0) #define JT_TCU_STATUS JIO_32_RW #define JN_TCU_STATUS TCU_STATUS #define JI_TCU_STATUS #define REG_TCU_STATUS_SET jz_reg(TCU_STATUS_SET) #define JA_TCU_STATUS_SET (JA_TCU_STATUS + 0x4) #define JT_TCU_STATUS_SET JIO_32_WO #define JN_TCU_STATUS_SET TCU_STATUS #define JI_TCU_STATUS_SET #define REG_TCU_STATUS_CLR jz_reg(TCU_STATUS_CLR) #define JA_TCU_STATUS_CLR (JA_TCU_STATUS + 0x8) #define JT_TCU_STATUS_CLR JIO_32_WO #define JN_TCU_STATUS_CLR TCU_STATUS #define JI_TCU_STATUS_CLR #define REG_TCU_STOP jz_reg(TCU_STOP) #define JA_TCU_STOP (0xb0002000 + 0x1c) #define JT_TCU_STOP JIO_32_RW #define JN_TCU_STOP TCU_STOP #define JI_TCU_STOP #define REG_TCU_STOP_SET jz_reg(TCU_STOP_SET) #define JA_TCU_STOP_SET (JA_TCU_STOP + 0x10) #define JT_TCU_STOP_SET JIO_32_WO #define JN_TCU_STOP_SET TCU_STOP #define JI_TCU_STOP_SET #define REG_TCU_STOP_CLR jz_reg(TCU_STOP_CLR) #define JA_TCU_STOP_CLR (JA_TCU_STOP + 0x20) #define JT_TCU_STOP_CLR JIO_32_WO #define JN_TCU_STOP_CLR TCU_STOP #define JI_TCU_STOP_CLR #define REG_TCU_ENABLE jz_reg(TCU_ENABLE) #define JA_TCU_ENABLE (0xb0002000 + 0x10) #define JT_TCU_ENABLE JIO_32_RW #define JN_TCU_ENABLE TCU_ENABLE #define JI_TCU_ENABLE #define REG_TCU_ENABLE_SET jz_reg(TCU_ENABLE_SET) #define JA_TCU_ENABLE_SET (JA_TCU_ENABLE + 0x4) #define JT_TCU_ENABLE_SET JIO_32_WO #define JN_TCU_ENABLE_SET TCU_ENABLE #define JI_TCU_ENABLE_SET #define REG_TCU_ENABLE_CLR jz_reg(TCU_ENABLE_CLR) #define JA_TCU_ENABLE_CLR (JA_TCU_ENABLE + 0x8) #define JT_TCU_ENABLE_CLR JIO_32_WO #define JN_TCU_ENABLE_CLR TCU_ENABLE #define JI_TCU_ENABLE_CLR #define REG_TCU_FLAG jz_reg(TCU_FLAG) #define JA_TCU_FLAG (0xb0002000 + 0x20) #define JT_TCU_FLAG JIO_32_RW #define JN_TCU_FLAG TCU_FLAG #define JI_TCU_FLAG #define REG_TCU_FLAG_SET jz_reg(TCU_FLAG_SET) #define JA_TCU_FLAG_SET (JA_TCU_FLAG + 0x4) #define JT_TCU_FLAG_SET JIO_32_WO #define JN_TCU_FLAG_SET TCU_FLAG #define JI_TCU_FLAG_SET #define REG_TCU_FLAG_CLR jz_reg(TCU_FLAG_CLR) #define JA_TCU_FLAG_CLR (JA_TCU_FLAG + 0x8) #define JT_TCU_FLAG_CLR JIO_32_WO #define JN_TCU_FLAG_CLR TCU_FLAG #define JI_TCU_FLAG_CLR #define REG_TCU_MASK jz_reg(TCU_MASK) #define JA_TCU_MASK (0xb0002000 + 0x30) #define JT_TCU_MASK JIO_32_RW #define JN_TCU_MASK TCU_MASK #define JI_TCU_MASK #define REG_TCU_MASK_SET jz_reg(TCU_MASK_SET) #define JA_TCU_MASK_SET (JA_TCU_MASK + 0x4) #define JT_TCU_MASK_SET JIO_32_WO #define JN_TCU_MASK_SET TCU_MASK #define JI_TCU_MASK_SET #define REG_TCU_MASK_CLR jz_reg(TCU_MASK_CLR) #define JA_TCU_MASK_CLR (JA_TCU_MASK + 0x8) #define JT_TCU_MASK_CLR JIO_32_WO #define JN_TCU_MASK_CLR TCU_MASK #define JI_TCU_MASK_CLR #define REG_TCU_CMP_FULL(_n1) jz_reg(TCU_CMP_FULL(_n1)) #define JA_TCU_CMP_FULL(_n1) (0xb0002000 + 0x40 + (_n1) * 0x10) #define JT_TCU_CMP_FULL(_n1) JIO_32_RW #define JN_TCU_CMP_FULL(_n1) TCU_CMP_FULL #define JI_TCU_CMP_FULL(_n1) (_n1) #define REG_TCU_CMP_HALF(_n1) jz_reg(TCU_CMP_HALF(_n1)) #define JA_TCU_CMP_HALF(_n1) (0xb0002000 + 0x44 + (_n1) * 0x10) #define JT_TCU_CMP_HALF(_n1) JIO_32_RW #define JN_TCU_CMP_HALF(_n1) TCU_CMP_HALF #define JI_TCU_CMP_HALF(_n1) (_n1) #define REG_TCU_COUNT(_n1) jz_reg(TCU_COUNT(_n1)) #define JA_TCU_COUNT(_n1) (0xb0002000 + 0x48 + (_n1) * 0x10) #define JT_TCU_COUNT(_n1) JIO_32_RW #define JN_TCU_COUNT(_n1) TCU_COUNT #define JI_TCU_COUNT(_n1) (_n1) #define REG_TCU_CTRL(_n1) jz_reg(TCU_CTRL(_n1)) #define JA_TCU_CTRL(_n1) (0xb0002000 + 0x4c + (_n1) * 0x10) #define JT_TCU_CTRL(_n1) JIO_32_RW #define JN_TCU_CTRL(_n1) TCU_CTRL #define JI_TCU_CTRL(_n1) (_n1) #define BP_TCU_CTRL_PRESCALE 3 #define BM_TCU_CTRL_PRESCALE 0x38 #define BV_TCU_CTRL_PRESCALE__BY_1 0x0 #define BV_TCU_CTRL_PRESCALE__BY_4 0x1 #define BV_TCU_CTRL_PRESCALE__BY_16 0x2 #define BV_TCU_CTRL_PRESCALE__BY_64 0x3 #define BV_TCU_CTRL_PRESCALE__BY_256 0x4 #define BV_TCU_CTRL_PRESCALE__BY_1024 0x5 #define BF_TCU_CTRL_PRESCALE(v) (((v) & 0x7) << 3) #define BFM_TCU_CTRL_PRESCALE(v) BM_TCU_CTRL_PRESCALE #define BF_TCU_CTRL_PRESCALE_V(e) BF_TCU_CTRL_PRESCALE(BV_TCU_CTRL_PRESCALE__##e) #define BFM_TCU_CTRL_PRESCALE_V(v) BM_TCU_CTRL_PRESCALE #define BP_TCU_CTRL_SOURCE 0 #define BM_TCU_CTRL_SOURCE 0x7 #define BV_TCU_CTRL_SOURCE__EXT 0x4 #define BV_TCU_CTRL_SOURCE__RTC 0x2 #define BV_TCU_CTRL_SOURCE__PCLK 0x1 #define BF_TCU_CTRL_SOURCE(v) (((v) & 0x7) << 0) #define BFM_TCU_CTRL_SOURCE(v) BM_TCU_CTRL_SOURCE #define BF_TCU_CTRL_SOURCE_V(e) BF_TCU_CTRL_SOURCE(BV_TCU_CTRL_SOURCE__##e) #define BFM_TCU_CTRL_SOURCE_V(v) BM_TCU_CTRL_SOURCE #define BP_TCU_CTRL_BYPASS 11 #define BM_TCU_CTRL_BYPASS 0x800 #define BF_TCU_CTRL_BYPASS(v) (((v) & 0x1) << 11) #define BFM_TCU_CTRL_BYPASS(v) BM_TCU_CTRL_BYPASS #define BF_TCU_CTRL_BYPASS_V(e) BF_TCU_CTRL_BYPASS(BV_TCU_CTRL_BYPASS__##e) #define BFM_TCU_CTRL_BYPASS_V(v) BM_TCU_CTRL_BYPASS #define BP_TCU_CTRL_CLRZ 10 #define BM_TCU_CTRL_CLRZ 0x400 #define BF_TCU_CTRL_CLRZ(v) (((v) & 0x1) << 10) #define BFM_TCU_CTRL_CLRZ(v) BM_TCU_CTRL_CLRZ #define BF_TCU_CTRL_CLRZ_V(e) BF_TCU_CTRL_CLRZ(BV_TCU_CTRL_CLRZ__##e) #define BFM_TCU_CTRL_CLRZ_V(v) BM_TCU_CTRL_CLRZ #define BP_TCU_CTRL_SHUTDOWN 9 #define BM_TCU_CTRL_SHUTDOWN 0x200 #define BV_TCU_CTRL_SHUTDOWN__GRACEFUL 0x0 #define BV_TCU_CTRL_SHUTDOWN__ABRUPT 0x1 #define BF_TCU_CTRL_SHUTDOWN(v) (((v) & 0x1) << 9) #define BFM_TCU_CTRL_SHUTDOWN(v) BM_TCU_CTRL_SHUTDOWN #define BF_TCU_CTRL_SHUTDOWN_V(e) BF_TCU_CTRL_SHUTDOWN(BV_TCU_CTRL_SHUTDOWN__##e) #define BFM_TCU_CTRL_SHUTDOWN_V(v) BM_TCU_CTRL_SHUTDOWN #define BP_TCU_CTRL_INIT_LVL 8 #define BM_TCU_CTRL_INIT_LVL 0x100 #define BF_TCU_CTRL_INIT_LVL(v) (((v) & 0x1) << 8) #define BFM_TCU_CTRL_INIT_LVL(v) BM_TCU_CTRL_INIT_LVL #define BF_TCU_CTRL_INIT_LVL_V(e) BF_TCU_CTRL_INIT_LVL(BV_TCU_CTRL_INIT_LVL__##e) #define BFM_TCU_CTRL_INIT_LVL_V(v) BM_TCU_CTRL_INIT_LVL #define BP_TCU_CTRL_PWM_EN 7 #define BM_TCU_CTRL_PWM_EN 0x80 #define BF_TCU_CTRL_PWM_EN(v) (((v) & 0x1) << 7) #define BFM_TCU_CTRL_PWM_EN(v) BM_TCU_CTRL_PWM_EN #define BF_TCU_CTRL_PWM_EN_V(e) BF_TCU_CTRL_PWM_EN(BV_TCU_CTRL_PWM_EN__##e) #define BFM_TCU_CTRL_PWM_EN_V(v) BM_TCU_CTRL_PWM_EN #define BP_TCU_CTRL_PWM_IN_EN 6 #define BM_TCU_CTRL_PWM_IN_EN 0x40 #define BF_TCU_CTRL_PWM_IN_EN(v) (((v) & 0x1) << 6) #define BFM_TCU_CTRL_PWM_IN_EN(v) BM_TCU_CTRL_PWM_IN_EN #define BF_TCU_CTRL_PWM_IN_EN_V(e) BF_TCU_CTRL_PWM_IN_EN(BV_TCU_CTRL_PWM_IN_EN__##e) #define BFM_TCU_CTRL_PWM_IN_EN_V(v) BM_TCU_CTRL_PWM_IN_EN #endif /* __HEADERGEN_TCU_H__*/