stmp3600
STMP3600
Amaury Pouly
2.4.0
ANATOP
Analog TOP
Analog TOP
ANATOP
0x8003c200
PROBE_OUTPUT_SELECT
PROBE_OUTPUT_SELECT
0x0
OUTPUT_SELECT
0
32
set
4
clr
8
tog
12
PROBE_INPUT_SELECT
PROBE_INPUT_SELECT
0x10
INPUT_SELECT
0
32
set
4
clr
8
tog
12
PROBE_DATA
PROBE_DATA
0x20
DATA
0
32
set
4
clr
8
tog
12
PROBE_DIGTOP_SELECT
PROBE_DIGTOP_SELECT
0x30
DIGTOP_SELECT
0
32
set
4
clr
8
tog
12
APBH
APHB DMA
AHB-to-APBH Bridge with DMA
APBH
0x80004000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RESET_CHANNEL
16
8
HWECC
0x1
SSP
0x2
SRC
0x4
DEST
0x8
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x30
NAND3
0x40
CLKGATE_CHANNEL
8
8
HWECC
0x1
SSP
0x2
SRC
0x4
DEST
0x8
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x30
NAND3
0x40
FREEZE_CHANNEL
0
8
HWECC
0x1
SSP
0x2
SRC
0x4
DEST
0x8
ATA
0x10
NAND0
0x10
NAND1
0x20
NAND2
0x30
NAND3
0x40
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
CH_CMDCMPLT_IRQ_EN
16
8
CH_CMDCMPLT_IRQ
0
8
set
4
clr
8
tog
12
DEVSEL
DEVSEL
0x20
CH7
28
4
CH6
24
4
CH5
20
4
CH4
16
4
CH3
12
4
CH2
8
4
CH1
4
4
CH0
0
4
CHn_DEBUG2
CHn_DEBUG2
0
8
0x90
0x70
APB_BYTES
16
16
AHB_BYTES
0
16
CHn_CURCMDAR
CHn_CURCMDAR
0
8
0x30
0x70
CMD_ADDR
0
32
CHn_BAR
CHn_BAR
0
8
0x60
0x70
ADDRESS
0
32
CHn_CMD
CHn_CMD
0
8
0x50
0x70
XFER_COUNT
16
16
CMDWORDS
12
4
WAIT4ENDCMD
7
SEMAPHORE
6
NANDWAIT4READY
5
NANDLOCK
4
IRQONCMPLT
3
CHAIN
2
COMMAND
0
2
NO_DMA_XFER
0x0
DMA_WRITE
0x1
DMA_READ
0x2
DMA_SENSE
0x3
CHn_NXTCMDAR
CHn_NXTCMDAR
0
8
0x40
0x70
CMD_ADDR
0
32
CHn_SEMA
CHn_SEMA
0
8
0x70
0x70
PHORE
16
8
INCREMENT_SEMA
0
8
CHn_DEBUG1
CHn_DEBUG1
0
8
0x80
0x70
REQ
31
BURST
30
KICK
29
END
28
RSVD2
25
3
NEXTCMDADDRVALID
24
RD_FIFO_EMPTY
23
RD_FIFO_FULL
22
WR_FIFO_EMPTY
21
WR_FIFO_FULL
20
RSVD1
5
15
STATEMACHINE
0
5
IDLE
0x0
REQ_CMD1
0x1
REQ_CMD3
0x2
REQ_CMD2
0x3
XFER_DECODE
0x4
REQ_WAIT
0x5
REQ_CMD4
0x6
PIO_REQ
0x7
READ_FLUSH
0x8
READ_WAIT
0x9
WRITE
0xc
READ_REQ
0xd
CHECK_CHAIN
0xe
XFER_COMPLETE
0xf
WAIT_END
0x15
WRITE_WAIT
0x1c
CHECK_WAIT
0x1e
APBX
APHX DMA
AHB-to-APBX Bridge with DMA
APBX
0x80024000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RESET_CHANNEL
16
8
AUDIOIN
0x1
AUDIOOUT
0x2
SPDIF_TX
0x4
I2C
0x8
LCDIF
0x10
DRI
0x20
UART_RX
0x30
IRDA_RX
0x30
UART_TX
0x40
IRDA_TX
0x40
FREEZE_CHANNEL
0
8
AUDIOIN
0x1
AUDIOOUT
0x2
SPDIF_TX
0x4
I2C
0x8
LCDIF
0x10
DRI
0x20
UART_RX
0x30
IRDA_RX
0x30
UART_TX
0x40
IRDA_TX
0x40
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
CH_CMDCMPLT_IRQ_EN
16
8
CH_CMDCMPLT_IRQ
0
8
set
4
clr
8
tog
12
DEVSEL
DEVSEL
0x20
CH7
28
4
USE_UART
0x0
USE_IRDA
0x1
CH6
24
4
USE_UART
0x0
USE_IRDA
0x1
CH5
20
4
CH4
16
4
CH3
12
4
CH2
8
4
CH1
4
4
CH0
0
4
CHn_NXTCMDAR
CHn_NXTCMDAR
0
8
0x40
0x70
CMD_ADDR
0
32
CHn_DEBUG2
CHn_DEBUG2
0
8
0x90
0x70
APB_BYTES
16
16
AHB_BYTES
0
16
CHn_BAR
CHn_BAR
0
8
0x60
0x70
ADDRESS
0
32
CHn_CMD
CHn_CMD
0
8
0x50
0x70
XFER_COUNT
16
16
CMDWORDS
12
4
WAIT4ENDCMD
7
SEMAPHORE
6
IRQONCMPLT
3
CHAIN
2
COMMAND
0
2
NO_DMA_XFER
0x0
DMA_WRITE
0x1
DMA_READ
0x2
CHn_DEBUG1
CHn_DEBUG1
0
8
0x80
0x70
REQ
31
BURST
30
KICK
29
END
28
RSVD2
25
3
NEXTCMDADDRVALID
24
RD_FIFO_EMPTY
23
RD_FIFO_FULL
22
WR_FIFO_EMPTY
21
WR_FIFO_FULL
20
RSVD1
5
15
STATEMACHINE
0
5
IDLE
0x0
REQ_CMD1
0x1
REQ_CMD3
0x2
REQ_CMD2
0x3
XFER_DECODE
0x4
REQ_WAIT
0x5
REQ_CMD4
0x6
PIO_REQ
0x7
READ_FLUSH
0x8
READ_WAIT
0x9
WRITE
0xc
READ_REQ
0xd
CHECK_CHAIN
0xe
XFER_COMPLETE
0xf
WAIT_END
0x15
WRITE_WAIT
0x1c
CHECK_WAIT
0x1e
CHn_SEMA
CHn_SEMA
0
8
0x70
0x70
PHORE
16
8
INCREMENT_SEMA
0
8
CHn_CURCMDAR
CHn_CURCMDAR
0
8
0x30
0x70
CMD_ADDR
0
32
AUDIOIN
AUDIOIN/ADC
Digital Audio Filter Input
AUDIOIN
0x8004c000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
LR_SWAP
10
EDGE_SYNC
9
INVERT_1BIT
8
OFFSET_ENABLE
7
HPF_ENABLE
6
WORD_LENGTH
5
LOOPBACK
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
ADC_PRESENT
31
ADCSRR
ADCSRR
0x20
OSR
31
OSR6
0x0
OSR12
0x1
BASEMULT
28
3
SINGLE_RATE
0x1
DOUBLE_RATE
0x2
QUAD_RATE
0x4
SRC_HOLD
24
3
SRC_INT
16
5
SRC_FRAC
0
13
set
4
clr
8
tog
12
ADCVOLUME
ADCVOLUME
0x30
VOLUME_UPDATE_LEFT
28
EN_ZCD
25
VOLUME_LEFT
16
8
VOLUME_UPDATE_RIGHT
12
VOLUME_RIGHT
0
8
set
4
clr
8
tog
12
ADCDEBUG
ADCDEBUG
0x40
ENABLE_ADCDMA
31
ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS
3
SET_INTERRUPT3_HAND_SHAKE
2
DMA_PREQ
1
FIFO_STATUS
0
set
4
clr
8
tog
12
ADCVOL
ADCVOL
0x50
SELECT_LEFT
28
2
SELECT_RIGHT
24
2
MUTE
8
GAIN_LEFT
4
4
GAIN_RIGHT
0
4
set
4
clr
8
tog
12
MICLINE
MICLINE
0x60
ATTEN_LINE
30
DIVIDE_LINE1
29
DIVIDE_LINE2
28
MIC_SELECT
24
MIC_RESISTOR
20
2
Off
0x0
2KOhm
0x1
4KOhm
0x2
8KOhm
0x3
MIC_BIAS
16
3
FORCE_MICAMP_PWRUP
8
MIC_GAIN
0
2
0dB
0x0
20dB
0x1
30dB
0x2
40dB
0x3
set
4
clr
8
tog
12
ANACLKCTRL
ANACLKCTRL
0x70
CLKGATE
31
DITHER_ENABLE
6
SLOW_DITHER
5
INVERT_ADCCLK
4
ADCDIV
0
3
set
4
clr
8
tog
12
DATA
DATA
0x80
HIGH
16
16
LOW
0
16
AUDIOOUT
AUDIOOUT/DAC
Digital Audio Filter Output
AUDIOOUT
0x80048000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
LR_SWAP
14
EDGE_SYNC
13
INVERT_1BIT
12
SS3D_EFFECT
8
2
WORD_LENGTH
6
DAC_ZERO_ENABLE
5
LOOPBACK
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
DAC_PRESENT
31
DACSRR
DACSRR
0x20
OSR
31
OSR6
0x0
OSR12
0x1
BASEMULT
28
3
SINGLE_RATE
0x1
DOUBLE_RATE
0x2
QUAD_RATE
0x4
SRC_HOLD
24
3
SRC_INT
16
5
SRC_FRAC
0
13
set
4
clr
8
tog
12
DACVOLUME
DACVOLUME
0x30
VOLUME_UPDATE_LEFT
28
EN_ZCD
25
MUTE_LEFT
24
VOLUME_LEFT
16
8
VOLUME_UPDATE_RIGHT
12
MUTE_RIGHT
8
VOLUME_RIGHT
0
8
set
4
clr
8
tog
12
DACDEBUG
DACDEBUG
0x40
ENABLE_DACDMA
31
SET_INTERRUPT1_CLK_CROSS
5
SET_INTERRUPT0_CLK_CROSS
4
SET_INTERRUPT1_HAND_SHAKE
3
SET_INTERRUPT0_HAND_SHAKE
2
DMA_PREQ
1
FIFO_STATUS
0
set
4
clr
8
tog
12
HPVOL
HPVOL
0x50
SELECT
24
2
MUTE
16
VOL_LEFT
8
5
VOL_RIGHT
0
5
set
4
clr
8
tog
12
SPKRVOL
SPKRVOL
0x60
MUTE
16
VOL
0
4
set
4
clr
8
tog
12
PWRDN
PWRDN
0x70
SPEAKER
24
SELFBIAS
20
RIGHT_ADC
16
DAC
12
ADC
8
CAPLESS
4
HEADPHONE
0
set
4
clr
8
tog
12
REFCTRL
REFCTRL
0x80
XTAL_BGR_BIAS
24
VBG_ADJ
20
3
LOW_PWR
19
LW_REF
18
BIAS_CTRL
16
2
ADJ_ADC
13
ADJ_VAG
12
ADC_REFVAL
8
4
VAG_VAL
4
4
DAC_ADJ
0
3
set
4
clr
8
tog
12
ANACTRL
ANACTRL
0x90
SHORT_CM_STS
28
SHORT_LR_STS
24
SHORTMODE_CM
20
2
SHORTMODE_LR
17
2
SHORT_LVLADJL
12
3
SHORT_LVLADJR
8
3
HP_HOLD_GND
5
HP_CLASSAB
4
EN_SPKR_ZCD
2
ZCD_SELECTADC
1
EN_ZCD
0
set
4
clr
8
tog
12
TEST
TEST
0xa0
HP_ANTIPOP
28
3
TM_ADCIN_TOHP
26
TM_SPEAKER
25
TM_HPCOMMON
24
HP_I1_ADJ
22
2
HP_IALL_ADJ
20
2
SPKR_I1_ADJ
18
2
SPKR_IALL_ADJ
16
2
VAG_CLASSA
13
VAG_DOUBLE_I
12
HP_CHOPCLK
8
2
DAC_CHOPCLK
4
2
DAC_CLASSA
2
DAC_DOUBLE_I
1
DAC_DIS_RTZ
0
set
4
clr
8
tog
12
BISTCTRL
BISTCTRL
0xb0
FAIL
3
PASS
2
DONE
1
START
0
set
4
clr
8
tog
12
BISTSTAT0
BISTSTAT0
0xc0
DATA
0
24
BISTSTAT1
BISTSTAT1
0xd0
STATE
24
5
ADDR
0
8
ANACLKCTRL
ANACLKCTRL
0xe0
CLKGATE
31
INVERT_DACCLK
4
DACDIV
0
3
set
4
clr
8
tog
12
DATA
DATA
0xf0
HIGH
16
16
LOW
0
16
set
4
clr
8
tog
12
BRAZOIOCSR
BRAZO IO
BRAZO PIO Control
BRAZOIOCSR
0x80038000
CLKCTRL
Clock Controller
Clock Generation and Control
CLKCTRL
0x80040000
PLLCTRL0
PLLCTRL0
0x0
PLLVCOKSTART
30
PLLCPSHORTLFR
29
PLLCPDBLIP
28
PLLCPNSEL
24
3
DEFAULT
0x0
TIMES_15
0x2
TIMES_075
0x3
TIMES_05
0x4
TIMES_04
0x7
PLLV2ISEL
20
2
NORMAL
0x0
LOWER
0x1
LOWEST
0x2
HIGHEST
0x3
FORCE_FREQ
19
FORCE_SAME_FREQ
0x1
HONOR_SAME_FREQ_RULE
0x0
EN_USB_CLKS
18
BYPASS
17
POWER
16
FREQ
0
9
set
4
clr
8
tog
12
PLLCTRL1
PLLCTRL1
0x10
LOCK
31
FORCE_LOCK
30
LOCK_COUNT
0
16
set
4
clr
8
tog
12
CPU
CPU
0x20
WAIT_PLL_LOCK
30
BUSY
29
INTERRUPT_WAIT
12
DIV
0
10
HBUS
HBUS
0x30
WAIT_PLL_LOCK
30
BUSY
29
EMI_BUSY_FAST
27
APBHDMA_BUSY_FAST
26
APBXDMA_BUSY_FAST
25
TRAFFIC_JAM_FAST
24
TRAFFIC_FAST
23
CPU_DATA_FAST
22
CPU_INSTR_FAST
21
AUTO_SLOW_MODE
20
SLOW_DIV
16
2
BY1
0x0
BY2
0x1
BY4
0x2
BY8
0x3
DIV
0
5
XBUS
XBUS
0x40
BUSY
31
DIV
0
10
XTAL
XTAL
0x50
UART_CLK_GATE
31
FILT_CLK24M_GATE
30
PWM_CLK24M_GATE
29
DRI_CLK24M_GATE
28
DIGCTRL_CLK1M_GATE
27
TIMROT_CLK32K_GATE
26
EXRAM_CLK16K_GATE
25
LRADC_CLK2K_GATE
24
OCRAM
OCRAM
0x60
CLKGATE
31
BUSY
30
DIV
0
10
UTMI
UTMI
0x70
UTMI_CLK120M_GATE
31
UTMI_CLK30M_GATE
30
SSP
SSP
0x80
CLKGATE
31
WAIT_PLL_LOCK
30
BUSY
29
DIV
0
9
GPMI
GPMI
0x90
CLKGATE
31
WAIT_PLL_LOCK
30
BUSY
29
DIV
0
10
SPDIF
SPDIF
0xa0
CLKGATE
31
BUSY
30
DIV
0
3
EMI
EMI
0xb0
CLKGATE
31
WAIT_PLL_LOCK
30
BUSY
29
DIV
0
3
IR
IR
0xc0
CLKGATE
31
WAIT_PLL_LOCK
30
AUTO_DIV
29
IR_BUSY
28
IROV_BUSY
27
IROV_DIV
16
9
IR_DIV
0
10
DACDMA
DAC DMA
DAC DMA Control
DACDMA
0x8004c000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
RUN
0
set
4
clr
8
tog
12
DATA
DATA
0x80
HIGH
16
16
LOW
0
16
DIGCTL
Digital Control
Digital Control and On-Chip RAM
DIGCTL
0x8001c000
CTRL
CTRL
0x0
MASTER_SELECT
24
5
ARM_I
0x1
ARM_D
0x2
USB
0x4
APBH
0x8
APBX
0x10
USB_TESTMODE
20
ANALOG_TESTMODE
19
DIGITAL_TESTMODE
18
UTMI_TESTMODE
17
UART_LOOPBACK
16
NORMAL
0x0
LOOPIT
0x1
DEBUG_DISABLE
3
USB_CLKGATE
2
RUN
0x0
NO_CLKS
0x1
JTAG_SHIELD
1
NORMAL
0x0
SHIELDS_UP
0x1
PACKAGE_SENSE_ENABLE
0
DISABLE
0x0
ENABLE
0x1
set
4
clr
8
tog
12
STATUS
STATUS
0x10
ROM_KEYS_PRESENT
31
JTAG_SHIELD_DEFAULT
6
ROM_SHIELDED
5
JTAG_IN_USE
4
PSWITCH
2
2
PACKAGE_TYPE
1
WRITTEN
0
HCLKCOUNT
HCLKCOUNT
0x20
COUNT
0
32
RAMCTRL
RAMCTRL
0x30
TEST_MARGIN
28
3
NORMAL
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
LEVEL4
0x4
LEVEL5
0x5
LEVEL6
0x6
LEVEL7
0x7
PWDN_BANKS
24
4
PWDN_BANK3
0x8
PWDN_BANK2
0x4
PWDN_BANK1
0x2
PWDN_BANK0
0x1
TEMP_SENSOR
20
3
TEST_TEMP_COMP
16
3
LOW_TEMP
0x1
RANGE_A
0x2
RANGE_B
0x3
RANGE_C
0x4
RANGE_D
0x5
RANGE_E
0x6
RANGE_F
0x7
SHIFT_COUNT
8
7
FLIP_CLK
7
NORMAL
0x0
INVERT
0x1
OVER_RIDE_TEMP
3
NORMAL
0x0
OVER_RIDE
0x1
REF_CLK_GATE
2
NORMAL
0x0
OFF
0x1
REPAIR_STATUS
1
IDLE
0x0
BUSY
0x1
REPAIR_TRANSMIT
0
IDLE
0x0
SEND
0x1
set
4
clr
8
tog
12
RAMREPAIR0
RAMREPAIR0
0x40
EFUSE3
24
7
EFUSE2
16
7
EFUSE1
8
7
EFUSE0
0
7
set
4
clr
8
tog
12
RAMREPAIR1
RAMREPAIR1
0x50
EFUSE3
24
7
EFUSE2
16
7
EFUSE1
8
7
EFUSE0
0
7
set
4
clr
8
tog
12
WRITEONCE
WRITEONCE
0x60
BITS
0
32
AHBCYCLES
AHBCYCLES
0x70
COUNT
0
32
AHBSTALLED
AHBSTALLED
0x80
COUNT
0
32
ENTROPY
ENTROPY
0x90
VALUE
0
32
ROMSHIELD
ROMSHIELD
0xa0
WRITE_ONCE
0
MICROSECONDS
MICROSECONDS
0xb0
VALUE
0
32
set
4
clr
8
tog
12
DBGRD
DBGRD
0xc0
COMPLEMENT
0
32
DBG
DBG
0xd0
VALUE
0
32
1TRAM_BIST_CSR
1TRAM_BIST_CSR
0xe0
FAIL
3
PASS
2
DONE
1
START
0
set
4
clr
8
tog
12
1TRAM_BIST_REPAIR0
1TRAM_BIST_REPAIR0
0xf0
1TRAM_BIST_REPAIR1
1TRAM_BIST_REPAIR1
0x100
1TRAM_STATUS0
1TRAM_STATUS0
0x110
FAILDATA00
0
32
1TRAM_STATUS1
1TRAM_STATUS1
0x120
FAILDATA01
0
32
1TRAM_STATUS2
1TRAM_STATUS2
0x130
FAILDATA10
0
32
1TRAM_STATUS3
1TRAM_STATUS3
0x140
FAILDATA11
0
32
1TRAM_STATUS4
1TRAM_STATUS4
0x150
FAILDATA20
0
32
1TRAM_STATUS5
1TRAM_STATUS5
0x160
FAILDATA21
0
32
1TRAM_STATUS6
1TRAM_STATUS6
0x170
FAILDATA30
0
32
1TRAM_STATUS7
1TRAM_STATUS7
0x180
FAILDATA31
0
32
1TRAM_STATUS8
1TRAM_STATUS8
0x190
FAILADDR01
16
16
FAILADDR00
0
16
1TRAM_STATUS9
1TRAM_STATUS9
0x1a0
FAILADDR11
16
16
FAILADDR10
0
16
1TRAM_STATUS10
1TRAM_STATUS10
0x1b0
FAILADDR21
16
16
FAILADDR20
0
16
1TRAM_STATUS11
1TRAM_STATUS11
0x1c0
FAILADDR31
16
16
FAILADDR30
0
16
1TRAM_STATUS12
1TRAM_STATUS12
0x1d0
FAILSTATE11
24
5
FAILSTATE10
16
5
FAILSTATE01
8
5
FAILSTATE00
0
5
1TRAM_STATUS13
1TRAM_STATUS13
0x1e0
FAILSTATE31
24
5
FAILSTATE30
16
5
FAILSTATE21
8
5
FAILSTATE20
0
5
SCRATCH0
SCRATCH0
0x290
PTR
0
32
SCRATCH1
SCRATCH1
0x2a0
PTR
0
32
ARMCACHE
ARMCACHE
0x2b0
CACHE_SS
8
2
DTAG_SS
4
2
ITAG_SS
0
2
SGTL
SGTL
0x300
COPYRIGHT
0
32
CHIPID
CHIPID
0x310
PRODUCT_CODE
16
16
REVISION
0
8
DRI
Digital Radio Interface
Digital Radio Interface (DRI)
DRI
0x80074000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
ENABLE_INPUTS
29
ANALOG_LINE_IN
0x0
DRI_DIGITAL_IN
0x1
STOP_ON_OFLOW_ERROR
26
IGNORE
0x0
STOP
0x1
STOP_ON_PILOT_ERROR
25
IGNORE
0x0
STOP
0x1
DMA_DELAY_COUNT
16
5
REACQUIRE_PHASE
15
NORMAL
0x0
NEW_PHASE
0x1
OVERFLOW_IRQ_EN
11
DISABLED
0x0
ENABLED
0x1
PILOT_SYNC_LOSS_IRQ_EN
10
DISABLED
0x0
ENABLED
0x1
ATTENTION_IRQ_EN
9
DISABLED
0x0
ENABLED
0x1
OVERFLOW_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
PILOT_SYNC_LOSS_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
ATTENTION_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
RUN
0
HALT
0x0
RUN
0x1
set
4
clr
8
tog
12
TIMING
TIMING
0x10
PILOT_REP_RATE
16
4
GAP_DETECTION_INTERVAL
0
8
STAT
STAT
0x20
DRI_PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
PILOT_PHASE
16
4
OVERFLOW_IRQ_SUMMARY
3
NO_REQUEST
0x0
REQUEST
0x1
PILOT_SYNC_LOSS_IRQ_SUMMARY
2
NO_REQUEST
0x0
REQUEST
0x1
ATTENTION_IRQ_SUMMARY
1
NO_REQUEST
0x0
REQUEST
0x1
DATA
DATA
0x30
DATA
0
32
DEBUG0
DEBUG0
0x40
DMAREQ
31
DMACMDKICK
30
DRI_CLK_INPUT
29
DRI_DATA_INPUT
28
TEST_MODE
27
PILOT_REP_RATE
26
8_AT_4MHZ
0x0
12_AT_6MHZ
0x1
SPARE
18
8
FRAME
0
18
set
4
clr
8
tog
12
DEBUG1
DEBUG1
0x50
INVERT_PILOT
31
NORMAL
0x0
INVERTED
0x1
INVERT_ATTENTION
30
NORMAL
0x0
INVERTED
0x1
INVERT_DRI_DATA
29
NORMAL
0x0
INVERTED
0x1
INVERT_DRI_CLOCK
28
NORMAL
0x0
INVERTED
0x1
REVERSE_FRAME
27
NORMAL
0x0
REVERSED
0x1
SWIZZLED_FRAME
0
18
set
4
clr
8
tog
12
EMI
External Memory Interface
External Memory Interface (EMI)
EMI
0x80020000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
CE3_MODE
3
STATIC
0x0
DRAM
0x1
CE2_MODE
2
STATIC
0x0
DRAM
0x1
CE1_MODE
1
STATIC
0x0
DRAM
0x1
CE0_MODE
0
STATIC
0x0
DRAM
0x1
set
4
clr
8
tog
12
STAT
STAT
0x10
DRAM_PRESENT
31
STATIC_PRESENT
30
LARGE_DRAM_ENABLED
29
WRITE_BUFFER_DATA
1
EMPTY
0x0
NOT_EMPTY
0x1
BUSY
0
NOT_BUSY
0x0
BUSY
0x1
DEBUG
DEBUG
0x20
STATIC_STATE
16
3
DRAM_STATE
0
5
DRAMSTAT
DRAMSTAT
0x80
SELF_REFRESH_ACK
2
BUSY
1
READY
0
DRAMCTRL
DRAMCTRL
0x90
EMICLK_DIVIDE
24
3
AUTO_EMICLK_GATE
23
EMICLK_ENABLE
21
EMICLKEN_ENABLE
20
DRAM_TYPE
16
4
PRECHARGE
2
SELF_REFRESH
1
set
4
clr
8
tog
12
DRAMADDR
DRAMADDR
0xa0
MODE
8
RBC
0x0
BRC
0x1
ROW_BITS
4
4
COLUMN_BITS
0
4
set
4
clr
8
tog
12
DRAMMODE
DRAMMODE
0xb0
CAS_LATENCY
4
3
RESERVED0
0x0
RESERVED1
0x1
CAS2
0x2
CAS3
0x3
RESERVED4
0x4
RESERVED5
0x5
RESERVED6
0x6
RESERVED7
0x7
DRAMTIME
DRAMTIME
0xc0
TRFC
24
4
TRC
20
4
TRAS
16
4
TRCD
12
4
TRP
8
2
TXSR
4
4
REFRESH_COUNTER
0
4
set
4
clr
8
tog
12
DRAMTIME2
DRAMTIME2
0xd0
PRECHARGE_COUNT
0
16
set
4
clr
8
tog
12
STATICCTRL
STATICCTRL
0x100
MEM_WIDTH
2
WRITE_PROTECT
1
RESET_OUT
0
set
4
clr
8
tog
12
STATICTIME
STATICTIME
0x110
THZ
24
4
TDH
16
4
TDS
8
4
TAS
0
4
set
4
clr
8
tog
12
GPMI
General Purpose Media Interface
General Purpose Media Interface
GPMI
0x8000c000
CTRL0
CTRL0
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
RUN
29
IDLE
0x0
BUSY
0x1
DEV_IRQ_EN
28
TIMEOUT_IRQ_EN
27
UDMA
26
DISABLED
0x0
ENABLED
0x1
COMMAND_MODE
24
2
WRITE
0x0
READ
0x1
READ_AND_COMPARE
0x2
WAIT_FOR_READY
0x3
WORD_LENGTH
23
16_BIT
0x0
8_BIT
0x1
LOCK_CS
22
DISABLED
0x0
ENABLED
0x1
CS
20
2
ADDRESS
17
3
NAND_DATA
0x0
NAND_CLE
0x1
NAND_ALE
0x2
ADDRESS_INCREMENT
16
DISABLED
0x0
ENABLED
0x1
XFER_COUNT
0
16
set
4
clr
8
tog
12
COMPARE
COMPARE
0x10
MASK
16
16
REFERENCE
0
16
CTRL1
CTRL1
0x20
DSAMPLE_TIME
12
2
DEV_IRQ
10
TIMEOUT_IRQ
9
BURST_EN
8
ABORT_WAIT_FOR_READY3
7
ABORT_WAIT_FOR_READY2
6
ABORT_WAIT_FOR_READY1
5
ABORT_WAIT_FOR_READY0
4
DEV_RESET
3
ENABLED
0x0
DISABLED
0x1
ATA_IRQRDY_POLARITY
2
ACTIVELOW
0x0
ACTIVEHIGH
0x1
CAMERA_MODE
1
GPMI_MODE
0
NAND
0x0
ATA
0x1
set
4
clr
8
tog
12
TIMING0
TIMING0
0x30
ADDRESS_SETUP
16
8
DATA_HOLD
8
8
DATA_SETUP
0
8
TIMING1
TIMING1
0x40
DEVICE_BUSY_TIMEOUT
16
16
ATA_READY_TIMEOUT
0
16
TIMING2
TIMING2
0x50
UDMA_TRP
24
8
UDMA_ENV
16
8
UDMA_HOLD
8
8
UDMA_SETUP
0
8
DATA
DATA
0x60
DATA
0
32
STAT
STAT
0x70
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
RDY_TIMEOUT
8
4
ATA_IRQ
7
FIFO_EMPTY
5
NOT_EMPTY
0x0
EMPTY
0x1
FIFO_FULL
4
NOT_FULL
0x0
FULL
0x1
DEV3_ERROR
3
DEV2_ERROR
2
DEV1_ERROR
1
DEV0_ERROR
0
DEBUG
DEBUG
0x80
READY3
31
READY2
30
READY1
29
READY0
28
WAIT_FOR_READY_END3
27
WAIT_FOR_READY_END2
26
WAIT_FOR_READY_END1
25
WAIT_FOR_READY_END0
24
SENSE3
23
SENSE2
22
SENSE1
21
SENSE0
20
DMAREQ3
19
DMAREQ2
18
DMAREQ1
17
DMAREQ0
16
CMD_END
12
4
UDMA_STATE
8
4
BUSY
7
DISABLED
0x0
ENABLED
0x1
PIN_STATE
4
3
PSM_IDLE
0x0
PSM_BYTCNT
0x1
PSM_ADDR
0x2
PSM_STALL
0x3
PSM_STROBE
0x4
PSM_ATARDY
0x5
PSM_DHOLD
0x6
PSM_DONE
0x7
MAIN_STATE
0
4
MSM_IDLE
0x0
MSM_BYTCNT
0x1
MSM_WAITFE
0x2
MSM_WAITFR
0x3
MSM_DMAREQ
0x4
MSM_DMAACK
0x5
MSM_WAITFF
0x6
MSM_LDFIFO
0x7
MSM_LDDMAR
0x8
MSM_RDCMP
0x9
MSM_DONE
0xa
I2C
I2C Interface
I2C Interface
I2C
0x80058000
CTRL0
CTRL0
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
RUN
29
HALT
0x0
RUN
0x1
PRE_ACK
27
ACKNOWLEDGE
26
SNAK
0x0
ACK
0x1
SEND_NAK_ON_LAST
25
ACK_IT
0x0
NAK_IT
0x1
PIO_MODE
24
MULTI_MASTER
23
SINGLE
0x0
MULTIPLE
0x1
CLOCK_HELD
22
RELEASE
0x0
HELD_LOW
0x1
RETAIN_CLOCK
21
RELEASE
0x0
HOLD_LOW
0x1
POST_SEND_STOP
20
NO_STOP
0x0
SEND_STOP
0x1
PRE_SEND_START
19
NO_START
0x0
SEND_START
0x1
SLAVE_ADDRESS_ENABLE
18
DISABLED
0x0
ENABLED
0x1
MASTER_MODE
17
SLAVE
0x0
MASTER
0x1
DIRECTION
16
RECEIVE
0x0
TRANSMIT
0x1
XFER_COUNT
0
16
set
4
clr
8
tog
12
TIMING0
TIMING0
0x10
HIGH_COUNT
16
10
RCV_COUNT
0
10
set
4
clr
8
tog
12
TIMING1
TIMING1
0x20
LOW_COUNT
16
10
XMIT_COUNT
0
10
set
4
clr
8
tog
12
TIMING2
TIMING2
0x30
BUS_FREE
16
10
LEADIN_COUNT
0
10
set
4
clr
8
tog
12
CTRL1
CTRL1
0x40
BCAST_SLAVE_EN
24
NO_BCAST
0x0
WATCH_BCAST
0x1
SLAVE_ADDRESS_BYTE
16
8
BUS_FREE_IRQ_EN
15
DISABLED
0x0
ENABLED
0x1
DATA_ENGINE_CMPLT_IRQ_EN
14
DISABLED
0x0
ENABLED
0x1
NO_SLAVE_ACK_IRQ_EN
13
DISABLED
0x0
ENABLED
0x1
OVERSIZE_XFER_TERM_IRQ_EN
12
DISABLED
0x0
ENABLED
0x1
EARLY_TERM_IRQ_EN
11
DISABLED
0x0
ENABLED
0x1
MASTER_LOSS_IRQ_EN
10
DISABLED
0x0
ENABLED
0x1
SLAVE_STOP_IRQ_EN
9
DISABLED
0x0
ENABLED
0x1
SLAVE_IRQ_EN
8
DISABLED
0x0
ENABLED
0x1
BUS_FREE_IRQ
7
NO_REQUEST
0x0
REQUEST
0x1
DATA_ENGINE_CMPLT_IRQ
6
NO_REQUEST
0x0
REQUEST
0x1
NO_SLAVE_ACK_IRQ
5
NO_REQUEST
0x0
REQUEST
0x1
OVERSIZE_XFER_TERM_IRQ
4
NO_REQUEST
0x0
REQUEST
0x1
EARLY_TERM_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
MASTER_LOSS_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_STOP_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_IRQ
0
NO_REQUEST
0x0
REQUEST
0x1
set
4
clr
8
tog
12
STAT
STAT
0x50
MASTER_PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
SLAVE_PRESENT
30
UNAVAILABLE
0x0
AVAILABLE
0x1
ANY_ENABLED_IRQ
29
NO_REQUESTS
0x0
AT_LEAST_ONE_REQUEST
0x1
RCVD_SLAVE_ADDR
16
8
SLAVE_ADDR_EQ_ZERO
15
ZERO_NOT_MATCHED
0x0
WAS_ZERO
0x1
SLAVE_FOUND
14
IDLE
0x0
WAITING
0x1
SLAVE_SEARCHING
13
IDLE
0x0
ACTIVE
0x1
DATA_ENGINE_DMA_WAIT
12
CONTINUE
0x0
WAITING
0x1
BUS_BUSY
11
IDLE
0x0
BUSY
0x1
CLK_GEN_BUSY
10
IDLE
0x0
BUSY
0x1
DATA_ENGINE_BUSY
9
IDLE
0x0
BUSY
0x1
SLAVE_BUSY
8
IDLE
0x0
BUSY
0x1
BUS_FREE_IRQ_SUMMARY
7
NO_REQUEST
0x0
REQUEST
0x1
DATA_ENGINE_CMPLT_IRQ_SUMMARY
6
NO_REQUEST
0x0
REQUEST
0x1
NO_SLAVE_ACK_IRQ_SUMMARY
5
NO_REQUEST
0x0
REQUEST
0x1
OVERSIZE_XFER_TERM_IRQ_SUMMARY
4
NO_REQUEST
0x0
REQUEST
0x1
EARLY_TERM_IRQ_SUMMARY
3
NO_REQUEST
0x0
REQUEST
0x1
MASTER_LOSS_IRQ_SUMMARY
2
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_STOP_IRQ_SUMMARY
1
NO_REQUEST
0x0
REQUEST
0x1
SLAVE_IRQ_SUMMARY
0
NO_REQUEST
0x0
REQUEST
0x1
DATA
DATA
0x60
DATA
0
32
DEBUG0
DEBUG0
0x70
DMAREQ
31
DMAENDCMD
30
DMAKICK
29
TBD
26
3
DMA_STATE
16
10
START_TOGGLE
15
STOP_TOGGLE
14
GRAB_TOGGLE
13
CHANGE_TOGGLE
12
TESTMODE
11
SLAVE_HOLD_CLK
10
SLAVE_STATE
0
10
set
4
clr
8
tog
12
DEBUG1
DEBUG1
0x80
I2C_CLK_IN
31
I2C_DATA_IN
30
DMA_BYTE_ENABLES
24
4
CLK_GEN_STATE
16
7
LST_MODE
9
2
BCAST
0x0
MY_WRITE
0x1
MY_READ
0x2
NOT_ME
0x3
LOCAL_SLAVE_TEST
8
FORCE_CLK_ON
5
FORCE_CLK_IDLE
4
FORCE_ARB_LOSS
3
FORCE_RCV_ACK
2
FORCE_I2C_DATA_OE
1
FORCE_I2C_CLK_OE
0
set
4
clr
8
tog
12
HWECC
Hardware ECC
Hardware ECC Accelerator
HWECC
0x80008000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
NUM_SYMBOLS
16
9
DMAWAIT_COUNT
8
5
BYTE_ENABLE
6
ECC_SEL
5
ENC_SEL
4
UNCORR_IRQ
2
UNCORR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
RSDEC_PRESENT
31
RSENC_PRESENT
30
SSDEC_PRESENT
29
SSENC_PRESENT
28
DEBUG0
DEBUG0
0x20
DMA_PENDCMD
29
DMA_PREQ
28
SYMBOL_STATE
24
4
CTRL_STATE
16
6
ECC_EXCEPTION
12
4
NUM_BIT_ERRORS
4
6
NUM_SYMBOL_ERRORS
0
3
DEBUG1
DEBUG1
0x30
SYNDROME2
18
9
SYNDROME1
9
9
SYNDROME0
0
9
DEBUG2
DEBUG2
0x40
SYNDROME5
18
9
SYNDROME4
9
9
SYNDROME3
0
9
DEBUG3
DEBUG3
0x50
OMEGA0
18
9
SYNDROME7
9
9
SYNDROME6
0
9
DEBUG4
DEBUG4
0x60
OMEGA3
18
9
OMEGA2
9
9
OMEGA1
0
9
DEBUG5
DEBUG5
0x70
LAMBDA2
18
9
LAMBDA1
9
9
LAMBDA0
0
9
DEBUG6
DEBUG6
0x80
LAMBDA4
9
9
LAMBDA3
0
9
DATA
DATA
0x90
DATA
0
32
set
4
clr
8
tog
12
ICOLL
Interrupt Collector
Interrupt Collector
ICOLL
0x80000000
VECTOR
VECTOR
0x0
IRQVECTOR
2
30
set
4
clr
8
tog
12
LEVELACK
LEVELACK
0x10
IRQLEVELACK
0
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
CTRL
CTRL
0x20
SFTRST
31
RUN
0x0
IN_RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLOCKS
0x1
ENABLE2FIQ35
27
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ34
26
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ33
25
DISABLE
0x0
ENABLE
0x1
ENABLE2FIQ32
24
DISABLE
0x0
ENABLE
0x1
BYPASS_FSM
20
NORMAL
0x0
BYPASS
0x1
NO_NESTING
19
NORMAL
0x0
NO_NEST
0x1
ARM_RSE_MODE
18
MUST_WRITE
0x0
READ_SIDE_EFFECT
0x1
FIQ_FINAL_ENABLE
17
DISABLE
0x0
ENABLE
0x1
IRQ_FINAL_ENABLE
16
DISABLE
0x0
ENABLE
0x1
set
4
clr
8
tog
12
STAT
STAT
0x30
VECTOR_NUMBER
0
6
VBASE
VBASE
0x160
TABLE_ADDRESS
2
30
set
4
clr
8
tog
12
DEBUG
DEBUG
0x170
INSERVICE
28
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
LEVEL_REQUESTS
24
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
REQUESTS_BY_LEVEL
20
4
LEVEL0
0x1
LEVEL1
0x2
LEVEL2
0x4
LEVEL3
0x8
FIQ
17
NO_FIQ_REQUESTED
0x0
FIQ_REQUESTED
0x1
IRQ
16
NO_IRQ_REQUESTED
0x0
IRQ_REQUESTED
0x1
VECTOR_FSM
0
10
FSM_IDLE
0x0
FSM_MULTICYCLE1
0x1
FSM_MULTICYCLE2
0x2
FSM_PENDING
0x4
FSM_MULTICYCLE3
0x8
FSM_MULTICYCLE4
0x10
FSM_ISR_RUNNING1
0x20
FSM_ISR_RUNNING2
0x40
FSM_ISR_RUNNING3
0x80
FSM_MULTICYCLE5
0x100
FSM_MULTICYCLE6
0x200
DBGFLAG
DBGFLAG
0x1a0
FLAG
0
16
set
4
clr
8
tog
12
DBGREQUESTn
DBGREQUESTn
0
2
0x1b0
0x10
BITS
0
32
RAWn
RAWn
0
2
0x40
0x10
RAW_IRQS
0
32
DBGREADn
DBGREADn
0
2
0x180
0x10
VALUE
0
32
PRIORITYn
PRIORITYn
0
16
0x60
0x10
SOFTIRQ3
27
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE3
26
DISABLE
0x0
ENABLE
0x1
PRIORITY3
24
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ2
19
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE2
18
DISABLE
0x0
ENABLE
0x1
PRIORITY2
16
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ1
11
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE1
10
DISABLE
0x0
ENABLE
0x1
PRIORITY1
8
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
SOFTIRQ0
3
NO_INTERRUPT
0x0
FORCE_INTERRUPT
0x1
ENABLE0
2
DISABLE
0x0
ENABLE
0x1
PRIORITY0
0
2
LEVEL0
0x0
LEVEL1
0x1
LEVEL2
0x2
LEVEL3
0x3
set
4
clr
8
tog
12
IR
IrDA
IrDA Controller
IR
0x80078000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
MTA
24
3
MTA_10MS
0x0
MTA_5MS
0x1
MTA_1MS
0x2
MTA_500US
0x3
MTA_100US
0x4
MTA_50US
0x5
MTA_10US
0x6
MTA_0
0x7
MODE
22
2
SIR
0x0
MIR
0x1
FIR
0x2
VFIR
0x3
SPEED
19
3
SPD000
0x0
SPD001
0x1
SPD010
0x2
SPD011
0x3
SPD100
0x4
SPD101
0x5
TC_TIME_DIV
8
6
TC_TYPE
7
SIR_GAP
4
3
GAP_10K
0x0
GAP_5K
0x1
GAP_1K
0x2
GAP_500
0x3
GAP_100
0x4
GAP_50
0x5
GAP_10
0x6
GAP_0
0x7
SIPEN
3
TCEN
2
TXEN
1
RXEN
0
set
4
clr
8
tog
12
TXDMA
TXDMA
0x10
RUN
31
EMPTY
29
INT
28
CHANGE
27
NEW_MTA
24
3
NEW_MODE
22
2
NEW_SPEED
19
3
BOF_TYPE
18
XBOFS
12
6
XFER_COUNT
0
12
set
4
clr
8
tog
12
RXDMA
RXDMA
0x20
RUN
31
XFER_COUNT
0
10
set
4
clr
8
tog
12
DBGCTRL
DBGCTRL
0x30
VFIRSWZ
12
NORMAL
0x0
SWAP
0x1
RXFRMOFF
11
RXCRCOFF
10
RXINVERT
9
TXFRMOFF
8
TXCRCOFF
7
TXINVERT
6
INTLOOPBACK
5
DUPLEX
4
MIO_RX
3
MIO_TX
2
MIO_SCLK
1
MIO_EN
0
set
4
clr
8
tog
12
INTR
INTR
0x40
RXABORT_IRQ_EN
22
DISABLED
0x0
ENABLED
0x1
SPEED_IRQ_EN
21
DISABLED
0x0
ENABLED
0x1
RXOF_IRQ_EN
20
DISABLED
0x0
ENABLED
0x1
TXUF_IRQ_EN
19
DISABLED
0x0
ENABLED
0x1
TC_IRQ_EN
18
DISABLED
0x0
ENABLED
0x1
RX_IRQ_EN
17
DISABLED
0x0
ENABLED
0x1
TX_IRQ_EN
16
DISABLED
0x0
ENABLED
0x1
RXABORT_IRQ
6
NO_REQUEST
0x0
REQUEST
0x1
SPEED_IRQ
5
NO_REQUEST
0x0
REQUEST
0x1
RXOF_IRQ
4
NO_REQUEST
0x0
REQUEST
0x1
TXUF_IRQ
3
NO_REQUEST
0x0
REQUEST
0x1
TC_IRQ
2
NO_REQUEST
0x0
REQUEST
0x1
RX_IRQ
1
NO_REQUEST
0x0
REQUEST
0x1
TX_IRQ
0
NO_REQUEST
0x0
REQUEST
0x1
set
4
clr
8
tog
12
DATA
DATA
0x50
DATA
0
32
STAT
STAT
0x60
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
MODE_ALLOWED
29
2
VFIR
0x0
FIR
0x1
MIR
0x2
SIR
0x3
ANY_IRQ
28
NO_REQUEST
0x0
REQUEST
0x1
RXABORT_SUMMARY
22
NO_REQUEST
0x0
REQUEST
0x1
SPEED_SUMMARY
21
NO_REQUEST
0x0
REQUEST
0x1
RXOF_SUMMARY
20
NO_REQUEST
0x0
REQUEST
0x1
TXUF_SUMMARY
19
NO_REQUEST
0x0
REQUEST
0x1
TC_SUMMARY
18
NO_REQUEST
0x0
REQUEST
0x1
RX_SUMMARY
17
NO_REQUEST
0x0
REQUEST
0x1
TX_SUMMARY
16
NO_REQUEST
0x0
REQUEST
0x1
MEDIA_BUSY
2
RX_ACTIVE
1
TX_ACTIVE
0
TCCTRL
TCCTRL
0x70
INIT
31
GO
30
BUSY
29
TEMIC
24
LOW
0x0
HIGH
0x1
EXT_DATA
16
8
DATA
8
8
ADDR
5
3
INDX
1
4
C
0
set
4
clr
8
tog
12
SI_READ
SI_READ
0x80
ABORT
8
DATA
0
8
DEBUG
DEBUG
0x90
TXDMAKICK
5
RXDMAKICK
4
TXDMAEND
3
RXDMAEND
2
TXDMAREQ
1
RXDMAREQ
0
LCDIF
LCD Interface
LCD Interface (LCDIF)
LCDIF
0x80060000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PRESENT
29
BUSY_ENABLE
25
BUSY_DISABLED
0x0
BUSY_ENABLED
0x1
FIFO_STATUS
24
FIFO_FULL
0x0
FIFO_OK
0x1
DMA_REQ
23
DATA_SWIZZLE
21
2
NO_SWAP
0x0
LITTLE_ENDIAN
0x0
BIG_ENDIAN_SWAP
0x1
SWAP_ALL_BYTES
0x1
HWD_SWAP
0x2
HWD_BYTE_SWAP
0x3
RESET
20
LCDRESET_LOW
0x0
LCDRESET_HIGH
0x1
MODE86
19
8080_MODE
0x0
6800_MODE
0x1
DATA_SELECT
18
CMD_MODE
0x0
DATA_MODE
0x1
WORD_LENGTH
17
16_BIT
0x0
8_BIT
0x1
RUN
16
COUNT
0
16
set
4
clr
8
tog
12
TIMING
TIMING
0x10
CMD_HOLD
24
8
CMD_SETUP
16
8
DATA_HOLD
8
8
DATA_SETUP
0
8
DATA
DATA
0x20
DATA_THREE
24
8
DATA_TWO
16
8
DATA_ONE
8
8
DATA_ZERO
0
8
DEBUG
DEBUG
0x30
BUSY
27
LAST_SUBWORD
26
SUBWORD_POSITION
24
2
EMPTY_WORD
23
STATE
16
7
DATA_COUNT
0
16
LRADC
Low Resolution ADC
Low-Resolution ADC and Touch-Screen Interface
LRADC
0x80050000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
ONCHIP_GROUNDREF
21
OFF
0x0
ON
0x1
TOUCH_DETECT_ENABLE
20
OFF
0x0
ON
0x1
YMINUS_ENABLE
19
OFF
0x0
ON
0x1
XMINUS_ENABLE
18
OFF
0x0
ON
0x1
YPLUS_ENABLE
17
OFF
0x0
ON
0x1
XPLUS_ENABLE
16
OFF
0x0
ON
0x1
SCHEDULE
0
8
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
TOUCH_DETECT_IRQ_EN
24
DISABLE
0x0
ENABLE
0x1
LRADC7_IRQ_EN
23
DISABLE
0x0
ENABLE
0x1
LRADC6_IRQ_EN
22
DISABLE
0x0
ENABLE
0x1
LRADC5_IRQ_EN
21
DISABLE
0x0
ENABLE
0x1
LRADC4_IRQ_EN
20
DISABLE
0x0
ENABLE
0x1
LRADC3_IRQ_EN
19
DISABLE
0x0
ENABLE
0x1
LRADC2_IRQ_EN
18
DISABLE
0x0
ENABLE
0x1
LRADC1_IRQ_EN
17
DISABLE
0x0
ENABLE
0x1
LRADC0_IRQ_EN
16
DISABLE
0x0
ENABLE
0x1
TOUCH_DETECT_IRQ
8
CLEAR
0x0
PENDING
0x1
LRADC7_IRQ
7
CLEAR
0x0
PENDING
0x1
LRADC6_IRQ
6
CLEAR
0x0
PENDING
0x1
LRADC5_IRQ
5
CLEAR
0x0
PENDING
0x1
LRADC4_IRQ
4
CLEAR
0x0
PENDING
0x1
LRADC3_IRQ
3
CLEAR
0x0
PENDING
0x1
LRADC2_IRQ
2
CLEAR
0x0
PENDING
0x1
LRADC1_IRQ
1
CLEAR
0x0
PENDING
0x1
LRADC0_IRQ
0
CLEAR
0x0
PENDING
0x1
set
4
clr
8
tog
12
CTRL2
CTRL2
0x20
DIVIDE_BY_TWO
24
8
LRADC6SELECT
20
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
LRADC7SELECT
16
4
CHANNEL0
0x0
CHANNEL1
0x1
CHANNEL2
0x2
CHANNEL3
0x3
CHANNEL4
0x4
CHANNEL5
0x5
CHANNEL6
0x6
CHANNEL7
0x7
CHANNEL8
0x8
CHANNEL9
0x9
CHANNEL10
0xa
CHANNEL11
0xb
CHANNEL12
0xc
CHANNEL13
0xd
CHANNEL14
0xe
CHANNEL15
0xf
TEMP_SENSOR_IENABLE1
9
DISABLE
0x0
ENABLE
0x1
TEMP_SENSOR_IENABLE0
8
DISABLE
0x0
ENABLE
0x1
TEMP_ISRC1
4
4
300
0xf
280
0xe
260
0xd
240
0xc
220
0xb
200
0xa
180
0x9
160
0x8
140
0x7
120
0x6
100
0x5
80
0x4
60
0x3
40
0x2
20
0x1
ZERO
0x0
TEMP_ISRC0
0
4
300
0xf
280
0xe
260
0xd
240
0xc
220
0xb
200
0xa
180
0x9
160
0x8
140
0x7
120
0x6
100
0x5
80
0x4
60
0x3
40
0x2
20
0x1
ZERO
0x0
set
4
clr
8
tog
12
CTRL3
CTRL3
0x30
DISCARD
24
2
1_SAMPLE
0x1
2_SAMPLES
0x2
3_SAMPLES
0x3
FORCE_ANALOG_PWUP
23
OFF
0x0
ON
0x1
FORCE_ANALOG_PWDN
22
ON
0x0
OFF
0x1
FORCE_PWD40UA_PWUP
21
OFF
0x0
ON
0x1
FORCE_PWD40UA_PWDN
20
ON
0x0
OFF
0x1
VDD_FILTER
16
2
0OHMS
0x0
100OHMS
0x1
250OHMS
0x2
5000OHMS
0x3
ADD_CAP2INPUTS
12
2
0PF
0x0
0_5PF
0x1
1_0PF
0x2
2_5PF
0x3
CYCLE_TIME
8
2
6MHZ
0x0
4MHZ
0x1
3MHZ
0x2
2MHZ
0x3
HIGH_TIME
4
2
42NS
0x0
83NS
0x1
125NS
0x2
250NS
0x3
REMOVE_CFILT
3
OFF
0x0
ON
0x1
SHORT_RFILT
2
OFF
0x0
ON
0x1
DELAY_CLOCK
1
NORMAL
0x0
DELAYED
0x1
INVERT_CLOCK
0
NORMAL
0x0
INVERT
0x1
set
4
clr
8
tog
12
STATUS
STATUS
0x40
TEMP1_PRESENT
26
TEMP0_PRESENT
25
TOUCH_PANEL_PRESENT
24
CHANNEL7_PRESENT
23
CHANNEL6_PRESENT
22
CHANNEL5_PRESENT
21
CHANNEL4_PRESENT
20
CHANNEL3_PRESENT
19
CHANNEL2_PRESENT
18
CHANNEL1_PRESENT
17
CHANNEL0_PRESENT
16
TOUCH_DETECT_RAW
0
OPEN
0x0
HIT
0x1
DEBUG0
DEBUG0
0x110
READONLY
16
16
STATE
0
12
DEBUG1
DEBUG1
0x120
REQUEST
16
8
TESTMODE_COUNT
8
5
TESTMODE6
2
NORMAL
0x0
TEST
0x1
TESTMODE5
1
NORMAL
0x0
TEST
0x1
TESTMODE
0
NORMAL
0x0
TEST
0x1
set
4
clr
8
tog
12
CONVERSION
CONVERSION
0x130
AUTOMATIC
20
DISABLE
0x0
ENABLE
0x1
SCALE_FACTOR
16
2
NIMH
0x0
DUAL_NIMH
0x1
LI_ION
0x2
ALT_LI_ION
0x3
SCALED_BATT_VOLTAGE
0
10
set
4
clr
8
tog
12
DELAYn
DELAYn
0
4
0xd0
0x10
TRIGGER_LRADCS
24
8
KICK
20
TRIGGER_DELAYS
16
4
LOOP_COUNT
11
5
DELAY
0
11
set
4
clr
8
tog
12
CHn
CHn
0
8
0x50
0x10
TOGGLE
31
ACCUMULATE
29
NUM_SAMPLES
24
5
VALUE
0
18
set
4
clr
8
tog
12
MEMCPY
MEMCPY Interface
MEMCPY Interface
MEMCPY
0x80014000
CTRL
CTRL
0x0
SFTRST
31
RUN
0x0
RESET
0x1
CLKGATE
30
RUN
0x0
NO_CLKS
0x1
PRESENT
29
UNAVAILABLE
0x0
AVAILABLE
0x1
BURST
16
XFER_SIZE
0
16
set
4
clr
8
tog
12
DATA
DATA
0x10
DATA
0
32
set
4
clr
8
tog
12
DEBUG
DEBUG
0x20
DST_END_CMD
30
DST_KICK
29
DST_DMA_REQ
28
SRC_KICK
25
SRC_DMA_REQ
24
WRITE_STATE
2
2
READ_STATE
0
2
PINCTRL
Pin Control
Pin Control and GPIO
PINCTRL
0x80018000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PRESENT3
29
PRESENT2
28
PRESENT1
27
PRESENT0
26
IRQOUT3
3
IRQOUT2
2
IRQOUT1
1
IRQOUT0
0
set
4
clr
8
tog
12
MUXSELLn
MUXSELLn
0
4
0x10
0x100
BITS
0
32
set
4
clr
8
tog
12
MUXSELHn
MUXSELHn
0
4
0x20
0x100
BITS
0
32
set
4
clr
8
tog
12
DRIVEn
DRIVEn
0
4
0x30
0x100
BITS
0
32
set
4
clr
8
tog
12
DOUTn
DOUTn
0
4
0x50
0x100
BITS
0
32
set
4
clr
8
tog
12
DINn
DINn
0
4
0x60
0x100
BITS
0
32
set
4
clr
8
tog
12
DOEn
DOEn
0
4
0x70
0x100
BITS
0
32
set
4
clr
8
tog
12
PIN2IRQn
PIN2IRQn
0
4
0x80
0x100
BITS
0
32
set
4
clr
8
tog
12
IRQENn
IRQENn
0
4
0x90
0x100
BITS
0
32
set
4
clr
8
tog
12
IRQLEVELn
IRQLEVELn
0
4
0xa0
0x100
BITS
0
32
set
4
clr
8
tog
12
IRQPOLn
IRQPOLn
0
4
0xb0
0x100
BITS
0
32
set
4
clr
8
tog
12
IRQSTATn
IRQSTATn
0
4
0xc0
0x100
BITS
0
32
set
4
clr
8
tog
12
POWER
Power Control
Power Supply
POWER
0x80044000
CTRL
CTRL
0x0
CLKGATE
30
BATT_BO_IRQ
8
ENIRQBATT_BO
7
VDDIO_BO_IRQ
6
ENIRQVDDIO_BO
5
VDDD_BO_IRQ
4
ENIRQVDDD_BO
3
POLARITY_VDD5V_GT_VDDIO
2
VDD5V_GT_VDDIO_IRQ
1
ENIRQ_VDD5V_GT_VDDIO
0
set
4
clr
8
tog
12
5VCTRL
5VCTRL
0x10
PWDN_5VBRNOUT
21
PWDN_IOBRNOUT
20
DISABLE_ILIMIT
19
DCDC_XFER
18
EN_BATT_PULLDN
17
VBUSVALID_5VDETECT
16
VBUSVALID_TRSH
8
2
USB_SUSPEND_I
7
VBUSVALID_TO_B
6
ILIMIT_EQ_ZERO
5
OTG_PWRUP_CMPS
4
EN_DCDC2
3
PWD_VDDD_LINREG
2
EN_DCDC1
1
LINREG_OFFSET
0
set
4
clr
8
tog
12
MINPWR
MINPWR
0x20
TEST_DISCHRG_VBUS
23
TEST_CHRG_VBUS
22
DC2_TST
21
DC1_TST
20
PERIPHERALSWOFF
19
TOGGLE_DIF
18
DISABLE_VDDIOSTEP
17
DISABLE_VDDSTEP
16
SEL_PLLDIV16CLK
9
PWD_VDDIOBO
8
LESSANA_I
7
DC1_HALFFETS
6
DC2_STOPCLK
5
DC1_STOPCLK
4
EN_DC2_PFM
3
EN_DC1_PFM
2
DC2_HALFCLK
1
DC1_HALFCLK
0
set
4
clr
8
tog
12
BATTCHRG
BATTCHRG
0x30
CHRG_STS_OFF
19
LIION_4P1
18
USE_EXTERN_R
17
PWD_BATTCHRG
16
STOP_ILIMIT
8
4
BATTCHRG_I
0
6
set
4
clr
8
tog
12
VDDCTRL
VDDCTRL
0x40
VDDIO_BO
24
5
VDDIO_TRG
16
5
VDDD_BO
8
5
VDDD_TRG
0
5
DC1MULTOUT
DC1MULTOUT
0x50
FUNCV
16
9
EN_BATADJ
8
ADJTN
0
4
DC1LIMITS
DC1LIMITS
0x60
EN_PFETOFF
24
POSLIMIT_BOOST
16
7
POSLIMIT_BUCK
8
7
NEGLIMIT
0
7
DC2LIMITS
DC2LIMITS
0x70
EN_BOOST
24
POSLIMIT_BOOST
16
7
POSLIMIT_BUCK
8
7
NEGLIMIT
0
7
LOOPCTRL
LOOPCTRL
0x80
TRAN_NOHYST
30
HYST_SIGN
29
EN_CMP_HYST
28
EN_DC2_RCSCALE
27
EN_DC1_RCSCALE
26
RC_SIGN
25
EN_RCSCALE
24
DC2_FF
20
3
DC2_R
16
4
DC2_C
12
2
DC1_FF
8
3
DC1_R
4
4
DC1_C
0
2
set
4
clr
8
tog
12
STS
STS
0x90
BATT_CHRG_PRESENT
31
MODE
20
2
BATT_BO
16
CHRGSTS
14
DC2_OK
13
DC1_OK
12
VDDIO_BO
9
VDDD_BO
8
VDD5V_GT_VDDIO
4
AVALID
3
BVALID
2
VBUSVALID
1
SESSEND
0
SPEEDTEMP
SPEEDTEMP
0xa0
SPEED_STS1
24
8
SPEED_STS2
16
8
TEMP_STS
8
4
SPEED_CTRL
4
2
TEMP_CTRL
0
4
set
4
clr
8
tog
12
BATTMONITOR
BATTMONITOR
0xb0
BATT_VAL
16
10
PWDN_BATTBRNOUT
9
BRWNOUT_PWD
8
BRWNOUT_LVL
0
4
RESET
RESET
0xc0
UNLOCK
16
16
KEY
0x3e77
PWD_OFF
4
POR
3
PWD
2
RST_DIG
1
RST_ALL
0
set
4
clr
8
tog
12
DEBUG
DEBUG
0xd0
ENCTRLVBUS
4
VBUSVALIDPIOLOCK
3
AVALIDPIOLOCK
2
BVALIDPIOLOCK
1
SESSENDPIOLOCK
0
set
4
clr
8
tog
12
PWM
Pulse width Modulation
Pulse-Width Modulator (PWM) Controller
PWM
0x80064000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
PWM4_PRESENT
29
PWM3_PRESENT
28
PWM2_PRESENT
27
PWM1_PRESENT
26
PWM0_PRESENT
25
PWM4_ENABLE
4
PWM3_ENABLE
3
PWM2_ENABLE
2
PWM1_ENABLE
1
PWM0_ENABLE
0
set
4
clr
8
tog
12
ACTIVEn
ACTIVEn
0
5
0x10
0x20
INACTIVE
16
16
ACTIVE
0
16
set
4
clr
8
tog
12
PERIODn
PERIODn
0
5
0x20
0x20
MATT
23
CDIV
20
3
DIV_1
0x0
DIV_2
0x1
DIV_4
0x2
DIV_8
0x3
DIV_16
0x4
DIV_64
0x5
DIV_256
0x6
DIV_1024
0x7
INACTIVE_STATE
18
2
HI_Z
0x0
0
0x2
1
0x3
ACTIVE_STATE
16
2
HI_Z
0x0
0
0x2
1
0x3
PERIOD
0
16
set
4
clr
8
tog
12
RTC
Real Time Clock
Real-Time Clock, Alarm, Watchdog, Persistent Bits
RTC
0x8005c000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
CLKDIV
24
4
SUPPRESS_COPY2ANALOG
6
NORMAL
0x0
NO_COPY
0x1
FORCE_UPDATE
5
NORMAL
0x0
FORCE_COPY
0x1
WATCHDOGEN
4
ONEMSEC_IRQ
3
ALARM_IRQ
2
ONEMSEC_IRQ_EN
1
ALARM_IRQ_EN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
RTC_PRESENT
31
ALARM_PRESENT
30
WATCHDOG_PRESENT
29
XTAL32768_PRESENT
28
STALE_REGS
16
6
NEW_REGS
8
6
FUSE_UNLOCK
1
FUSE_DONE
0
MILLISECONDS
MILLISECONDS
0x20
COUNT
0
32
set
4
clr
8
tog
12
SECONDS
SECONDS
0x30
COUNT
0
32
set
4
clr
8
tog
12
ALARM
ALARM
0x40
VALUE
0
32
set
4
clr
8
tog
12
WATCHDOG
WATCHDOG
0x50
COUNT
0
32
set
4
clr
8
tog
12
PERSISTENT0
PERSISTENT0
0x60
GENERAL
16
16
SDRAM_BOOT
0x8000
ENUMERATE_500MA_TWICE
0x4000
USB_BOOT_PLAYER_MODE
0x2000
SKIP_CHECKDISK
0x1000
USB_LOW_POWER_MODE
0x800
OTG_HNP_BIT
0x400
OTG_ATL_ROLE_BIT
0x200
SDRAM_CS_HI
0x100
SDRAM_CS_LO
0x80
SDRAM_NDX_3
0x40
SDRAM_NDX_2
0x20
SDRAM_NDX_1
0x10
SDRAM_NDX_0
0x8
ETM_ENABLE
0x4
DCDC_CTRL
6
10
SD_PRESENT
0x200
LOWBAT_3P0
0x100
SELFBIAS_PWRUP
0x80
AUTO_RESTART
0x40
DETECT_LOWBAT
0x20
DROP_BIAS1
0x10
DROP_BIAS2
0x8
SPARE
0x4
DISABLE_XTALSTOP
0x2
SPARE2
0x1
XTAL32_PDOWN
5
XTAL24_PDOWN
4
ALARM_WAKE_EN
3
ALARM_EN
2
ALARM_WAKE
1
CLOCKSOURCE
0
set
4
clr
8
tog
12
PERSISTENT1
PERSISTENT1
0x70
GENERAL
0
32
set
4
clr
8
tog
12
PERSISTENT2
PERSISTENT2
0x80
SRAM_LO
0
32
WARM_BOOT
0x80000000
set
4
clr
8
tog
12
PERSISTENT3
PERSISTENT3
0x90
SRAM_HI
0
32
set
4
clr
8
tog
12
DEBUG
DEBUG
0xa0
WATCHDOG_RESET_MASK
1
WATCHDOG_RESET
0
set
4
clr
8
tog
12
UNLOCK
UNLOCK
0x200
KEY
0
32
VAL
0xc6a83957
set
4
clr
8
tog
12
LASERFUSEn
LASERFUSEn
0
12
0x300
0x10
BITS
0
32
set
4
clr
8
tog
12
SPDIF
Sony/Phillips Digital Audio Interface
SPDIF Transmitter
SPDIF
0x80054000
CTRL
CTRL
0x0
SFTRST
31
CLKGATE
30
DMAWAIT_COUNT
16
5
WAIT_END_XFER
5
WORD_LENGTH
4
FIFO_UNDERFLOW_IRQ
3
FIFO_OVERFLOW_IRQ
2
FIFO_ERROR_IRQ_EN
1
RUN
0
set
4
clr
8
tog
12
STAT
STAT
0x10
PRESENT
31
END_XFER
0
FRAMECTRL
FRAMECTRL
0x20
V_CONFIG
17
AUTO_MUTE
16
USER_DATA
14
V
13
L
12
CC
4
7
PRE
3
COPY
2
AUDIO
1
PRO
0
set
4
clr
8
tog
12
SRR
SRR
0x30
BASEMULT
28
3
RATE
0
20
set
4
clr
8
tog
12
DEBUG
DEBUG
0x40
DMA_PREQ
1
FIFO_STATUS
0
DATA
DATA
0x50
HIGH
16
16
LOW
0
16
set
4
clr
8
tog
12
SSP
Sync Serial Port
Synchronous Serial Ports (SSP)
SSP
0x80010000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RUN
29
HALF_DUPLEX
28
LOCK_CS
27
IGNORE_CRC
26
READ
25
DATA_XFER
24
SDIO_IRQ
23
BUS_WIDTH
22
ONE_BIT
0x0
FOUR_BIT
0x1
WAIT_FOR_IRQ
21
WAIT_FOR_CMD
20
LONG_RESP
19
CHECK_RESP
18
GET_RESP
17
ENABLE
16
XFER_COUNT
0
16
set
4
clr
8
tog
12
CMD0
CMD0
0x10
CMD
0
8
MMC_GO_IDLE_STATE
0x0
MMC_SEND_OP_COND
0x1
MMC_ALL_SEND_CID
0x2
MMC_SET_RELATIVE_ADDR
0x3
MMC_SET_DSR
0x4
MMC_RESERVED_5
0x5
MMC_SWITCH
0x6
MMC_SELECT_DESELECT_CARD
0x7
MMC_SEND_EXT_CSD
0x8
MMC_SEND_CSD
0x9
MMC_SEND_CID
0xa
MMC_READ_DAT_UNTIL_STOP
0xb
MMC_STOP_TRANSMISSION
0xc
MMC_SEND_STATUS
0xd
MMC_BUSTEST_R
0xe
MMC_GO_INACTIVE_STATE
0xf
MMC_SET_BLOCKLEN
0x10
MMC_READ_SINGLE_BLOCK
0x11
MMC_READ_MULTIPLE_BLOCK
0x12
MMC_BUSTEST_W
0x13
MMC_WRITE_DAT_UNTIL_STOP
0x14
MMC_SET_BLOCK_COUNT
0x17
MMC_WRITE_BLOCK
0x18
MMC_WRITE_MULTIPLE_BLOCK
0x19
MMC_PROGRAM_CID
0x1a
MMC_PROGRAM_CSD
0x1b
MMC_SET_WRITE_PROT
0x1c
MMC_CLR_WRITE_PROT
0x1d
MMC_SEND_WRITE_PROT
0x1e
MMC_ERASE_GROUP_START
0x23
MMC_ERASE_GROUP_END
0x24
MMC_ERASE
0x26
MMC_FAST_IO
0x27
MMC_GO_IRQ_STATE
0x28
MMC_LOCK_UNLOCK
0x2a
MMC_APP_CMD
0x37
MMC_GEN_CMD
0x38
SD_GO_IDLE_STATE
0x0
SD_ALL_SEND_CID
0x2
SD_SEND_RELATIVE_ADDR
0x3
SD_SET_DSR
0x4
SD_IO_SEND_OP_COND
0x5
SD_SELECT_DESELECT_CARD
0x7
SD_SEND_CSD
0x9
SD_SEND_CID
0xa
SD_STOP_TRANSMISSION
0xc
SD_SEND_STATUS
0xd
SD_GO_INACTIVE_STATE
0xf
SD_SET_BLOCKLEN
0x10
SD_READ_SINGLE_BLOCK
0x11
SD_READ_MULTIPLE_BLOCK
0x12
SD_WRITE_BLOCK
0x18
SD_WRITE_MULTIPLE_BLOCK
0x19
SD_PROGRAM_CSD
0x1b
SD_SET_WRITE_PROT
0x1c
SD_CLR_WRITE_PROT
0x1d
SD_SEND_WRITE_PROT
0x1e
SD_ERASE_WR_BLK_START
0x20
SD_ERASE_WR_BLK_END
0x21
SD_ERASE_GROUP_START
0x23
SD_ERASE_GROUP_END
0x24
SD_ERASE
0x26
SD_LOCK_UNLOCK
0x2a
SD_IO_RW_DIRECT
0x34
SD_IO_RW_EXTENDED
0x35
SD_APP_CMD
0x37
SD_GEN_CMD
0x38
set
4
clr
8
tog
12
CMD1
CMD1
0x20
CMD_ARG
0
32
COMPREF
COMPREF
0x30
REFERENCE
0
32
COMPMASK
COMPMASK
0x40
MASK
0
32
TIMING
TIMING
0x50
TIMEOUT
16
16
CLOCK_DIVIDE
8
8
CLOCK_RATE
0
8
CTRL1
CTRL1
0x60
SDIO_IRQ
31
SDIO_IRQ_EN
30
RESP_ERR_IRQ
29
RESP_ERR_IRQ_EN
28
RESP_TIMEOUT_IRQ
27
RESP_TIMEOUT_IRQ_EN
26
DATA_TIMEOUT_IRQ
25
DATA_TIMEOUT_IRQ_EN
24
DATA_CRC_IRQ
23
DATA_CRC_IRQ_EN
22
XMIT_IRQ
21
XMIT_IRQ_EN
20
RECV_IRQ
19
RECV_IRQ_EN
18
RECV_TIMEOUT_IRQ
17
RECV_TIMEOUT_IRQ_EN
16
RECV_OVRFLW_IRQ
15
RECV_OVRFLW_IRQ_EN
14
DMA_ENABLE
13
LOOPBACK
12
SLAVE_OUT_DISABLE
11
PHASE
10
POLARITY
9
SLAVE_MODE
8
WORD_LENGTH
4
4
RESERVED0
0x0
RESERVED1
0x1
RESERVED2
0x2
FOUR_BITS
0x3
EIGHT_BITS
0x7
SIXTEEN_BITS
0xf
SSP_MODE
0
4
SPI
0x0
SSI
0x1
MICROWIRE
0x2
SD_MMC
0x3
MS
0x4
set
4
clr
8
tog
12
DATA
DATA
0x70
DATA
0
32
SDRESP0
SDRESP0
0x80
RESP0
0
32
SDRESP1
SDRESP1
0x90
RESP1
0
32
SDRESP2
SDRESP2
0xa0
RESP2
0
32
SDRESP3
SDRESP3
0xb0
RESP3
0
32
STATUS
STATUS
0xc0
PRESENT
31
MS_PRESENT
30
SD_PRESENT
29
CARD_DETECT
28
RECV_COUNT
24
4
XMIT_COUNT
20
4
DMAREQ
19
DMAEND
18
SDIO_IRQ
17
RESP_CRC_ERR
16
RESP_ERR
15
RESP_TIMEOUT
14
DATA_CRC_ERR
13
TIMEOUT
12
RECV_TIMEOUT_STAT
11
RECV_DATA_STAT
10
RECV_OVRFLW
9
RECV_FULL
8
RECV_NOT_EMPTY
7
XMIT_NOT_FULL
6
XMIT_EMPTY
5
XMIT_UNDRFLW
4
CMD_BUSY
3
DATA_BUSY
2
DATA_XFER
1
BUSY
0
DEBUG
DEBUG
0x100
DATACRC_ERR
28
4
DATA_STALL
27
DAT_SM
24
3
DSM_IDLE
0x0
DSM_START
0x1
DSM_WORD
0x2
DSM_CRC1
0x3
DSM_CRC2
0x4
DSM_END
0x5
DSM_RXDLY
0x6
MSTK_SM
20
4
MSTK_IDLE
0x0
MSTK_CKON
0x1
MSTK_BS1
0x2
MSTK_TPC
0x3
MSTK_BS2
0x4
MSTK_HDSHK
0x5
MSTK_BS3
0x6
MSTK_RW
0x7
MSTK_CRC1
0x8
MSTK_CRC2
0x9
MSTK_BS0
0xa
MSTK_DONE
0xb
CMD_OE
19
CMD_SM
16
3
CSM_IDLE
0x0
CSM_INDEX
0x1
CSM_ARG
0x2
CSM_CRC
0x3
CLK_OE
15
MMC_SM
12
3
MMC_IDLE
0x0
MMC_CMD
0x1
MMC_TRC
0x2
MMC_RESP
0x3
MMC_RPRX
0x4
MMC_TX
0x5
MMC_CTOK
0x6
MMC_RX
0x7
DAT0_OE
11
DAT321_OE
10
SSP_CMD
9
SSP_RESP
8
SSP_TXD
4
4
SSP_RXD
0
4
TIMROT
Timers/Rotary Interface
Timers and Rotary Decoder
TIMROT
0x80068000
ROTCTRL
ROTCTRL
0x0
SFTRST
31
CLKGATE
30
ROTARY_PRESENT
29
TIM3_PRESENT
28
TIM2_PRESENT
27
TIM1_PRESENT
26
TIM0_PRESENT
25
STATE
22
3
DIVIDER
16
6
RELATIVE
12
OVERSAMPLE
10
2
8X
0x0
4X
0x1
2X
0x2
1X
0x3
POLARITY_B
9
POLARITY_A
8
SELECT_B
4
3
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
SELECT_A
0
3
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
set
4
clr
8
tog
12
ROTCOUNT
ROTCOUNT
0x10
UPDOWN
0
16
TIMCTRL3
TIMCTRL3
0x80
TEST_SIGNAL
16
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
IRQ
15
IRQ_EN
14
DUTY_VALID
10
DUTY_CYCLE
9
POLARITY
8
UPDATE
7
RELOAD
6
PRESCALE
4
2
DIV_BY_1
0x0
DIV_BY_2
0x1
DIV_BY_4
0x2
DIV_BY_8
0x3
SELECT
0
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
set
4
clr
8
tog
12
TIMCOUNT3
TIMCOUNT3
0x90
LOW_RUNNING_COUNT
16
16
HIGH_FIXED_COUNT
0
16
TIMCOUNTn
TIMCOUNTn
0
3
0x30
0x20
RUNNING_COUNT
16
16
FIXED_COUNT
0
16
TIMCTRLn
TIMCTRLn
0
3
0x20
0x20
IRQ
15
IRQ_EN
14
POLARITY
8
UPDATE
7
RELOAD
6
PRESCALE
4
2
DIV_BY_1
0x0
DIV_BY_2
0x1
DIV_BY_4
0x2
DIV_BY_8
0x3
SELECT
0
4
NEVER_TICK
0x0
PWM0
0x1
PWM1
0x2
PWM2
0x3
PWM3
0x4
PWM4
0x5
ROTARYA
0x6
ROTARYB
0x7
32KHZ_XTAL
0x8
8KHZ_XTAL
0x9
4KHZ_XTAL
0xa
1KHZ_XTAL
0xb
TICK_ALWAYS
0xc
set
4
clr
8
tog
12
UARTAPP
Application UART
Application UART
UARTAPP
0x8006c000
CTRL0
CTRL0
0x0
SFTRST
31
CLKGATE
30
RUN
28
RX_SOURCE
25
RXTO_ENABLE
24
RXTIMEOUT
16
8
XFER_COUNT
0
16
set
4
clr
8
tog
12
CTRL1
CTRL1
0x10
RUN
28
XFER_COUNT
0
16
set
4
clr
8
tog
12
CTRL2
CTRL2
0x20
INVERT_RTS
31
INVERT_CTS
30
INVERT_TX
29
INVERT_RX
28
DMAONERR
26
TXDMAE
25
RXDMAE
24
RXIFLSEL
20
3
NOT_EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
TXIFLSEL
16
3
EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
CTSEN
15
RTSEN
14
OUT2
13
OUT1
12
RTS
11
DTR
10
RXE
9
TXE
8
LBE
7
SIRLP
2
SIREN
1
UARTEN
0
set
4
clr
8
tog
12
LINECTRL
LINECTRL
0x30
BAUD_DIVINT
16
16
BAUD_DIVFRAC
8
6
SPS
7
WLEN
5
2
FEN
4
STP2
3
EPS
2
PEN
1
BRK
0
set
4
clr
8
tog
12
INTR
INTR
0x40
OEIEN
26
BEIEN
25
PEIEN
24
FEIEN
23
RTIEN
22
TXIEN
21
RXIEN
20
DSRMIEN
19
DCDMIEN
18
CTSMIEN
17
RIMIEN
16
OEIS
10
BEIS
9
PEIS
8
FEIS
7
RTIS
6
TXIS
5
RXIS
4
DSRMIS
3
DCDMIS
2
CTSMIS
1
RIMIS
0
set
4
clr
8
tog
12
DATA
DATA
0x50
DATA
0
32
STAT
STAT
0x60
PRESENT
31
UNAVAILABLE
0x0
AVAILABLE
0x1
HISPEED
30
UNAVAILABLE
0x0
AVAILABLE
0x1
BUSY
29
CTS
28
TXFE
27
RXFF
26
TXFF
25
RXFE
24
RXBYTE_INVALID
20
4
OERR
19
BERR
18
PERR
17
FERR
16
RXCOUNT
0
16
DEBUG
DEBUG
0x70
TXDMARUN
5
RXDMARUN
4
TXCMDEND
3
RXCMDEND
2
TXDMARQ
1
RXDMARQ
0
UARTDBG
Debug UART
Debug UART
UARTDBG
0x80070000
DR
DR
0x0
UNAVAILABLE
16
16
RESERVED
12
4
OE
11
BE
10
PE
9
FE
8
DATA
0
8
RSR_ECR
RSR_ECR
0x4
UNAVAILABLE
8
24
EC
4
4
OE
3
BE
2
PE
1
FE
0
FR
FR
0x18
UNAVAILABLE
16
16
RESERVED
9
7
RI
8
TXFE
7
RXFF
6
TXFF
5
RXFE
4
BUSY
3
DCD
2
DSR
1
CTS
0
ILPR
ILPR
0x20
UNAVAILABLE
8
24
ILPDVSR
0
8
IBRD
IBRD
0x24
UNAVAILABLE
16
16
BAUD_DIVINT
0
16
FBRD
FBRD
0x28
UNAVAILABLE
8
24
RESERVED
6
2
BAUD_DIVFRAC
0
6
LCR_H
LCR_H
0x2c
UNAVAILABLE
16
16
RESERVED
8
8
SPS
7
WLEN
5
2
FEN
4
STP2
3
EPS
2
PEN
1
BRK
0
CR
CR
0x30
UNAVAILABLE
16
16
CTSEN
15
RTSEN
14
OUT2
13
OUT1
12
RTS
11
DTR
10
RXE
9
TXE
8
LBE
7
RESERVED
3
4
SIRLP
2
SIREN
1
UARTEN
0
IFLS
IFLS
0x34
UNAVAILABLE
16
16
RESERVED
6
10
RXIFLSEL
3
3
NOT_EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
TXIFLSEL
0
3
EMPTY
0x0
ONE_QUARTER
0x1
ONE_HALF
0x2
THREE_QUARTERS
0x3
SEVEN_EIGHTHS
0x4
INVALID5
0x5
INVALID6
0x6
INVALID7
0x7
IMSC
IMSC
0x38
UNAVAILABLE
16
16
RESERVED
11
5
OEIM
10
BEIM
9
PEIM
8
FEIM
7
RTIM
6
TXIM
5
RXIM
4
DSRMIM
3
DCDMIM
2
CTSMIM
1
RIMIM
0
RIS
RIS
0x3c
UNAVAILABLE
16
16
RESERVED
11
5
OERIS
10
BERIS
9
PERIS
8
FERIS
7
RTRIS
6
TXRIS
5
RXRIS
4
DSRRMIS
3
DCDRMIS
2
CTSRMIS
1
RIRMIS
0
MIS
MIS
0x40
UNAVAILABLE
16
16
RESERVED
11
5
OEMIS
10
BEMIS
9
PEMIS
8
FEMIS
7
RTMIS
6
TXMIS
5
RXMIS
4
DSRMMIS
3
DCDMMIS
2
CTSMMIS
1
RIMMIS
0
ICR
ICR
0x44
UNAVAILABLE
16
16
RESERVED
11
5
OEIC
10
BEIC
9
PEIC
8
FEIC
7
RTIC
6
TXIC
5
RXIC
4
DSRMIC
3
DCDMIC
2
CTSMIC
1
RIMIC
0
DMACR
DMACR
0x48
UNAVAILABLE
16
16
RESERVED
3
13
DMAONERR
2
TXDMAE
1
RXDMAE
0
ARC
USB Controller
USB High-Speed Host/Device Controller
ARC
0x80080000
BASE
BASE
0x0
ID
ID
0x0
HCSPARAMS
HCSPARAMS
0x104
USBCMD
USBCMD
0x140
USBSTS
USBSTS
0x144
USBINTR
USBINTR
0x148
FRINDEX
FRINDEX
0x14c
DEVADDR
DEVADDR
0x154
ENDPTLISTADDR
ENDPTLISTADDR
0x158
PORTSC1
PORTSC1
0x184
OTGSC
OTGSC
0x1a4
USBMODE
USBMODE
0x1a8
ENDPTSETUPSTAT
ENDPTSETUPSTAT
0x1ac
ENDPTPRIME
ENDPTPRIME
0x1b0
ENDPTFLUSH
ENDPTFLUSH
0x1b4
ENDPTSTATUS
ENDPTSTATUS
0x1b8
ENDPTCOMPLETE
ENDPTCOMPLETE
0x1bc
ENDPTCTRL0
ENDPTCTRL0
0x1c0
ENDPTCTRL1
ENDPTCTRL1
0x1c4
ENDPTCTRL2
ENDPTCTRL2
0x1c8
ENDPTCTRL3
ENDPTCTRL3
0x1cc
ENDPTCTRL4
ENDPTCTRL4
0x1d0
ENDPTCTRL5
ENDPTCTRL5
0x1d4
ENDPTCTRL6
ENDPTCTRL6
0x1d8
ENDPTCTRL7
ENDPTCTRL7
0x1dc
ENDPTCTRL8
ENDPTCTRL8
0x1e0
ENDPTCTRL9
ENDPTCTRL9
0x1e4
ENDPTCTRL10
ENDPTCTRL10
0x1e8
ENDPTCTRL11
ENDPTCTRL11
0x1ec
ENDPTCTRL12
ENDPTCTRL12
0x1f0
ENDPTCTRL13
ENDPTCTRL13
0x1f4
ENDPTCTRL14
ENDPTCTRL14
0x1f8
ENDPTCTRL15
ENDPTCTRL15
0x1fc
ENDPTCTRLn
ENDPTCTRLn
0
5
0x1c0
0x4
USBPHY
USB Physical Interface
Integrated USB 2.0 PHY
USBPHY
0x8007c000
PWD
PWD
0x0
RXPWDRX
20
RXPWDDIFF
19
RXPWD1PT1
18
RXPWDENV
17
TXPWDCOMP
14
TXPWDVBG
13
TXPWDV2I
12
TXPWDIBIAS
11
TXPWDFS
10
set
4
clr
8
tog
12
TX
TX
0x10
TXCMPOUT_STATUS
23
TXENCAL45DP
21
TXCAL45DP
16
5
TXENCAL45DN
13
TXCAL45DN
8
5
TXCALIBRATE
7
set
4
clr
8
tog
12
RX
RX
0x20
RXDBYPASS
22
DISCONADJ
4
2
ENVADJ
0
2
set
4
clr
8
tog
12
CTRL
CTRL
0x30
SFTRST
31
CLKGATE
30
UTMI_SUSPENDM
29
RESUME_IRQ
10
ENIRQRESUMEDETECT
9
ENOTGIDDETECT
7
ENDEVPLUGINDETECT
4
HOSTDISCONDETECT_IRQ
3
ENIRQHOSTDISCON
2
ENHOSTDISCONDETECT
1
ENHSPRECHARGEXMIT
0
set
4
clr
8
tog
12
STATUS
STATUS
0x40
RESUME_STATUS
10
OTGID_STATUS
8
DEVPLUGIN_STATUS
6
HOSTDISCONDETECT_STATUS
3
DEBUG
DEBUG
0x50
CLKGATE
30
SQUELCHRESETLENGTH
25
4
ENSQUELCHRESET
24
SQUELCHRESETCOUNT
16
5
ENTX2RXCOUNT
12
TX2RXCOUNT
8
4
ENHSTPULLDOWN
4
2
HSTPULLDOWN
2
2
DEBUG_INTERFACE_HOLD
1
OTGIDPIOLOCK
0
set
4
clr
8
tog
12
DEBUG0_STATUS
DEBUG0_STATUS
0x60
SQUELCH_COUNT
26
6
UTMI_RXERROR_FAIL_COUNT
16
10
LOOP_BACK_FAIL_COUNT
0
16
DEBUG1_STATUS
DEBUG1_STATUS
0x70
UTMI_TX_DATA
16
16
UTMI_RX_DATA
0
16
DEBUG2_STATUS
DEBUG2_STATUS
0x80
UTMI_TXVALIDH
22
UTMI_TXVALID
21
UTMI_TERMSELECT
20
UTMI_XCVRSELECT
18
2
UTMI_OPMODE
16
2
UTMI_LINESTATE
6
2
UTMI_SUSPENDM
5
UTMI_RXVALIDH
4
UTMI_RXVALID
3
UTMI_RXACTIVE
2
UTMI_RXERROR
1
UTMI_TXREADY
0
DEBUG3_STATUS
DEBUG3_STATUS
0x90
B_CNT_FSM
28
3
SQ_UNLOCK_FSM
23
3
BIT_CNT
12
10
MAIN_HS_RX_FSM
8
4
UNSTUFF_BIT_CNT
0
8
DEBUG4_STATUS
DEBUG4_STATUS
0xa0
BYTE_FSM
16
13
SND_FSM
0
14
DEBUG5_STATUS
DEBUG5_STATUS
0xb0
MAIN_FSM
24
4
SYNC_FSM
16
6
PRECHARGE_FSM
12
3
SHIFT_FSM
8
3
SOF_FSM
0
5
DEBUG6_STATUS
DEBUG6_STATUS
0xc0
FIRST_EOP_FSM
8
3
EOP_FSM
0
8
DEBUG7_STATUS
DEBUG7_STATUS
0xd0
FIRST_DATA_FSM
28
2
BIT_CNT
24
4
UNSTUFF_CNT
20
3
LD_FSM
16
2
FIFO_FSM
8
6
MAIN_FSM
4
4
EOP_FSM
0
4
DEBUG8_STATUS
DEBUG8_STATUS
0xe0
RX_SIE_FSM
28
4
TX_SIE_FSM
24
4
SHIFT_FSM
8
2
FS_TX_MAIN_FSM
0
7