/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 2.1.7 * XML versions: stmp3600:2.3.0 * * Copyright (C) 2013 by Amaury Pouly * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN__STMP3600__SPDIF__H__ #define __HEADERGEN__STMP3600__SPDIF__H__ #define REGS_SPDIF_BASE (0x80054000) #define REGS_SPDIF_VERSION "2.3.0" /** * Register: HW_SPDIF_CTRL * Address: 0 * SCT: yes */ #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) #define BP_SPDIF_CTRL_SFTRST 31 #define BM_SPDIF_CTRL_SFTRST 0x80000000 #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) #define BP_SPDIF_CTRL_CLKGATE 30 #define BM_SPDIF_CTRL_CLKGATE 0x40000000 #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) #define BP_SPDIF_CTRL_WAIT_END_XFER 5 #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) #define BP_SPDIF_CTRL_WORD_LENGTH 4 #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) #define BP_SPDIF_CTRL_RUN 0 #define BM_SPDIF_CTRL_RUN 0x1 #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) /** * Register: HW_SPDIF_STAT * Address: 0x10 * SCT: no */ #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10)) #define BP_SPDIF_STAT_PRESENT 31 #define BM_SPDIF_STAT_PRESENT 0x80000000 #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) #define BP_SPDIF_STAT_END_XFER 0 #define BM_SPDIF_STAT_END_XFER 0x1 #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) /** * Register: HW_SPDIF_FRAMECTRL * Address: 0x20 * SCT: yes */ #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) #define BP_SPDIF_FRAMECTRL_USER_DATA 14 #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) #define BP_SPDIF_FRAMECTRL_V 13 #define BM_SPDIF_FRAMECTRL_V 0x2000 #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) #define BP_SPDIF_FRAMECTRL_L 12 #define BM_SPDIF_FRAMECTRL_L 0x1000 #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) #define BP_SPDIF_FRAMECTRL_CC 4 #define BM_SPDIF_FRAMECTRL_CC 0x7f0 #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) #define BP_SPDIF_FRAMECTRL_PRE 3 #define BM_SPDIF_FRAMECTRL_PRE 0x8 #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) #define BP_SPDIF_FRAMECTRL_COPY 2 #define BM_SPDIF_FRAMECTRL_COPY 0x4 #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) #define BP_SPDIF_FRAMECTRL_AUDIO 1 #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) #define BP_SPDIF_FRAMECTRL_PRO 0 #define BM_SPDIF_FRAMECTRL_PRO 0x1 #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) /** * Register: HW_SPDIF_SRR * Address: 0x30 * SCT: yes */ #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) #define BP_SPDIF_SRR_BASEMULT 28 #define BM_SPDIF_SRR_BASEMULT 0x70000000 #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) #define BP_SPDIF_SRR_RATE 0 #define BM_SPDIF_SRR_RATE 0xfffff #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) /** * Register: HW_SPDIF_DEBUG * Address: 0x40 * SCT: no */ #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40)) #define BP_SPDIF_DEBUG_DMA_PREQ 1 #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) #define BP_SPDIF_DEBUG_FIFO_STATUS 0 #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) /** * Register: HW_SPDIF_DATA * Address: 0x50 * SCT: yes */ #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) #define BP_SPDIF_DATA_HIGH 16 #define BM_SPDIF_DATA_HIGH 0xffff0000 #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) #define BP_SPDIF_DATA_LOW 0 #define BM_SPDIF_DATA_LOW 0xffff #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) #endif /* __HEADERGEN__STMP3600__SPDIF__H__ */