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5 commits

Author SHA1 Message Date
Aidan MacDonald
e85bc74b30 x1000: GPIO refactor
The GPIO API was pretty clunky and pin settings were decentralized,
making it hard to see what was happening and making GPIO stuff look
like a mess, frankly.

Instead of passing clunky (port, pin) pairs everywhere, GPIOs are now
identified with a single int. The extra overhead should be minimal as
GPIO configuration is generally not on a performance-critical path.

Pin assignments are now mostly consolidated in gpio-target.h and put
in various tables so gpio_init() can assign most pins at boot time.

Most drivers no longer need to touch GPIOs and basic pin I/O stuff
can happen without config since pins are put into the right state.
IRQ pins still need to be configured manually before use.

Change-Id: Ic5326284b0b2a2f613e9e76a41cb50e24af3aa47
2021-06-06 11:06:14 +00:00
Aidan MacDonald
3f26fcf340 FiiO M3K: New bootloader
SPL and UCL-compressed bootloader are now packed into one output,
bootloader.m3k, eliminating the separate SPL build phase.

The Rockbox bootloader now has a recovery menu, accessible by
holding VOL+ when booting, that lets you back up, restore, and
update the bootloader from the device.

Change-Id: I642c6e5fb83587a013ab2fbfd1adab439561ced2
2021-05-12 10:35:20 +00:00
Aidan MacDonald
20fc928221 x1000: Centralize common definitions, memory layout
Change-Id: I8daad058ae55d4b750b1ae407153e4917de5d095
2021-04-28 20:04:10 +01:00
Aidan MacDonald
01d1eb4258 FiiO M3K/X1000: Do system clock initialization in the SPL
Initializing the clocks in the SPL brings Rockbox in line with
how the FiiO M3K's original SPL works. It's likely other X1000
devices do this too.

There was a logic error in the previous setup: the code falsely
assumed that DDR memory would always be running from MPLL, but
it would be switched to APLL by the bootloader. Rockbox would
then try to re-init APLL, albeit with the same parameters. Maybe
this was the cause of the boot hang on some units.

Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
2021-04-17 20:24:07 +00:00
Aidan MacDonald
1b8542490d x1000: Redesign SPL, and allow it to flash the bootloader
SPL is now designed so core X1000 code is in control of the boot,
under the reasonable assumption that the device boots from flash.
It should not be too hard to adapt to other X1000 ports.

The biggest functional change is that the SPL can now read/write
the flash, under the control of a host computer. The SPL relies
on the boot ROM for USB communication, so the host has to execute
the SPL multiple times following a protocol.

Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
2021-04-17 20:22:49 +00:00
Renamed from bootloader/fiiom3k-spl.c (Browse further)