This was spotted while playing with qemu-jz:
1) rockbox reads TECR and TESR which are described as write-only
registers. Datasheet doesn't mention what happens if they are
readed. Apparently this doesn't have fatal side effects.
It comes down to two defines from jz4740.h
__tcu_stop_counter(n) and __tcu_start_counter(n) which use
read-modify-write sequence.
2) rockbox accesses out of bound offset 0xd4 in DMA memspace.
It comes from dis_irq() in system-jz4740.c. NUM_DMA is 6 but
DMA channels are 0-5 so (irq <= IRQ_DMA_0 + NUM_DMA)) bound
check is wrong.
This are *NOT* tested on device.
Change-Id: I29dff6a4f828030877b7d50fbcc98866478b9e3d
Reviewed-on: http://gerrit.rockbox.org/338
Reviewed-by: Bertrik Sikken <bertrik@sikken.nl>
Tested-by: Purling Nayuki <cyq.yzfl@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This patch adds to YP-R0 (and other future targets using Linux
framebuffer) the ability to use LCD_ENABLE to save some CPU cycles
while display is powered off.
This patch also changes the way to toggle LCD power: now using
a proper ioctl call, slightly more efficient.
Change-Id: I544de77f5abd4ac1c13d3fe3a6e40a30f7c0bece
Reviewed-on: http://gerrit.rockbox.org/410
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
The GPIO device file wasn't closed due to this. This wasn't a big deal
because the device powers off shorty afterwards anyway.
Change-Id: I9a6b4d57d32627157323b4883e47b8812f5dcb4d
As per title this patch aims at splitting common target
code and specific target code in a better way to
support future ports within the same environment
(e.g. Samsung YP-R1 where the Linux and the SoC
are the same, with differences in hardware devices
handling)
Change-Id: I67b4918c46403b184d3d8f42ab5aae7d01037fd0
Reviewed-on: http://gerrit.rockbox.org/409
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
If DRMODE_FG now the alpha channel in bitmaps can be used to draw the bitmap
over the framebuffer, so that e.g. a line selector isn't cleared for
for transparent bitmap pixels.
Change-Id: I09d59a09d2f3c90450a0fe2b83c6c59d757b686b
By saving current_vp fields into temp vars just before the loop gcc can
put them into registers. This yields ~15% speedup for drawing anti-aliased fonts.
Change-Id: I4c0c9f5ff7a7f084e2eb08c4ed874176b1f9832c
The comment about the format was actually incorrect. The alpha information
is now negated during conversion to native format, according to the
corrected comment.
Change-Id: Ifdb9ffdf9b55e39e64983eec2d9d60339e570bd9
commit_discard_dcache_range() is used in sd, lcd and pcm drivers
to handle transfers form/to data buffers so this should not introduce
any problems. It is reported to fix pop noise observed on some hifimans.
We apparently don't fully understand cache handling on this platform.
Change-Id: I436d291509f91d16a13d10965a28171fb27574ab
The build of bootloader with HAVE_ATA_DMA fails because of missing
commit_discard_dcache(). This seems to be bigger problem as
bootloader builds don't call cache_init() also which seems wrong.
but I know too little about the PP platform to judge.
For now use ATA DMA only in regular builds.
Change-Id: I82873cb1771f5a95ebfbef91ce26744e3abd743c
PP502x ATA DMA was disabled in 55fab77 because it caused various
instability on all targets using it. This instability is fixed in
583c948 via FS#12391. Here, ATA DMA is enabled for all PP502x targets
except nano1g and hdd6330. For nano1g, there may be other causes of
instability and more testing is needed. ATA DMA does not work on hdd6330.
Change-Id: I786b9edb19e74e6eb957ab205ea026f0969200ac
Reviewed-on: http://gerrit.rockbox.org/340
Tested-by: David Hooper <dave@beermex.com>
Tested-by: Boris Gjenero <boris.gjenero@gmail.com>
Reviewed-by: Szymon Dziok <b0hoon@o2.pl>
Tested-by: Szymon Dziok <b0hoon@o2.pl>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
In commit_discard_idcache(), cache lines were marked as invalid. When
some cache lines are marked as invalid, memory corruption can occur.
This caused instability when using PP502x ATA DMA because of the many
more calls to that function. Here, commit_discard_idcache() is changed
to avoid the problem. Also, the cache is filled after being enabled to
to ensure there are never any cache lines that aren't marked as valid.
Change-Id: Ia26300acef6b0573c1f40299c496ee5cbda3dac8
Reviewed-on: http://gerrit.rockbox.org/339
Reviewed-by: Szymon Dziok <b0hoon@o2.pl>
Tested-by: Szymon Dziok <b0hoon@o2.pl>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
The SD driver doesn't initialised drives at the beginning but
upon request to handle removable drives. Since means that the
init should call init_drive() and not init_sd_card() otherwise
the check for WINDOW flag is bypasses. This breaks the zenxfi3
bootloader and has been overlooked for some time.
Change-Id: I7325f7164d16d7e7e54eeb4645e98517a08e0836
Move to a table based approach (scales better) and distinguish
between upward changes (increase frequency) and downward changes
(decrease frequency). This provides a better ordering of
operations and in particular it allows to avoid changing the
regulator while running at low speed since it takes a long time !
This should result in a much smoother scaling.
Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
For some reason it is the responsability of the driver to send
this event so do it. This might fix some non-updating screens.
Change-Id: Ib5fdc94bf266c3497a8ac4e89d0418c0e876ff9f
The lcd kind is always set to st7783 in case we can't read the ID
so don't bother handling impossible cases
Change-Id: I352fd43b26068b460e69190d37c4cd4627e1db9a
The flip and invert settings can potentially be reset to their
value accross a disable/enable cycle, so save the value of the
impacted registers and apply it after each enable. Also avoid
poking registers when the lcd is not on.
Change-Id: Ica98f166c060aade7eb205f5628b58aae692024f
When chaging the cpu and memory frequency we need to disable the
external memory interface (EMI) for a small time. This can
underflow the dma and cause some breakage. Hopefully the SSP
controller handles this gracefully by stopping the clock and the
I2C probably handles this naturally because the clock can be
streched anyway. However the LCDIF has a special setting for this
which needs to be enable, otherwise it will send garbage to the
LCD. No other block is known to suffer from this currently but
this issue might have more unexpected consequences.
Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
pcm_dma_apply_settings(): sets the configured PCM frequency,
all native CS42L55 sample rates are available.
Change-Id: I2fcd5581457a669c3044516804cb64fb972218d0
Actually Rockbox does not use this mode, it is supported by
other iPods, so implemented on Classic as well.
Change-Id: Ia6578506df27a95a7f7522b3034b764631a8bb3a
Scale battery voltage ADC readings by 1023 instead of 1000,
using ADC1 (substractor) instead of ADC0 (multiplicator) to
get better resolution.
Percent charge/discharge tables are also modified to return
a similar value than the old ones.
Change-Id: I2951c75faa02f4302599ec24f9156cfd209c36eb
Fixes missing Settings - General Settings - System - Disk - Spindown
setting.
Change-Id: Iae686598dfd7ad4ca1faf8db9f1271e7808de752
Reviewed-on: http://gerrit.rockbox.org/376
Reviewed-by: Michael Giacomelli <giac2000@hotmail.com>
Tested-by: Michael Giacomelli <giac2000@hotmail.com>
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
Do low level power init in system_init(). This can be needed
since imx233 must be able to frequecy scale atfer system_init()
and kernel_init() and this is only possible if power system was
initialised.
Change-Id: I27c66ec0dccd60bda26a45be24683c0bfe72c6da
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
