Commit graph

17 commits

Author SHA1 Message Date
Amaury Pouly
06c94740e5 imx233/fuze+: prepare target to enable MMU
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30199 a1c6a512-1295-4272-9138-f99709370657
2011-07-23 11:45:18 +00:00
Michael Sparmann
152847977a New port: iPod Classic (also known as iPod 6G/6.5G/7G)
Major known issues:
- No bootloader yet
- No support for the first-generation 160GB CE-ATA hard disk drive yet
- Audio playback is slow, only FLAC seems to reach realtime


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28953 a1c6a512-1295-4272-9138-f99709370657
2011-01-02 23:16:27 +00:00
Thomas Martitz
dd5dd8cfd9 Rename cache coherency functions.
The old cache coherency function names where wrong and misleading.
The new names are (purposely different from vendor manuals)
*  commit_* (write-back only)
*  discard_* (removing lines from cache only)
*  commit_discard_* (write-back and removing lines from cache)

It's suspected the old names have led to wrong uses. The old names still exist
(as aliases) so every call via the old names need to be double checked and changed
to the new name.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
2010-09-08 17:05:49 +00:00
Bertrik Sikken
a5248a2995 Update Samsung YP-S3 bootloader demo
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26417 a1c6a512-1295-4272-9138-f99709370657
2010-05-30 21:43:14 +00:00
Rafaël Carré
5ea1fe614a cpucache_invalidate: use bx reg instead of mov pc, reg to return
Using BX has the effect to set the T bit, so it can return to a thumb
function

With this change, rockbox runs fine on Clipv2 built with -mthumb (for
most files which don't use inline 32 bits ARM assembly)

Some other places use code which change the T bit on armv5 but not on
armv4 so armv4 won't run

See FS#6734

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26386 a1c6a512-1295-4272-9138-f99709370657
2010-05-29 17:12:42 +00:00
Rafaël Carré
d556f26820 as3525: use DMA for recording
Flyspray: FS#11257

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25980 a1c6a512-1295-4272-9138-f99709370657
2010-05-13 05:26:12 +00:00
Rafaël Carré
f6ae574ac6 s5l870x : use mmu-arm.S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:59:49 +00:00
Rafaël Carré
635de60ff3 mmu-arm.S: comment out dump_dcache_range()
It is only used by gigabeats, and is defined in mmu-armv6.S already

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25630 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:22:01 +00:00
Rafaël Carré
96e97987d9 mmu-arm.S: disable MMU functions on CPUs which don't use them
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25629 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:17:08 +00:00
Rafaël Carré
4205a508d7 mmu-arm.S: Use correct implementations on arm926ej-s CPUs
clean_dcache and invalidate_dcache were incorrect and too tied to the
arm920t/arm922t 64-way set associative caches

Make those functions smaller on as3525, as this CPU has a smaller cache
than the gigabeat F/X

Flyspray: FS#11106
Authors: Jack Halpin and myself

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25628 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 15:04:55 +00:00
Rafaël Carré
2f97effab9 mmu-arm* : cpucache_invalidate() needs to be in IRAM for rolo
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25627 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:29:37 +00:00
Rafaël Carré
208dc249e6 mmu-arm (v4/v5) : fix previous commit, clean/invalidate correctly the first segment in each loop
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25626 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:15:37 +00:00
Rafaël Carré
a0e1e329f7 mmu-arm (v4/v5) : use one less instruction in invalidate_dcache/clean_dcache
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25625 a1c6a512-1295-4272-9138-f99709370657
2010-04-13 14:12:54 +00:00
Rafaël Carré
735b522929 Split ARMv6 code from mmu-arm.S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23244 a1c6a512-1295-4272-9138-f99709370657
2009-10-18 13:07:14 +00:00
Michael Sparmann
3ac50ca9ff Fix S5L870x cache coherency functions. They were split into a different file, as changes were needed all over the place.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
2009-10-17 23:06:45 +00:00
Michael Sparmann
a931acd3ab Added S5L870X cache coherency support
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23058 a1c6a512-1295-4272-9138-f99709370657
2009-10-09 21:41:57 +00:00
Michael Sevakis
63e709c7c8 Refine the routines in mmu-arm.c and move them to mmu-arm.S since the code is now 100% assembly.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19980 a1c6a512-1295-4272-9138-f99709370657
2009-02-11 23:56:00 +00:00