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17 commits

Author SHA1 Message Date
Michael Sevakis
940e8990b5 PP502x: Make RAM physical addresses uncached. Cache the flash ROM on targets with one. Kill all the now unneeded cache flushing and i2s tweaking on e200 so clicking is no worry. Write the driver framebuffer at uncached addresses. Recording monitoring may be a little noisy in the left channel for the moment when not boosted and will be addressed. All seems to work as advertised including flash ROM dump. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14976 a1c6a512-1295-4272-9138-f99709370657
 2007-10-04 04:53:01 +00:00
Michael Sevakis
da55251a35 Compile Portal Player bootloaders as single core. Cleanup the startup code for bootloaders. Remove cop stack entirely and keep IRAM use down on all relevant targets - just use the 128-byte idle stack. Use the inline asm version of current_core for pp5002 as well. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14898 a1c6a512-1295-4272-9138-f99709370657
 2007-09-29 06:17:33 +00:00
Michael Sevakis
a13a1d5492 Anti-red: No need for COP initialization in the bootloaders nor idle stacks. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14880 a1c6a512-1295-4272-9138-f99709370657
 2007-09-28 10:54:27 +00:00
Michael Sevakis
7914e90738 Commit a subset of the dual core changes that have to do with cache handling, stacks, firmware startup and thread startup. Tested on e200, H10-20GB, iPod Color and 5.5G. Thread function return implemented for all targets. Some changes to plugins to follow shortly. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14879 a1c6a512-1295-4272-9138-f99709370657
 2007-09-28 10:20:02 +00:00
Karl Kurbjun
67ef4500e3 More interupt/timer work 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14823 a1c6a512-1295-4272-9138-f99709370657
 2007-09-22 23:17:52 +00:00
Catalin Patulea
c3126e0f3c m:robe 500i port: Add primitives for the SPI bus and start moving toward new-style register definitions. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14798 a1c6a512-1295-4272-9138-f99709370657
 2007-09-21 09:06:02 +00:00
Jonathan Gordon
bdf4d3927c Hopefully fix all the errors/warnings 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14764 a1c6a512-1295-4272-9138-f99709370657
 2007-09-20 08:01:56 +00:00
Karl Kurbjun
7b97fe21c0 Beginning of an M:Robe 500i port. Currently only in the bootloader stage. Needs another piece of code to start the boot process - will be in the wiki. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14763 a1c6a512-1295-4272-9138-f99709370657
 2007-09-20 04:46:41 +00:00
Barry Wardell
2fc19497fc PP502x: Clock setup cleanup. 
* Prepare sleep mode by adding CPUFREQ_SLEEP, as was done previsouly with PP5002. This is already confirmed working on PP5020 (H10), PP5022 (mini2g) and PP5024 (Sansa), but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode.
* Simplify set_cpu_frequency() somewhat to make it more like the PP5002 version.


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14106 a1c6a512-1295-4272-9138-f99709370657
 2007-07-31 20:48:49 +00:00
Jens Arnold
1bc3b7feb2 PP5002: Clock setup cleanup. * Switch to 80MHz when boosted like on the other PP targets. * Prepare sleep mode by adding CPUFREQ_SLEEP. This is already confirmed working, but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14096 a1c6a512-1295-4272-9138-f99709370657
 2007-07-31 10:56:50 +00:00
Jens Arnold
8d3ac97aff Clean up PP502x CPU clock setup code and use the full 80MHz when boosted. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14004 a1c6a512-1295-4272-9138-f99709370657
 2007-07-26 15:07:16 +00:00
Dave Chapman
ebc076bc15 Remove the hack which read the ipod hardware revision from flash in the bootloader and passed it to Rockbox via a fixed address in SDRAM. Rockbox now remaps flash and so can just read the value itself. Also clean up the debug menu a little - only display the hw revision for ipods, and add the lcd_type variable to indicate the type of LCD (0 or 1) for ipod Color/Photo. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13986 a1c6a512-1295-4272-9138-f99709370657
 2007-07-25 13:12:38 +00:00
Jens Arnold
fe23dc8f15 Improved CPU clock setup for PP502x. PP5020 and PP5022 are not register compatible here, so define the PP5022 targets properly, and introduce a CPU_PP502x macro for easier family check. Improves stability on PP5020 (less freezing, tested with Mini G1) and reduces clock change penalty (500us on PP5020; uses the relock bit on PP5022). 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
 2007-07-02 05:16:40 +00:00
Michael Sevakis
d803cf5e4e Heh. Better way to load the PROCESSOR_ID address. Thanks Thom. :) 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13156 a1c6a512-1295-4272-9138-f99709370657
 2007-04-14 11:46:05 +00:00
Michael Sevakis
036168cbf9 PP5020/PP5024: Add ASM optimized inline current_core. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13155 a1c6a512-1295-4272-9138-f99709370657
 2007-04-14 11:15:43 +00:00
Michael Sevakis
20c6bf50fe Do the target shuffle again a better way by including from higher levels 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13151 a1c6a512-1295-4272-9138-f99709370657
 2007-04-14 01:18:06 +00:00
Michael Sevakis
d95c39072a Portal Player: Add invalidate_icache and flush_icache. Flush the cache on the core for newborn threads. In doing so, move more ARM stuff to the target tree and organize it to make a clean job of it. If anything isn't appropriate for some particular device give a hollar or even just fix it by some added #ifdefing. I was informed that the PP targets are register compatible so I'm going off that advice. The Sansa likes it though. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13144 a1c6a512-1295-4272-9138-f99709370657
 2007-04-13 20:55:48 +00:00