Queue power off requests because power_off() can be called within tick
context that must not acquire mutex.
Change-Id: I6f1a8f81d15518876cd03556118fc9eb37b8175f
Import non-free firmware image from linux-firmware package.
Firmware loading works but is disabled at compile time because just
loading firmware without configuring device results in higher power
consumption without any benefit to end user.
Change-Id: I8fd252c49385ede1ea4e0f9b1e29adeb331ab8ae
This new design saves on binary size and stack usage. The API is
also block- and page-based, requiring awareness of the chip layout
to use properly. Out-of-band areas are also exposed for reading
and writing.
The byte-oriented routines are kept for compatibility with the
existing installer and SPL.
Change-Id: Iaacc694d2f651ab74d45330e0434ee778a0d91bc
Waiting 10 us between selecting slave and transmitting data on SPI
resolves spurious startup glitches.
Cache last read monotime value as it can differ from the first one.
Change-Id: Ia6ac5696f6ee2bc3c6a8be27e33aaddd9ff4ce2a
Read monotime twice in a row and only accept the value if it matches or
the two reads are 1 second apart.
Change-Id: Ibd289103a20404dd1b2bbd131fdfa8905852c788
AVR requires bigger delays between retries. Read state instead of
version for synchronization purposes as it shifts more bytes.
Change-Id: Ib7fa980496d3bc7744a086b45e1865861ef58b88
If the commands repeatedly fail it is likely that the AVR is not
programmed. In such case simply continue normal operation. This is
especially important in bootloader as it makes it possible to load new
rockbox build using bootloader USB mode. Otherwise, the only recovery
option would be to use I2C serial.
Change-Id: I4b0999833e9a906ec6353bdfdd5b68211f07ac81
Use 32-bit monotime AVR counter for time tracking. Set the time by
adding fixed offset to the counter value. Store the offset in rockbox
directory to make it persistent between reboots.
Do not implement alarm functionality as wakeup is only possible from
sleep and not from complete power off.
Change-Id: I615c7eb4df8ab0619dcbfcff107bc7051a15aace
Keep Slave Select active during command transmission. This relaxes
timing requirements on the AVR side.
Change-Id: Ia1a6cf45aba3c11f6aeaa7441c6793807ca827f0
Add defines for all commands handled by AVR, including the unknown
opcodes (0xC5, 0xD3, 0xD4, 0xD5, 0xD6).
Properly synchronize with AVR and keep repeating command until it looks
like AVR has accepted it.
Change-Id: I3d42e973f135e33092c71c9887421906a900ab58
This uses an equivalent algorithm but with a different initial value
than we normally use (all bits off vs all bits on). Use the new crc_32r
to replace the original MI4 crc32 implementation.
This frees up some extra space on mi4 targets which gives us more
room on a few very space constrained targets (sansa c200/e200, etc).
Change-Id: Iaaac3ae353b30566156b1404cbf31ca32926203d
Consider battery level down to 0 as safe as OF continues to operate
normally even when at level 0.
Change-Id: Ie3889e5662b9fa6588e20ad02d8953f29e28800c
Wait on semaphore until DMA finishes instead of busy waiting. This
allows the CPU to be used by other tasks during transfers.
Increase peripheral clock frequency, divide AHB by 2 instead of 3.
Function clock frequency is AHB divided by MMC divider + 1.
Change-Id: Ic890634da7e3541962ea3501eae8fa2ca2db606a
- Missing mutex unlock in nand_open()
- SET_FEATURE command incorrectly issued as a read operation
- Inverted protection bits, not sure how that happened...
- Block erase skipped ahead by a wrong amount, causing erases
spanning multiple blocks to erase the wrong blocks
This code was buggy as hell... it's in need of a major overhaul.
It's not very flexible or reliable, and access to the flash is
useful during development of a new port, even if not useful once
the port is complete.
Change-Id: Ib85ee7453beab9657e3d19798ebaa09174b3649e
Disabling double buffering results in expected CPPI TX behaviour. With
the double buffering enabled, sending single ZLP resulted in two ZLPs
being available. The two ZLPs is problematic because this causes Windows
to reset USB device after failed SCSI command.
The problematic sequence on Windows 10 was as follows:
* Host sends SCSI Mode Sense(6) Informational Exceptions Control(0x1C)
* Device sends ZLP
* Device sends command failed response
With endpoint double buffering enabled the ZLP was read twice by host.
As host was expecting command response on the second read (and got ZLP
instead), host attempts recovery by resetting USB device and retrying.
Change-Id: I64e95998f429ffb7b14143d956b1f29d20218d14
Allows for the i2c boilerplate to be shared between the M3K and
Shanling Q1 ports. M3K-specific quirks remain in button-fiiom3k.
Change-Id: I8879b603cefc16416bb200f1c484ca916d935c6a
Acknowledge SYS_USB_CONNECTED in all queues so USB task can gain
exclusive access to the storage.
Reduce CPPI requeue timeout to speed up disk access.
Change-Id: I322aae4cac679696bb8186ccacf838a18f0715e9
Correctly set endpoint maximum packet size so host will not consider
end of transfer after receiving first packet when transfer is larger
than 64 bytes (at High Speed the endpoint max packet size was set to
64 but according to descriptor it is 512).
Split DMA transfers up to CPPI_MAX_FRAG so we get single interrupt
after each call to tnetv_cppi_send().
Change-Id: I385b66bc5d71975a4e3e9167efac0b1334bd3ffc
Return complete R2 response to caller. Due to incorrect bitfield
handling only bits [127-96] were ever returned to caller.
Change-Id: I83726af35fb24a8051fcca8b8d019ad89d17500e
I had hoped this would fix FS#13297, but no luck. Might as well
do this change anyway, because it's the "right" thing to do.
Change-Id: I55819c881d2141dd565e1c1f21460578c9114ff6
Avoids having to #define the names of GPIO pin interrupt handlers,
as they can now be set at runtime instead.
Change-Id: Ib5da1bdb475ff7b64280fe7cdd00adab63389152
The GPIO API was pretty clunky and pin settings were decentralized,
making it hard to see what was happening and making GPIO stuff look
like a mess, frankly.
Instead of passing clunky (port, pin) pairs everywhere, GPIOs are now
identified with a single int. The extra overhead should be minimal as
GPIO configuration is generally not on a performance-critical path.
Pin assignments are now mostly consolidated in gpio-target.h and put
in various tables so gpio_init() can assign most pins at boot time.
Most drivers no longer need to touch GPIOs and basic pin I/O stuff
can happen without config since pins are put into the right state.
IRQ pins still need to be configured manually before use.
Change-Id: Ic5326284b0b2a2f613e9e76a41cb50e24af3aa47
Port USB driver from Sansa Connect Linux kernel sources. The device
successfully enumerates and responds to SCSI commands but actual disk
access does not work. The SCSI response sent to host mentions that both
internal storage and microsd card are not present.
Change-Id: Ic6c07da12382c15c0b069f23a75f7df9765b7525
Modify count, buffer and start address only after successful transfer.
This makes the retry operation to use the same address and buffer as the
just failed transfer.
Change-Id: I4f49bbdc861d634e33ea5e939a9693474411d24d
- Use unsigned bitfields in 'lcd_tgt_config'
- Set DTIMES when using an 8-bit bus width
- Allow using DMA big-endian mode
- Provide an #ifdef to avoid stopping DMA in the middle of a frame
- Correctly #ifdef LCD sleep code when target does not implement it
Change-Id: I327c6b05223638b876d5ab62cb6e48f82e6d5fa5
- Change busy loop to wait on the timer flag instead of hoping to
catch the timer at exactly the right moment... unsurprisingly,
that did not work well with higher frequency PWM outputs.
- Put GPIO data into a dedicated const array.
Change-Id: I2a920ed265c192da197a18c7242f3205d11636d3
The old name was a bit misleading. AXP173 is sort of the lowest common
denominator of a series of related chips. The M3K uses an AXP192 which
has a few extra features vs. the AXP173.
New voltage regulator stuff was added for the sake of the Shanling Q1
native port (that player also uses an AXP192).
Change-Id: Id0c162c23094bb03d13fae2d6c332e3047968d6e
- Drop obsolete NAND patch script (it's simpler to use 'dd' directly)
- Remove an outdated comment
- Fix missing 'void' in a function definition
- Reset the poweroff timer when we poke the backlight
Change-Id: I752624386f30ac95f41a731d2b6be837e12275a9
Some audiohw API calls are shared between playback and recording,
eg. frequency settings. Implementing these in the DAC driver won't
work for the M3K, as it uses a separate codec for microphone input.
Change-Id: Ieb0a267f8a81b9e2bbf0bbca951c5778f8dcd203
I think this covers everything now, although some fields are missing
enum values. Those can be added in if and when they are needed.
Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f
- Add support for skip and seek while the player is locked.
(Thanks to @bahus for the suggestion)
- Fix touch zones because the down button zone ended up being
a lot smaller than expected due to the touchpad's wonkiness.
Also added a visual display of the touchpad to its debug menu.
- Fixes the pictureflow keymap because it was mostly unusable.
Change-Id: Ic0da4f8df3613ff7828ce1cb940ed9e77ada3281
Clearing recoverzap parameter exists the Recovery Mode. This makes it
possible to run Rockbox on Sansa Connect without relying on original
Linux firmware.
Enable write-through cache on flash memory as write-back complicates
handling without any real benefits. The flash memory accepts commands
as series of writes at predefined addresses, so it is important that
the cache does not interfere with the writes.
Change-Id: I219f962f20953d84df43012cf16bbb16d673add8
SPL and UCL-compressed bootloader are now packed into one output,
bootloader.m3k, eliminating the separate SPL build phase.
The Rockbox bootloader now has a recovery menu, accessible by
holding VOL+ when booting, that lets you back up, restore, and
update the bootloader from the device.
Change-Id: I642c6e5fb83587a013ab2fbfd1adab439561ced2
- Removed unnecessary layers of generic code
- Software ECC is gone since we don't need it now (and maybe not ever)
- Removed bounce buffering, so callers must now align buffers
Change-Id: I33fbac9d9d12a4657980b8618c7d62bfa91e2ea0
This overwrote the first 2 instructions of crt0 in the bootloader!
I'm really not sure how this *didn't* cause a fatal exception.
This address isn't special as far as I know, so just move it to the
TCSM by making it a static variable.
Change-Id: I58e1486804aeb2b68325e8de2aa1874c97abef19
The abiflags data is only used to communicate ABI information to a
program loader -- you can see what info is stored with readelf -A.
Dropping it shaves 24 bytes off of every binary (including plugins).
Change-Id: Iae78eeffe5c840ff67717707fb94821d24aac8ec
It never worked, and hasn't compiled in something like a decade, Given
the HW capabilities (limited onboard flash, no expandability) there's
really no point in trying to fix/complete it.
Change-Id: I7d175089840396f8891645bd10010d730dd5bfdc
They were never finished, never saw any release ever, and haven't
compiled for the better part of a decade. Given their HW capabilities [1],
they are not worth trying to fix.
[1] 1-2MB RAM, ~256MB onboard flash, no expandability
Change-Id: I7b2a5806d687114c22156bb0458d4a10a9734190
There's absolutely no way for gpio_config() to get called from two
different threads due to the co-operative threading model, and it
is unsafe to call from IRQ context no matter what we do.
Change-Id: I58f7d1f68c7a414610bb020e26b774cb1015a3b0
Using a macro to put each function in its own .icode-based section
allows us to put the functions in IRAM _and_ have linker GC. This
removes a troublesome #ifdef BOOTLOADER_SPL on the X1000 target.
Change-Id: Ia7b59778f5c36b7970dee4280547e434a1f4fc5a
This only required a minor patch to the usb-designware driver due
to DMA requiring physical addresses -- on the X1000, these differ
from virtual addresses so we have to do the usual conversion.
Both the mass storage and HID drivers work, but there are a few
issues so this can't be considered 100% stable yet.
- Mass storage might not be detected properly on insertion,
and USB has to be replugged before it shows up
- HID driver may occasionally panic or hang the machine
Change-Id: Ia3ce7591d5928ec7cbca7953abfef01bdbd873ef
- Added register names to reduce usage of magic numbers
- Added function to control max charging current, needed for USB
- Corrected comment about axp173, since FiiO M3K has an axp192
Change-Id: I6604ce8d44e5a2ee84061cf042d17ccc4734ac57
After conducting some simplistic tests, I found that the power usage
did not appear to be affected by the CPU frequency.
I tested by playing back a 44.1 KHz FLAC file on single track repeat,
and measured current with the AXP173's battery discharge current ADC.
The button and LCD backlights were set to always on. Headphones were
unplugged and the volume was muted to eliminate any influence from
the headphone amp.
On average the current usage was between 78-81 mA at 1008 MHz, 252 MHz,
and 112 MHz. If anything, 1008 MHz drew _less_ current than the lower
frequencies, by about 1-3 mA.
A possible explanation for this, assuming it's not just a bias of the
test, is that the CPU idle state saves so much power that it's better
to maximize the real time that the CPU spends idling. More systematic
testing is needed to confirm this.
Change-Id: I527473e8c4c12bc1e94f8d4e849fecc108022abe
There's no point including this in normal builds: the stats are not
used for anything, they are not really of interest to anyone except
developers, and add a small overhead to the kernel tick.
Change-Id: I1b4f67cc62d11d634a8cec279dca513dd10eea96
Initializing the clocks in the SPL brings Rockbox in line with
how the FiiO M3K's original SPL works. It's likely other X1000
devices do this too.
There was a logic error in the previous setup: the code falsely
assumed that DDR memory would always be running from MPLL, but
it would be switched to APLL by the bootloader. Rockbox would
then try to re-init APLL, albeit with the same parameters. Maybe
this was the cause of the boot hang on some units.
Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
What we really want is to avoid any interrupts being generated
before the drivers which handle them are properly initialized.
Intead of trashing all GPIOs, search for the problem pins and
fix them, leaving the others alone.
This fixes the M3K's button light flickering on boot and should
stop the M3K from entering a potentially confusing "dead" state
where all the lights are off but the CPU is still on.
Change-Id: I13a6da0f0950190396bff5d6e8c343c668e8fea1
SPL is now designed so core X1000 code is in control of the boot,
under the reasonable assumption that the device boots from flash.
It should not be too hard to adapt to other X1000 ports.
The biggest functional change is that the SPL can now read/write
the flash, under the control of a host computer. The SPL relies
on the boot ROM for USB communication, so the host has to execute
the SPL multiple times following a protocol.
Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
Detection at startup is proving to be unreliable. Even if card is not
present at startup, upon insertion it will sort itself out properly.
Change-Id: I9ee90b724c90c530a39264f698c200a48aa72b1d
Including direct use of the external SD card mount
Known issue: If SD card is inserted at startup, it must be
ejected and reinserted to be registered.
Change-Id: I5f420160bda32135cbb088c1e8b04b6e3a73018e
The X3's line out is a bit hot, at ~4.3Vpp, so allow it to be backed off.
(On my X3, backing it off to -6dB brings Vpp down to ~3.4V)
Change-Id: Iea38ef1c6a1b183d0f8fb4eaf2bf9ed6b350a532
- Proper error codes are now returned from all functions. These codes will
be used by a host-side flash tool for error reporting.
- nand_erase_block() was replaced by nand_erase_bytes(). The caller can't
know how big an eraseblock is with the current API, so next best thing
is to verify the correct alignment inside the call and reject the erase
if it isn't properly aligned.
- Fixed typo in nandcmd_block_erase() which would cause an SFC error to be
interpreted as success. Yikes.
Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
headphone ADC thread stack was slightly too small. Bump it up a bit.
(it was _perfectly_ sized for the prior older toolchain+optimization flags...)
Change-Id: I2ca67c2b85c54f879892a31e281d7696f893389c
Use of IF_COP_CORE was mistakenly introduced as part of 89acde6af2,
effectively short-circuiting multiple tests resulting in the code
paths always being executed, on both cores.
Use the correct macro, so per-CPU paths are handled properly.
Change-Id: Id346cf759fc1b06b7d56694d7af1f469caf785a4
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Enable its use in the jz47xx MIPS targets.
(accidently committed g#3249 before making these changes)
Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
* PREV/NEXT now swapped so they do what is expected in most contexts
* List and setting context retains prior behavior
* Enable the ADC that reads the headset remote and map the keys.
* As ADC-based remote "events" arrive as press/release pairs,
delay the button release.
Change-Id: I22d4eac3bfe1573b50eca795cf377bdafdeb5336
affects all hiby targets, fiiom3k, and ibasso dx50/dx90
As well as deduplicating a small pile of code, this also implements
hysteresis so we're not doing a sysfs read/lookup multiple times
back-to-back every time the power management tick fires.
Change-Id: I2f7672acbb36341becf67e07960c24c681270d09
Previously these were placed in DRAM, which is overwritten by RoLo
when it loads a new image, but RoLo must call commit_discard_idcache()
after loading the image.
Change-Id: I5dcc4ca711b774166f83c668695edbcabfab2604
The filesystem API often passes in unaligned receive buffers, and some
code (eg BMP reader) processes data in-place, leading to data loss when
we dropped the cache.
(And document exactly what we're doing, so we don't go through this again
at $future_date)
Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.
It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.
Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
- The range-based cache operations on MIPS were broken and only worked
properly when BOTH the address and size were multiples of the cache
line size. If this was not the case, the last cache line of the range
would not be touched!
Fix is to align start/end pointers to cache lines before iterating.
- To my knowledge all MIPS processors have a cache, so I enabled
HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
the CACHEALIGN_UP/DOWN macros.
- Make jz4760/system-target.h define its cache line size properly.
Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
ATA DMA was enabled for all PP502x targets in d118f47 after previously reported instabilities were thought to have been fixed. The iPod 4G target remains unstable when UDMA 2 is enabled. File system corruption will eventually occur even using stock hardware in normal usage, according to both my own experience and that of several other forum users. UDMA 1 appears to be stable.
Change-Id: I8526bad9e879f5dad5174cfe07cd8828d8b72406
Basically no longer treat SCROLL_FWD/BACK as "button" events, instead
relying on the scrollwheel hooks to handle things properly.
Change-Id: I9bf18595ab3ca68e912f6dfb1f2eac2544578e73
