Commit graph

5 commits

Author SHA1 Message Date
Amaury Pouly
eac1ca22bd imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-28 16:49:22 +02:00
Amaury Pouly
55c5c7ea66 imx233/emi: cleanup and don't change emi freq if not needed
Change-Id: I19f633a85bb12f880215905482934e34da549a13
2014-06-24 18:07:56 +02:00
Amaury Pouly
659febc749 imx233: add emi debug info
Change-Id: I33317ae26b70c825d4c5e3aaac364da5e0dc06c2
2013-07-07 17:36:20 +02:00
Amaury Pouly
e6a931301f imx233: rewrite emi using new register headers
Change-Id: Ie893162aac38ea3aaf73b4e84e54be714a5fc33f
2013-06-16 15:30:46 +02:00
Amaury Pouly
5aa19f3eeb imx233: implement emi frequency scaling (disabled by default)
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.

Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
2013-01-10 00:51:35 +00:00