Move to a table based approach (scales better) and distinguish
between upward changes (increase frequency) and downward changes
(decrease frequency). This provides a better ordering of
operations and in particular it allows to avoid changing the
regulator while running at low speed since it takes a long time !
This should result in a much smoother scaling.
Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
For some reason it is the responsability of the driver to send
this event so do it. This might fix some non-updating screens.
Change-Id: Ib5fdc94bf266c3497a8ac4e89d0418c0e876ff9f
The lcd kind is always set to st7783 in case we can't read the ID
so don't bother handling impossible cases
Change-Id: I352fd43b26068b460e69190d37c4cd4627e1db9a
The flip and invert settings can potentially be reset to their
value accross a disable/enable cycle, so save the value of the
impacted registers and apply it after each enable. Also avoid
poking registers when the lcd is not on.
Change-Id: Ica98f166c060aade7eb205f5628b58aae692024f
When chaging the cpu and memory frequency we need to disable the
external memory interface (EMI) for a small time. This can
underflow the dma and cause some breakage. Hopefully the SSP
controller handles this gracefully by stopping the clock and the
I2C probably handles this naturally because the clock can be
streched anyway. However the LCDIF has a special setting for this
which needs to be enable, otherwise it will send garbage to the
LCD. No other block is known to suffer from this currently but
this issue might have more unexpected consequences.
Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
There is a windows port of the sg_utils library for scsi pass-
through. This little changes make it compile under mingw. A better
fix would be to implement direct ioctl on both windows and linux
but that's already better than nothing
Change-Id: I0d77cd1bad69806a66f0590362f165f24fa240e9
pcm_dma_apply_settings(): sets the configured PCM frequency,
all native CS42L55 sample rates are available.
Change-Id: I2fcd5581457a669c3044516804cb64fb972218d0
Actually Rockbox does not use this mode, it is supported by
other iPods, so implemented on Classic as well.
Change-Id: Ia6578506df27a95a7f7522b3034b764631a8bb3a
Scale battery voltage ADC readings by 1023 instead of 1000,
using ADC1 (substractor) instead of ADC0 (multiplicator) to
get better resolution.
Percent charge/discharge tables are also modified to return
a similar value than the old ones.
Change-Id: I2951c75faa02f4302599ec24f9156cfd209c36eb
With radioart enabled there appears to be buffer corruption when
the image is loaded causing the player to data abort in skin_render_line()
So, disable the code untill someone can fix it.
Change-Id: I6acf3f76ce38aa2784b1b24ed6da29a9c5bee479
As well as using an index, which breaks when a file is added or
removed, use the crc32 of the filename. When the crc32 check passes the
index is used directly. When it fails, the slow path is taken checking
each file name in the playlist until the right crc is found. If that fails
the playlist is started from the beginning.
See http://www.rockbox.org/tracker/6411
Bump plugin API and nvram version numbers
Change-Id: I156f61a9f1ac428b4a682bc680379cb6b60b1b10
Reviewed-on: http://gerrit.rockbox.org/372
Tested-by: Jonathan Gordon <rockbox@jdgordon.info>
Reviewed-by: Jonathan Gordon <rockbox@jdgordon.info>
On Windows the sector buffer is allocated using VirtualAlloc, thus releasing
this buffer should be done using VirtualFree. Provide an additional function
for deallocating the buffer so users of ipodpatcher do not need to know about
this.
Change-Id: Ibb0fc575a185148a389e63935e86a392bf8d180d
The working directory will usually be different than the one libtools.make is
located in, so make sure to use the correct starting folder for the relative
path.
Change-Id: I9a84a0573c9f1f32601f31587425689dcf8fb81f
Similar as the ipod_t structure for ipodpatcher the sansa_t structure holds all
relevant information for sansapatcher. Put the global sansa_sectorbuf pointer
into it as well.
Change-Id: Iad08ef6aafc49609c3d0d556914246f230ee0179
The ipod_t structure holds all relevant information for ipodpatcher. Put the
global ipod_sectorbuf pointer into it as well. Allows the Rockbox Utility Ipod
class to be instanciated multiple times since each instance can now have its
own buffer.
Change-Id: Ie319cbadbc20c367ceadba9a46b4dc34b57a79a7
Fixes missing Settings - General Settings - System - Disk - Spindown
setting.
Change-Id: Iae686598dfd7ad4ca1faf8db9f1271e7808de752
Reviewed-on: http://gerrit.rockbox.org/376
Reviewed-by: Michael Giacomelli <giac2000@hotmail.com>
Tested-by: Michael Giacomelli <giac2000@hotmail.com>
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
Do low level power init in system_init(). This can be needed
since imx233 must be able to frequecy scale atfer system_init()
and kernel_init() and this is only possible if power system was
initialised.
Change-Id: I27c66ec0dccd60bda26a45be24683c0bfe72c6da
The old GCC version currently required (sbox-arm-linux-gcc 3.4.4
release) apparently has trouble with function pointers used as
static array initializers when using indexed initializers + ranges
(ie. [A ... B] = fn).
Change-Id: I494c2b607e4d93a9893264749d0ac257fb54ce3b
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
HAVE_USB_CHARGING_ENABLE is not only used for software usb, so checking
for HAVE_USBSTACK is wrong.
Change-Id: I422796b517c262f33f35623e992434219e288424
1) slight keymaps update
Remove mapping of BUTTON_BACK reseting game to avoid pressing it
involuntary.
Direct mapping of BUTTON_POWER to go into menu.
2) manual updated
Change-Id: I28875104c4a4058216532b9aa12bb2defabcca6d
Reviewed-on: http://gerrit.rockbox.org/352
Reviewed-by: Amaury Pouly <amaury.pouly@gmail.com>
The lcd driver does not wait for the refresh to be done to return
from lcd_update(). This means that changing a register is unsafe
if done in the middle of the redraw. This could happen when
disabling the lcd for example. Make sure it doesn't happen by
waiting for the lcdif to be ready.
Change-Id: I43ec62a637dd61c3b2a3a6e131c1a9e8035524b1
When changing the cpu frequency, it is important to make sure that
HBUS stays at a reasonable frequency otherwise the chip will
crash. Special care is needed about auto-slow and clk_p/clk_h
ratio on intermediate steps.
Change-Id: Ief9f68ddf286caabe75c879718dac5027ab1560f
Make sure DCDC is running at boot (it is disabled by default when
5V is present and we don't want to rely on the bootloader to
change this).
When changing the voltage on a regulator, it usually takes 2ms for
the voltage to stabilize. In DCDC mode, there is an irq to notify
about the event so use it ! This is especially important when
changing cpu frequency because increasing the cpu freq while the
voltage is rising is unreliable.
Change-Id: Icfe9ef3ee90156d1e17da0820d9041859f7f3bca
HBUS uses the same field for integer and fractional dividers, the
choice is made by a bit. Make sure both are changed together,
otherwise this could result in the wrong divider to be used and in
HBUS freq to be too low or too high (very bad).
Change-Id: I253d8eeee26c5038868b729c4f791511295a39f0
