Ask for alignement of USB buffers on cache line
Also remind that the hardware is identical to the hardware in nano2g
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28033 a1c6a512-1295-4272-9138-f99709370657
- change buffer alignement to 32 bytes (not sure if it's useful)
- flush rx fifo on reset
- use AS3525_PHYSICAL_ADDR for DMA
- reset endpoints structure states on reset
- force full speed for debugging purpose
- add more debugging code
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27986 a1c6a512-1295-4272-9138-f99709370657
Move CLKDIV macros into clock-target.h.
Only enable the necessary interfaces for the 3 clock registers used for SD.
Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657
Reuse some code from Clip (LCD) and a lot of code from AS3525
Add a new CPU type : AS3525v2, identical to AS3525 except it's an ARMv5 (arm926-ejs)
SD code still not working
For an unknown reason LCD doesn't work anymore (to be investigated)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24131 a1c6a512-1295-4272-9138-f99709370657
