Linus Nielsen Feltzing
|
cff83c78c7
|
ColdFire: DCR is a 16-bit register
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
|
2005-06-08 07:37:32 +00:00 |
|
Linus Nielsen Feltzing
|
752d0bb8be
|
Added DMA register definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6202 a1c6a512-1295-4272-9138-f99709370657
|
2005-03-18 11:33:07 +00:00 |
|
Linus Nielsen Feltzing
|
e52e3f713f
|
Correct size for the DCRx registers
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5993 a1c6a512-1295-4272-9138-f99709370657
|
2005-02-16 22:14:36 +00:00 |
|
Linus Nielsen Feltzing
|
b57fd974de
|
Correct size for the BCRx registers
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5992 a1c6a512-1295-4272-9138-f99709370657
|
2005-02-16 22:10:47 +00:00 |
|
Linus Nielsen Feltzing
|
672092c6dc
|
Made the Coldfire registers volatile, rename PLLCONTROL to PLLCR
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5941 a1c6a512-1295-4272-9138-f99709370657
|
2005-02-14 21:30:30 +00:00 |
|
Linus Nielsen Feltzing
|
58462ab101
|
The timer registers are 16-bit
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5364 a1c6a512-1295-4272-9138-f99709370657
|
2004-10-27 06:50:00 +00:00 |
|
Linus Nielsen Feltzing
|
515d819d3e
|
CPU definitions for MCF5249
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5183 a1c6a512-1295-4272-9138-f99709370657
|
2004-10-06 13:25:56 +00:00 |
|