From eb755ec351507c8706fc8cd0e292349034ddbe68 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Fri, 9 Apr 2010 13:21:32 +0000 Subject: [PATCH] Gigabeat S: Slow down the SPI clock to 1/8 current speed. It seems lower voltages can reveal the weakness that forbids maximum-speed clocking per the SPI spec. OF leaves it set much slower. Push it a bit over OF since it's been gotten away with fairly cleanly so far. Settings on pins and interface to be more thoroughly investigated. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25554 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx31/mc13783-imx31.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index fc5dfa72f6..9b7248dc45 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c @@ -38,7 +38,7 @@ static struct spi_node mc13783_spi = CSPI2_NUM, /* CSPI module 2 */ CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ - CSPI_CONREG_DATA_RATE_DIV_4 | /* Clock = IPG_CLK/4 - 16.5MHz */ + CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ CSPI_CONREG_SSPOL | /* SS active high */ CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */