From e02a1a534d40a4acd482a8bc9fca88d3ffaf75fa Mon Sep 17 00:00:00 2001
From: Marcoen Hirschberg <marcoen@gmail.com>
Date: Fri, 1 Jul 2005 07:55:19 +0000
Subject: [PATCH] - enable S/PDIF optical output - set the proper noise shape
 filter

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6959 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/drivers/power.c   |  2 +-
 firmware/drivers/uda1380.c | 14 ++++++++++++++
 firmware/export/uda1380.h  |  2 ++
 firmware/pcm_playback.c    | 21 ++++++++++++++-------
 4 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/firmware/drivers/power.c b/firmware/drivers/power.c
index fecc79a465..32a420056d 100644
--- a/firmware/drivers/power.c
+++ b/firmware/drivers/power.c
@@ -71,7 +71,7 @@ void power_init(void)
     GPIO_ENABLE |= 0x80000000;
     GPIO_FUNCTION |= 0x80000000;
 #ifdef HAVE_SPDIF_POWER
-    spdif_power_enable(false);
+    spdif_power_enable(true);
 #endif
 #else
 #ifdef HAVE_POWEROFF_ON_PB5
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c
index 7fd65a75e2..15d58e697f 100644
--- a/firmware/drivers/uda1380.c
+++ b/firmware/drivers/uda1380.c
@@ -279,3 +279,17 @@ void uda1380_set_monitor(int enable)
         uda1380_write_reg(REG_MIX_VOL, (uda1380_regs[REG_MIX_VOL] & 0x00FF) | MIX_VOL_CH_2(0xff));
     }
 }
+
+/* Change the order of the noise chaper, 5th order is recommended above 32kHz */
+void uda1380_set_nsorder(int order)
+{
+    switch(order)
+    {
+    case 5:
+        uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | MIX_CTL_SEL_NS);
+        break;
+    case 3:
+    default:
+        uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] & ~MIX_CTL_SEL_NS);
+    }
+}
diff --git a/firmware/export/uda1380.h b/firmware/export/uda1380.h
index 5a32a50356..b5a31e33fe 100644
--- a/firmware/export/uda1380.h
+++ b/firmware/export/uda1380.h
@@ -28,6 +28,7 @@ extern void uda1380_set_bass(int value);
 extern void uda1380_set_treble(int value);
 extern int uda1380_mute(int mute);
 extern void uda1380_close(void);
+extern void uda1380_set_nsorder(int order);
 
 extern void uda1380_enable_recording(bool source_mic);
 extern void uda1380_disable_recording(void);
@@ -135,6 +136,7 @@ extern void uda1380_set_monitor(int enable);
 #define REG_MIX_CTL         0x14
 #define MIX_CTL_MIX_POS     (1 << 13)
 #define MIX_CTL_MIX         (1 << 12)
+#define MIX_CTL_SEL_NS      (1 << 14)
 
 /* REG_DEC_VOL: Decimator (ADC) volume control */
 #define REG_DEC_VOL         0x20
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c
index cad835e20e..9a261dbf77 100644
--- a/firmware/pcm_playback.c
+++ b/firmware/pcm_playback.c
@@ -106,6 +106,7 @@ static void dma_start(const void *addr, long size)
 
     /* Reset the audio FIFO */
     IIS2CONFIG = 0x800;
+    EBU1CONFIG = 0x800;
     
     /* Set up DMA transfer  */
     SAR0 = ((unsigned long)addr); /* Source address */
@@ -113,7 +114,9 @@ static void dma_start(const void *addr, long size)
     BCR0 = size;                  /* Bytes to transfer */
 
     /* Enable the FIFO and force one write to it */
-    IIS2CONFIG = (pcm_freq << 12) | 0x300;
+    IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2;
+    /* Also send the audio to S/PDIF */
+    EBU1CONFIG = 7 << 12 |  3 << 8 | 5 << 2;
     DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START;
 }
 
@@ -140,6 +143,7 @@ static void dma_stop(void)
     DCR0 = 0;
     /* Reset the FIFO */
     IIS2CONFIG = 0x800;
+    EBU1CONFIG = 0x800;
 }
 
 /* sets frequency of input to DAC */
@@ -148,16 +152,17 @@ void pcm_set_frequency(unsigned int frequency)
     switch(frequency)
     {
     case 11025:
-        pcm_freq = 0x2;
+        pcm_freq = 0x4;
+        uda1380_set_nsorder(3);
         break;
     case 22050:
-        pcm_freq = 0x4;
+        pcm_freq = 0x6;
+        uda1380_set_nsorder(3);
         break;
     case 44100:
-        pcm_freq = 0x6;
-        break;
     default:
-        pcm_freq = 0x6;
+        pcm_freq = 0xC;
+        uda1380_set_nsorder(5);
         break;
     }
 }
@@ -266,7 +271,8 @@ void pcm_play_pause(bool play)
         SAR0 = (unsigned long)next_start;
         BCR0 = next_size;
         /* Enable the FIFO and force one write to it */
-        IIS2CONFIG = (pcm_freq << 12) | 0x300;
+        IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2;
+        EBU1CONFIG = 7 << 12 |  3 << 8 | 5 << 2;
         DCR0 |= DMA_EEXT | DMA_START;
     }
     else if(!pcm_paused && !play)
@@ -275,6 +281,7 @@ void pcm_play_pause(bool play)
         /* Disable DMA peripheral request. */
         DCR0 &= ~DMA_EEXT;
         IIS2CONFIG = 0x800;
+        EBU1CONFIG = 0x800;
     }
     pcm_paused = !play;
 }