diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index f1060686f1..8f308fdb8f 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h @@ -3366,14 +3366,14 @@ do { \ #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) -#define CFG_EXTAL 12000000 +#define CFG_EXTAL (12000000) #ifdef CFG_EXTAL #define JZ_EXTAL CFG_EXTAL #else -#define JZ_EXTAL 3686400 +#define JZ_EXTAL (3686400) #endif -#define JZ_EXTAL2 32768 /* RTC clock */ +#define JZ_EXTAL2 (32768) /* RTC clock */ /* PLL output frequency */ static __inline__ unsigned int __cpm_get_pllout(void) diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c index c9ca85cfaf..57361370dc 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c @@ -30,6 +30,7 @@ #include "storage.h" #include "buffer.h" #include "string.h" +//#define LOGF_ENABLE #include "logf.h" //#define USE_DMA @@ -114,8 +115,9 @@ static struct nand_info* banks[4]; static unsigned int nr_banks = 1; static unsigned long bank_size; static struct nand_param internal_param; -#ifdef USE_DMA static struct mutex nand_mtx; +#ifdef USE_DMA +static struct mutex nand_dma_mtx; static struct wakeup nand_wkup; #endif static unsigned char temp_page[4096]; /* Max page size */ @@ -148,7 +150,7 @@ static inline void jz_nand_read_buf8(void *buf, int count) #else static void jz_nand_write_dma(void *source, unsigned int len, int bw) { - mutex_lock(&nand_mtx); + mutex_lock(&nand_dma_mtx); if(((unsigned int)source < 0xa0000000) && len) dma_cache_wback_inv((unsigned long)source, len); @@ -176,12 +178,12 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw) dma_disable(); - mutex_unlock(&nand_mtx); + mutex_unlock(&nand_dma_mtx); } static void jz_nand_read_dma(void *target, unsigned int len, int bw) { - mutex_lock(&nand_mtx); + mutex_lock(&nand_dma_mtx); if(((unsigned int)target < 0xa0000000) && len) dma_cache_wback_inv((unsigned long)target, len); @@ -208,7 +210,7 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) dma_disable(); - mutex_unlock(&nand_mtx); + mutex_unlock(&nand_dma_mtx); } void DMA_CALLBACK(DMA_NAND_CHANNEL)(void) @@ -427,7 +429,7 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst) if (stat & EMC_NFINTS_UNCOR) { /* Uncorrectable error occurred */ - panicf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr); + logf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr); return -1; } else @@ -596,8 +598,9 @@ int nand_init(void) if(!inited) { res = jz_nand_init(); -#ifdef USE_DMA mutex_init(&nand_mtx); +#ifdef USE_DMA + mutex_init(&nand_dma_mtx); wakeup_init(&nand_wkup); system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); #endif @@ -608,38 +611,58 @@ int nand_init(void) return res; } +static inline int read_sector(unsigned long start, unsigned int count, + void* buf, unsigned int chip_size) +{ + register int ret; + + if(UNLIKELY(start % chip_size == 0 && count == chip_size)) + ret = jz_nand_read_page(start / chip_size, buf); + else + { + ret = jz_nand_read_page(start / chip_size, temp_page); + memcpy(buf, temp_page + (start % chip_size), count); + } + + return ret; +} + int nand_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf) { - int i, ret = 0, chip_size = chip_info->page_size; + int ret = 0; + unsigned int i, _count, chip_size = chip_info->page_size; + unsigned long _start; - logf("nand_read_sectors(%ld, %d, 0x%x)", start, count, (int)buf); + logf("start"); + mutex_lock(&nand_mtx); + + _start = start << 9; + _count = count << 9; - start *= 512; - count *= 512; - - if(count <= chip_size) + if(_count <= chip_size) { - jz_nand_select(start / 512 / bank_size); - - ret = jz_nand_read_page(start/chip_size, temp_page); - memcpy(buf, temp_page+(start%chip_size), count); - - jz_nand_deselect(start / 512 / bank_size); + jz_nand_select(start / bank_size); + ret = read_sector(_start, _count, buf, chip_size); + jz_nand_deselect(start / bank_size); } else { - for(i=0; i>9)) / bank_size); - ret = jz_nand_read_page((start+i)/chip_size, temp_page); - memcpy(buf+i, temp_page+((start+i)%chip_size), - (count-i < chip_size ? count-i : chip_size)); + ret = read_sector(_start+i, (_count-i < chip_size ? + _count-i : chip_size), + buf+i, chip_size); - jz_nand_deselect((start/512+i) / bank_size); + jz_nand_deselect((start+(i>>9)) / bank_size); } } + mutex_unlock(&nand_mtx); + + logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); + return ret; } diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c index 374bc110d6..2c77da4ba7 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c @@ -24,7 +24,8 @@ #include "jz4740.h" /* TQ7051 chip */ -#define USB_CHARGER_GPIO (32*1+30) /* STAT port */ +#define UNK_GPIO (32*1+30) /* STAT port */ +#define USB_CHARGER_GPIO (32*3+28) /* Detect which power sources are present. */ unsigned int power_input_status(void) diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 9c7f83530f..052ea64495 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c @@ -369,15 +369,10 @@ void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc) panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr); } -static const int FR2n[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; static unsigned int iclk; - static void detect_clock(void) { - unsigned int cfcr, pllout; - cfcr = REG_CPM_CPCCR; - pllout = (__cpm_get_pllm() + 2)* JZ_EXTAL / (__cpm_get_plln() + 2); - iclk = pllout / FR2n[__cpm_get_cdiv()]; + iclk = __cpm_get_cclk(); } void udelay(unsigned int usec) @@ -639,6 +634,9 @@ static inline void set_cpu_freq(unsigned int pllin, unsigned int div) static void OF_init_clocks(void) { + unsigned long t = read_c0_status(); + write_c0_status(t & ~1); + unsigned int prog_entry = ((unsigned int)OF_init_clocks >> 5) << 5; unsigned int i, prog_size = 1024; @@ -675,6 +673,8 @@ static void OF_init_clocks(void) set_cpu_freq(336000000, 1); for(i=0; i<60; i++); + + write_c0_status(t); } static void my_init_clocks(void) @@ -700,10 +700,10 @@ static void my_init_clocks(void) CPM_CPCCR_UCS | CPM_CPCCR_PCS | (0 << CPM_CPCCR_CDIV_BIT) | - (2 << CPM_CPCCR_HDIV_BIT) | - (2 << CPM_CPCCR_PDIV_BIT) | - (2 << CPM_CPCCR_MDIV_BIT) | - (2 << CPM_CPCCR_LDIV_BIT); + (1 << CPM_CPCCR_HDIV_BIT) | + (1 << CPM_CPCCR_PDIV_BIT) | + (1 << CPM_CPCCR_MDIV_BIT) | + (1 << CPM_CPCCR_LDIV_BIT); plcr1 = (54 << CPM_CPPCR_PLLM_BIT) | /* FD */ (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ @@ -763,6 +763,7 @@ void system_main(void) #if 0 my_init_clocks(); + //OF_init_clocks(); /*__cpm_stop_udc(); REG_CPM_CPCCR |= CPM_CPCCR_UCS; REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | (3 << CPM_CPCCR_UDIV_BIT); diff --git a/firmware/target/mips/mmu-mips.h b/firmware/target/mips/mmu-mips.h index 1670d57f1c..def4196be1 100644 --- a/firmware/target/mips/mmu-mips.h +++ b/firmware/target/mips/mmu-mips.h @@ -22,7 +22,8 @@ #ifndef __MMU_MIPS_INCLUDE_H #define __MMU_MIPS_INCLUDE_H -void map_address(unsigned long virtual, unsigned long physical, unsigned long length); +void map_address(unsigned long virtual, unsigned long physical, + unsigned long length, unsigned int cache_flags); void tlb_init(void); #endif /* __MMU_MIPS_INCLUDE_H */