diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c index d0b9c2b717..3b2ede685a 100755 --- a/bootloader/mrobe500.c +++ b/bootloader/mrobe500.c @@ -38,6 +38,7 @@ #include "common.h" #include "rbunicode.h" #include "usb.h" +#include "spi-target.h" void main(void) { @@ -55,7 +56,7 @@ void main(void) uartSetup(); lcd_init(); font_init(); - // dm320_spi_init(); + dm320_spi_init(); lcd_setfont(FONT_SYSFIXED); @@ -97,12 +98,8 @@ void main(void) #endif printf("ATA"); - int count = 0, i = 0, c = 0; - char data[64]; - unsigned short out[] = {0x8000}; - unsigned short in[2]; - outw(inw(IO_GIO_DIR1)&~(1<<10), IO_GIO_DIR1); // set GIO26 to output + outw(inw(IO_GIO_DIR1)&~(1<<10), IO_GIO_DIR1); // set GIO26 to output while(true) { if (button_read_device() == BUTTON_POWER) @@ -110,9 +107,19 @@ void main(void) printf("reset"); outw(1<<10, IO_GIO_BITSET1); } - // dm320_spi_block_transfer(0, out, 16, 16, in, 0); - // printf("%x", in[0]); - + + // Read X, Y, Z1, Z2 touchscreen coordinates. + int page = 0, address = 0; + unsigned short command = 0x8000|(page << 11)|(address << 5); + unsigned char out[] = {command >> 8, command & 0xff}; + unsigned char in[8]; + dm320_spi_block_transfer(out, sizeof(out), in, sizeof(in)); + + printf("%02x%02x %02x%02x %02x%02x %02x%02x\n", + in[0], in[1], + in[2], in[3], + in[4], in[5], + in[6], in[7]); } #if 0 rc = ata_init(); diff --git a/firmware/SOURCES b/firmware/SOURCES index e62d9331a5..3a606e5bfd 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -601,6 +601,7 @@ target/arm/olympus/mrobe-500/system-mr500.c target/arm/olympus/mrobe-500/timer-mr500.c target/arm/olympus/mrobe-500/usb-mr500.c target/arm/olympus/mrobe-500/uart-mr500.c +target/arm/olympus/mrobe-500/spi-mr500.c #ifndef BOOTLOADER #endif diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 5e164cff57..f072e8975f 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h @@ -27,6 +27,7 @@ #define FRAME ((short *) (0x4470000)) #define PHY_IO_BASE 0x00030000 +#define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr))) /* Timer 0-3 */ #define IO_TIMER0_TMMD 0x0000 @@ -58,20 +59,20 @@ #define IO_TIMER3_TMCNT 0x018A /* Serial 0/1 */ -#define IO_SERIAL0_TX_DATA 0x0200 -#define IO_SERIAL0_RX_DATA 0x0202 -#define IO_SERIAL0_TX_ENABLE 0x0204 -#define IO_SERIAL0_MODE 0x0206 -#define IO_SERIAL0_DMA_TRIGGER 0x0208 -#define IO_SERIAL0_DMA_MODE 0x020A -#define IO_SERIAL0_DMA_SDRAM_LOW 0x020C -#define IO_SERIAL0_DMA_SDRAM_HI 0x020E -#define IO_SERIAL0_DMA_STATUS 0x0210 +#define IO_SERIAL0_TX_DATA DM320_REG(0x0200) +#define IO_SERIAL0_RX_DATA DM320_REG(0x0202) +#define IO_SERIAL0_TX_ENABLE DM320_REG(0x0204) +#define IO_SERIAL0_MODE DM320_REG(0x0206) +#define IO_SERIAL0_DMA_TRIGGER DM320_REG(0x0208) +#define IO_SERIAL0_DMA_MODE DM320_REG(0x020A) +#define IO_SERIAL0_DMA_SDRAM_LOW DM320_REG(0x020C) +#define IO_SERIAL0_DMA_SDRAM_HI DM320_REG(0x020E) +#define IO_SERIAL0_DMA_STATUS DM320_REG(0x0210) -#define IO_SERIAL1_TX_DATA 0x0280 -#define IO_SERIAL1_RX_DATA 0x0282 -#define IO_SERIAL1_TX_ENABLE 0x0284 -#define IO_SERIAL1_MODE 0x0286 +#define IO_SERIAL1_TX_DATA DM320_REG(0x0280) +#define IO_SERIAL1_RX_DATA DM320_REG(0x0282) +#define IO_SERIAL1_TX_ENABLE DM320_REG(0x0284) +#define IO_SERIAL1_MODE DM320_REG(0x0286) /* UART 0/1 */ #define IO_UART0_DTRR 0x0300 @@ -383,31 +384,31 @@ #define IO_VID_ENC_ATR0 0x0854 /* Clock Controller */ -#define IO_CLK_PLLA 0x0880 -#define IO_CLK_PLLB 0x0882 -#define IO_CLK_SEL0 0x0884 -#define IO_CLK_SEL1 0x0886 -#define IO_CLK_SEL2 0x0888 -#define IO_CLK_DIV0 0x088A -#define IO_CLK_DIV1 0x088C -#define IO_CLK_DIV2 0x088E -#define IO_CLK_DIV3 0x0890 -#define IO_CLK_DIV4 0x0892 -#define IO_CLK_BYP 0x0894 -#define IO_CLK_INV 0x0896 -#define IO_CLK_MOD0 0x0898 -#define IO_CLK_MOD1 0x089A -#define IO_CLK_MOD2 0x089C -#define IO_CLK_LPCTL0 0x089E -#define IO_CLK_LPCTL1 0x08A0 -#define IO_CLK_OSEL 0x08A2 -#define IO_CLK_00DIV 0x08A4 -#define IO_CLK_O1DIV 0x08A6 -#define IO_CLK_02DIV 0x08A8 -#define IO_CLK_PWM0C 0x08AA -#define IO_CLK_PWM0H 0x08AC -#define IO_CLK_PWM1C 0x08AE -#define IO_CLK_PWM1H 0x08B0 +#define IO_CLK_PLLA DM320_REG(0x0880) +#define IO_CLK_PLLB DM320_REG(0x0882) +#define IO_CLK_SEL0 DM320_REG(0x0884) +#define IO_CLK_SEL1 DM320_REG(0x0886) +#define IO_CLK_SEL2 DM320_REG(0x0888) +#define IO_CLK_DIV0 DM320_REG(0x088A) +#define IO_CLK_DIV1 DM320_REG(0x088C) +#define IO_CLK_DIV2 DM320_REG(0x088E) +#define IO_CLK_DIV3 DM320_REG(0x0890) +#define IO_CLK_DIV4 DM320_REG(0x0892) +#define IO_CLK_BYP DM320_REG(0x0894) +#define IO_CLK_INV DM320_REG(0x0896) +#define IO_CLK_MOD0 DM320_REG(0x0898) +#define IO_CLK_MOD1 DM320_REG(0x089A) +#define IO_CLK_MOD2 DM320_REG(0x089C) +#define IO_CLK_LPCTL0 DM320_REG(0x089E) +#define IO_CLK_LPCTL1 DM320_REG(0x08A0) +#define IO_CLK_OSEL DM320_REG(0x08A2) +#define IO_CLK_00DIV DM320_REG(0x08A4) +#define IO_CLK_O1DIV DM320_REG(0x08A6) +#define IO_CLK_02DIV DM320_REG(0x08A8) +#define IO_CLK_PWM0C DM320_REG(0x08AA) +#define IO_CLK_PWM0H DM320_REG(0x08AC) +#define IO_CLK_PWM1C DM320_REG(0x08AE) +#define IO_CLK_PWM1H DM320_REG(0x08B0) /* Bus Controller */ #define IO_BUSC_ECR 0x0900 diff --git a/firmware/target/arm/olympus/mrobe-500/spi-mr500.c b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c new file mode 100644 index 0000000000..6c0d4b5990 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c @@ -0,0 +1,77 @@ +/* + * SPI interface driver for the DM320 SoC + * + * Copyright (C) 2007 shirour + * Copyright (C) 2007 Catalin Patulea + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "system.h" + +#define GIO_TS_ENABLE (1<<2) +#define clr_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITSET1) +#define set_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITCLR1) + +int dm320_spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, + uint8_t *rx_bytes, unsigned int rx_size) +{ + /* Activate the slave select pin */ + set_gio_enable(); + + while (tx_size--) + { + /* Send one byte */ + IO_SERIAL0_TX_DATA = *tx_bytes++; + + /* Wait until transfer finished */ + while (IO_SERIAL0_RX_DATA & 0x100); + } + + while (rx_size--) + { + /* Make the clock tick */ + IO_SERIAL0_TX_DATA = 0; + + /* Wait until transfer finished */ + unsigned short data; + while ((data = IO_SERIAL0_RX_DATA) & 0x100); + + *rx_bytes++ = data & 0xff; + } + + clr_gio_enable(); + + return 0; +} + +void dm320_spi_init(void) +{ + /* Set SCLK idle level = 0 */ + IO_SERIAL0_MODE |= (1<<10); + + /* Enable TX */ + IO_SERIAL0_TX_ENABLE = 0x0001; + + /* Set GIO 18 to output for touch screen slave enable */ + outw(inw(IO_GIO_DIR1)&~GIO_TS_ENABLE, IO_GIO_DIR1); + clr_gio_enable(); +} diff --git a/firmware/target/arm/olympus/mrobe-500/spi-target.h b/firmware/target/arm/olympus/mrobe-500/spi-target.h new file mode 100644 index 0000000000..ebaacb45a0 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/spi-target.h @@ -0,0 +1,29 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Catalin Patulea + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#ifndef SPI_TARGET_H +#define SPI_TARGET_H + +#include + +void dm320_spi_init(void); +int dm320_spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, + uint8_t *rx_bytes, unsigned int rx_size); + +#endif diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 4e7228415d..fa63c8fb2c 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h @@ -93,8 +93,8 @@ static inline void flush_icache(void) #endif /* CONFIG_CPU */ #else /* CPU_CONFIG == DM320 */ -#define inw(p) (*((unsigned short*)(p + PHY_IO_BASE))) -#define outw(v,p) (*((unsigned short*)(p + PHY_IO_BASE)) = v) +#define inw(p) (*((volatile unsigned short*)((p) + PHY_IO_BASE))) +#define outw(v,p) (*((volatile unsigned short*)((p) + PHY_IO_BASE)) = (v)) #endif