diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index c78f990f5f..28e050fcef 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -71,9 +71,33 @@ static const struct nand_chip chip_w25n01gvxx = {
     .setup_chip = winbond_setup_chip,
 };
 
+static const struct nand_chip chip_gd5f1gq4xexx = {
+    .log2_ppb = 6, /* 64 pages */
+    .page_size = 2048,
+    .oob_size = 64, /* 128B when hardware ECC is disabled */
+    .nr_blocks = 1024,
+    .bbm_pos = 2048,
+    .clock_freq = 150000000,
+    .dev_conf = jz_orf(SFC_DEV_CONF,
+                       CE_DL(1), HOLD_DL(1), WP_DL(1),
+                       CPHA(0), CPOL(0),
+                       TSH(7), TSETUP(0), THOLD(0),
+                       STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS),
+                       SMP_DELAY(1)),
+    .flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT |
+             NAND_CHIPFLAG_ON_DIE_ECC,
+    .cmd_page_read = NANDCMD_PAGE_READ,
+    .cmd_program_execute = NANDCMD_PROGRAM_EXECUTE,
+    .cmd_block_erase = NANDCMD_BLOCK_ERASE,
+    .cmd_read_cache = NANDCMD_READ_CACHE_x4,
+    .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4,
+};
+
 const struct nand_chip_id supported_nand_chips[] = {
     NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12),
     NAND_CHIP_ID(&chip_w25n01gvxx, NAND_READID_ADDR, 0xef, 0xaa, 0x21),
+    NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xd1),
+    NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xc1),
 };
 
 const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips);