diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c new file mode 100644 index 0000000000..e8b8c14399 --- /dev/null +++ b/firmware/drivers/uda1380.c @@ -0,0 +1,145 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2005 by Andy Young + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "lcd.h" +#include "cpu.h" +#include "kernel.h" +#include "thread.h" +#include "power.h" +#include "debug.h" +#include "system.h" +#include "sprintf.h" +#include "button.h" +#include "string.h" +#include "file.h" +#include "buffer.h" + +#include "i2c-h100.h" +#include "uda1380.h" + +/* ------------------------------------------------- */ +/* Local functions and variables */ +/* ------------------------------------------------- */ + +int uda1380_write_reg(unsigned char reg, unsigned short value); +unsigned short uda1380_regs[0x30]; + +/* Definition of a good (?) configuration to start with */ +/* Not enabling ADC for now.. */ + +#define NUM_DEFAULT_REGS 13 +unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = +{ + REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50, + REG_I2S, I2S_IFMT_IIS, + REG_PWR, PON_PLL | PON_HP | PON_DAC | EN_AVC | PON_AVC | PON_BIAS, + REG_AMIX, AMIX_RIGHT(0x10) | AMIX_LEFT(0x10), /* 00=max, 3f=mute */ + REG_MASTER_VOL, MASTER_VOL_LEFT(0x7f) | MASTER_VOL_RIGHT(0x7f), /* 00=max, ff=mute */ + REG_MIX_VOL, MIX_VOL_CHANNEL_1(0) | MIX_VOL_CHANNEL_2(0xff), /* 00=max, ff=mute */ + REG_EQ, 0, + REG_MUTE, MUTE_CH2, /* Mute channel 2 (digital decimation filter) */ + REG_MIX_CTL, 0, + REG_DEC_VOL, 0, + REG_PGA, MUTE_ADC, + REG_ADC, SKIP_DCFIL, + REG_AGC, 0 +}; + +/* Returns 0 if register was written or -1 if write failed */ +int uda1380_write_reg(unsigned char reg, unsigned short value) +{ + unsigned char data[4]; + + data[0] = UDA1380_ADDR; + data[1] = reg; + data[2] = value >> 8; + data[3] = value & 0xff; + + if (i2c_write(1, data, 4) != 4) + { + DEBUGF("uda1380 error reg=0x%x", reg); + return -1; + } + + uda1380_regs[reg] = value; + + return 0; +} + +/** + * Sets the master volume + * + * \param vol Range [0..255] 0=max, 255=mute + * + */ +int uda1380_setvol(int vol) +{ + return uda1380_write_reg(REG_MASTER_VOL, + MASTER_VOL_LEFT(vol) | MASTER_VOL_RIGHT(vol)); +} + +/** + * Mute (mute=1) or enable sound (mute=0) + * + */ +int uda1380_mute(int mute) +{ + unsigned int value = uda1380_regs[REG_MUTE]; + + if (mute) + value = value | MUTE_MASTER; + else + value = value & ~MUTE_MASTER; + + return uda1380_write_reg(REG_MUTE, value); +} + +/* Returns 0 if successful or -1 if some register failed */ +int uda1380_set_regs(void) +{ + int i; + memset(uda1380_regs, 0, sizeof(uda1380_regs)); + + /* Initialize all registers */ + for (i=0; i ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2002 by Linus Nielsen Feltzing + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* + * Driver for UDA1380 Audio-Codec + * 2005-02-17 hubble@mochine.com + * + */ + +#ifndef _UDA1380_H +#define _UDA1380_H + +extern int uda1380_init(void); +extern int uda1380_setvol(int vol); +extern int uda1380_mute(int mute); +extern void uda1380_close(void); + +#define UDA1380_ADDR 0x30 + +/* REG_0: Misc settings */ +#define REG_0 0x00 + +#define EN_ADC (1 << 11) /* Enable ADC */ +#define EN_DEC (1 << 10) /* Enable Decimator */ +#define EN_DAC (1 << 9) /* Enable DAC */ +#define EN_INT (1 << 8) /* Enable Interpolator */ +#define ADC_CLK (1 << 5) /* ADC_CLK: WSPLL (1) SYSCLK (0) */ +#define DAC_CLK (1 << 4) /* DAC_CLK: WSPLL (1) SYSCLK (0) */ + +/* SYSCLK freqency select */ +#define SYSCLK_256FS (0 << 2) +#define SYSCLK_384FS (1 << 2) +#define SYSCLK_512FS (2 << 2) +#define SYSCLK_768FS (3 << 2) + +/* WSPLL Input frequency range (kHz) */ +#define WSPLL_625_125 (0 << 0) /* 6.25 - 12.5 */ +#define WSPLL_125_25 (1 << 0) /* 12.5 - 25 */ +#define WSPLL_25_50 (2 << 0) /* 25 - 50 */ +#define WSPLL_50_100 (3 << 0) /* 50 - 100 */ + + +/* REG_I2S: I2S settings */ +#define REG_I2S 0x01 +#define I2S_IFMT_IIS (0 << 8) +#define I2S_IFMT_LSB16 (1 << 8) +#define I2S_IFMT_LSB18 (2 << 8) +#define I2S_IFMT_LSB20 (3 << 8) +#define I2S_IFMT_MSB (5 << 8) +#define I2S_OFMT_IIS (0 << 0) +#define I2S_OFMT_LSB16 (1 << 0) +#define I2S_OFMT_LSB18 (2 << 0) +#define I2S_OFMT_LSB20 (3 << 0) +#define I2S_OFMT_LSB24 (4 << 0) +#define I2S_OFMT_MSB (5 << 0) + + +/* REG_PWR: Power control */ +#define REG_PWR 0x02 +#define PON_PLL (1 << 15) /* Power-on WSPLL */ +#define PON_HP (1 << 13) /* Power-on Headphone driver */ +#define PON_DAC (1 << 10) /* Power-on DAC */ +#define PON_BIAS (1 << 8) /* Power-on BIAS for ADC, AVC, FSDAC */ +#define EN_AVC (1 << 7) /* Enable analog mixer */ +#define PON_AVC (1 << 6) /* Power-on analog mixer */ +#define PON_LNA (1 << 4) /* Power-on LNA & SDC */ +#define PON_PGAL (1 << 3) /* Power-on PGA left */ +#define PON_ADCL (1 << 2) /* Power-on ADC left */ +#define PON_PGAR (1 << 1) /* Power-on PGA right */ +#define PON_ADCR (1 << 0) /* Power-on ADC right */ + + +/* REG_AMIX: Analog mixer */ +#define REG_AMIX 0x03 +#define AMIX_LEFT(x) (((x) & 0x3f) << 8) +#define AMIX_RIGHT(x) (((x) & 0x3f) << 0) + +/* REG_HP: Headphone amp */ +#define REG_HP 0x04 + +/* REG_MV: Master Volume control */ +#define REG_MASTER_VOL 0x10 + +#define MASTER_VOL_RIGHT(x) (((x) & 0xff) << 8) +#define MASTER_VOL_LEFT(x) (((x) & 0xff) << 0) + +/* REG_MIX: Mixer volume control */ +/* Channel 1 is from digital data from I2S */ +/* Channel 2 is from decimation filter */ + +#define REG_MIX_VOL 0x11 +#define MIX_VOL_CHANNEL_1(x) (((x) & 0xff) << 0) +#define MIX_VOL_CHANNEL_2(x) (((x) & 0xff) << 8) + +/* REG_EQ: Bass boost and tremble */ +#define REG_EQ 0x12 + +/* REG_MUTE: Master Mute */ +#define REG_MUTE 0x13 +#define MUTE_MASTER (1 << 14) /* Master Mute (soft) */ +#define MUTE_CH2 (1 << 11) /* Channel 2 mute */ +#define MUTE_CH1 (1 << 3) /* Channel 1 mute */ + +/* REG_MIX_CTL: Mixer, silence detector and oversampling settings */ +#define REG_MIX_CTL 0x14 +#define MIX_CTL_MIX_POS (1 << 13) +#define MIX_CTL_MIX (1 << 12) + +/* REG_DEC_VOL: Decimator Volume control */ +#define REG_DEC_VOL 0x20 + +/* REG_PGA: PGA settings and mute */ +#define REG_PGA 0x21 +#define MUTE_ADC (1 << 15) /* Mute ADC */ + +/* REG_ADC: */ +#define REG_ADC 0x22 + +/* REG_AGC: Attack / Gain */ +#define REG_AGC 0x23 +#define SKIP_DCFIL ( 1 << 1) + + +/* Audio tick interrupt */ +#define AUDIO_TICK_NUMBER 8 +#define AUDIO_TICK_BIT (1 << 8) + + +/* AUDIOGLOB bits */ + +#define TICK_COUNT(x) ((x) << 3) + +#define TICK_SOURCE_IIS1_TX 1 +#define TICK_SOURCE_IIS2_TX 2 +#define TICK_SOURCE_EBU_TX 3 +#define TICK_SOURCE_IIS1_RX 4 +#define TICK_SOURCE_IIS3_RX 5 +#define TICK_SOURCE_IIS4_RX 6 +#define TICK_SOURCE_EBU1_RX 7 +#define TICK_SOURCE_EBU2_RX (1 << 11) + + + + +#endif /* _UDA_1380_H */