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Gigabeat S/i.MX31: Continue, and most likely complete, the platform/player-specific code/data shuffling begun in r25547.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25564 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2010-04-10 09:24:06 +00:00
parent 0f6e79a227
commit 79d90b9e76
2 changed files with 21 additions and 16 deletions
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20
firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c
View file

@ -22,6 +22,7 @@
****************************************************************************/ ****************************************************************************/
#include "config.h" #include "config.h"
#include "system.h" #include "system.h"
#include "spi-imx31.h"
#include "mc13783.h" #include "mc13783.h"
#include "mc13783-target.h" #include "mc13783-target.h"
#include "adc-target.h" #include "adc-target.h"
@ -30,6 +31,25 @@
#include "power-gigabeat-s.h" #include "power-gigabeat-s.h"
#include "powermgmt-target.h" #include "powermgmt-target.h"
/* Gigabeat S mc13783 serial interface node. */
/* This is all based on communicating with the MC13783 PMU which is on
* CSPI2 with the chip select at 0. The LCD controller resides on
* CSPI3 cs1, but we have no idea how to communicate to it */
struct spi_node mc13783_spi =
{
CSPI2_NUM, /* CSPI module 2 */
CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */
CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */
CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */
CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */
CSPI_CONREG_SSPOL | /* SS active high */
CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */
CSPI_CONREG_MODE, /* Master mode */
0, /* SPI clock - no wait states */
};
/* Gigabeat S definitions for static MC13783 event registration */ /* Gigabeat S definitions for static MC13783 event registration */
static const struct mc13783_event mc13783_events[] = static const struct mc13783_event mc13783_events[] =

17
firmware/target/arm/imx31/mc13783-imx31.c
View file

@ -30,23 +30,8 @@
#define PMIC_DRIVER_CLOSE #define PMIC_DRIVER_CLOSE
#endif #endif
/* This is all based on communicating with the MC13783 PMU which is on
* CSPI2 with the chip select at 0. The LCD controller resides on
* CSPI3 cs1, but we have no idea how to communicate to it */
static struct spi_node mc13783_spi =
{
CSPI2_NUM, /* CSPI module 2 */
CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */
CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */
CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */
CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */
CSPI_CONREG_SSPOL | /* SS active high */
CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */
CSPI_CONREG_MODE, /* Master mode */
0, /* SPI clock - no wait states */
};
extern const struct mc13783_event_list mc13783_event_list; extern const struct mc13783_event_list mc13783_event_list;
extern struct spi_node mc13783_spi;
static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
static const char *mc13783_thread_name = "pmic"; static const char *mc13783_thread_name = "pmic";