From 75cb8ba8a4c3b5f2a5bd7195ef3d61089151a6f5 Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Wed, 21 Apr 2021 01:47:02 +0100 Subject: [PATCH] FiiO M3K/X1000: add USB support This only required a minor patch to the usb-designware driver due to DMA requiring physical addresses -- on the X1000, these differ from virtual addresses so we have to do the usual conversion. Both the mass storage and HID drivers work, but there are a few issues so this can't be considered 100% stable yet. - Mass storage might not be detected properly on insertion, and USB has to be replugged before it shows up - HID driver may occasionally panic or hang the machine Change-Id: Ia3ce7591d5928ec7cbca7953abfef01bdbd873ef --- apps/keymaps/keymap-fiiom3k.c | 63 +++ bootloader/fiiom3k.c | 107 ++++- firmware/SOURCES | 1 + firmware/drivers/usb-designware.c | 13 +- firmware/export/config/fiiom3k.h | 12 +- .../ingenic_x1000/fiiom3k/power-fiiom3k.c | 10 + .../target/mips/ingenic_x1000/system-target.h | 3 + .../target/mips/ingenic_x1000/system-x1000.c | 2 + .../target/mips/ingenic_x1000/usb-x1000.c | 223 ++++++++++ .../target/mips/ingenic_x1000/x1000/cpm.h | 394 ++++++++++++++++++ utils/reggen-ng/x1000.reggen | 81 ++++ 11 files changed, 886 insertions(+), 23 deletions(-) create mode 100644 firmware/target/mips/ingenic_x1000/usb-x1000.c diff --git a/apps/keymaps/keymap-fiiom3k.c b/apps/keymaps/keymap-fiiom3k.c index e562443227..440f851650 100644 --- a/apps/keymaps/keymap-fiiom3k.c +++ b/apps/keymaps/keymap-fiiom3k.c @@ -185,6 +185,61 @@ static const struct button_mapping button_context_keyboard[] = { LAST_ITEM_IN_LIST }; /* button_context_keyboard */ +static const struct button_mapping button_context_usb_hid[] = { + {ACTION_USB_HID_MODE_SWITCH_NEXT, BUTTON_POWER, BUTTON_NONE}, + LAST_ITEM_IN_LIST, +}; /* button_context_usb_hid */ + +static const struct button_mapping button_context_usb_hid_mode_multimedia[] = { + {ACTION_USB_HID_MULTIMEDIA_VOLUME_UP, BUTTON_VOL_UP, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_VOLUME_UP, BUTTON_VOL_UP|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_VOLUME_DOWN, BUTTON_VOL_DOWN, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_VOLUME_DOWN, BUTTON_VOL_DOWN|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_VOLUME_MUTE, BUTTON_VOL_DOWN|BUTTON_PLAY, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_PLAYBACK_PLAY_PAUSE, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY}, + {ACTION_USB_HID_MULTIMEDIA_PLAYBACK_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_PLAY}, + {ACTION_USB_HID_MULTIMEDIA_PLAYBACK_TRACK_PREV, BUTTON_LEFT, BUTTON_NONE}, + {ACTION_USB_HID_MULTIMEDIA_PLAYBACK_TRACK_NEXT, BUTTON_RIGHT, BUTTON_NONE}, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_USB_HID) +}; /* button_context_usb_hid_mode_multimedia */ + +static const struct button_mapping button_context_usb_hid_mode_presentation[] = { + {ACTION_USB_HID_PRESENTATION_SLIDESHOW_START, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY}, + {ACTION_USB_HID_PRESENTATION_SLIDESHOW_LEAVE, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_PLAY}, + {ACTION_USB_HID_PRESENTATION_SLIDE_PREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT}, + {ACTION_USB_HID_PRESENTATION_SLIDE_NEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT}, + {ACTION_USB_HID_PRESENTATION_SLIDE_FIRST, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT}, + {ACTION_USB_HID_PRESENTATION_SLIDE_LAST, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_RIGHT}, + {ACTION_USB_HID_PRESENTATION_SCREEN_BLACK, BUTTON_VOL_UP, BUTTON_NONE}, + {ACTION_USB_HID_PRESENTATION_SCREEN_WHITE, BUTTON_VOL_DOWN, BUTTON_NONE}, + {ACTION_USB_HID_PRESENTATION_LINK_PREV, BUTTON_MENU, BUTTON_NONE}, + {ACTION_USB_HID_PRESENTATION_LINK_NEXT, BUTTON_BACK, BUTTON_NONE}, + {ACTION_USB_HID_PRESENTATION_MOUSE_CLICK, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT}, + {ACTION_USB_HID_PRESENTATION_MOUSE_OVER, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT}, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_USB_HID) +}; /* button_context_usb_hid_mode_presentation */ + +static const struct button_mapping button_context_usb_hid_mode_browser[] = { + {ACTION_USB_HID_BROWSER_SCROLL_UP, BUTTON_SCROLL_BACK, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_UP, BUTTON_SCROLL_BACK|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_DOWN, BUTTON_SCROLL_FWD, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_DOWN, BUTTON_SCROLL_FWD|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_PAGE_DOWN, BUTTON_DOWN, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_PAGE_UP, BUTTON_UP, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_PAGE_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_SCROLL_PAGE_UP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_ZOOM_IN, BUTTON_VOL_UP, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_ZOOM_OUT, BUTTON_VOL_DOWN, BUTTON_NONE}, + {ACTION_USB_HID_BROWSER_ZOOM_RESET, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY}, + {ACTION_USB_HID_BROWSER_TAB_PREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT}, + {ACTION_USB_HID_BROWSER_TAB_NEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT}, + {ACTION_USB_HID_BROWSER_TAB_CLOSE, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT}, + {ACTION_USB_HID_BROWSER_HISTORY_BACK, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT}, + {ACTION_USB_HID_BROWSER_HISTORY_FORWARD, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_RIGHT}, + {ACTION_USB_HID_BROWSER_VIEW_FULL_SCREEN, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_PLAY}, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_USB_HID) +}; /* button_context_usb_hid_mode_browser */ + const struct button_mapping* get_context_mapping(int context) { switch (context) @@ -215,5 +270,13 @@ const struct button_mapping* get_context_mapping(int context) return button_context_yesnoscreen; case CONTEXT_KEYBOARD: return button_context_keyboard; + case CONTEXT_USB_HID: + return button_context_usb_hid; + case CONTEXT_USB_HID_MODE_MULTIMEDIA: + return button_context_usb_hid_mode_multimedia; + case CONTEXT_USB_HID_MODE_PRESENTATION: + return button_context_usb_hid_mode_presentation; + case CONTEXT_USB_HID_MODE_BROWSER: + return button_context_usb_hid_mode_browser; } } diff --git a/bootloader/fiiom3k.c b/bootloader/fiiom3k.c index 93010e86d2..9f169755ae 100644 --- a/bootloader/fiiom3k.c +++ b/bootloader/fiiom3k.c @@ -24,13 +24,17 @@ #include "i2c.h" #include "power.h" #include "lcd.h" +#include "font.h" #include "backlight.h" +#include "backlight-target.h" #include "button.h" #include "storage.h" #include "file_internal.h" #include "disk.h" +#include "usb.h" #include "rb-loader.h" #include "loader_strerror.h" +#include "version.h" /* Load address where the binary needs to be placed */ extern unsigned char loadaddress[]; @@ -53,20 +57,67 @@ void exec(void* dst, const void* src, int bytes) __builtin_unreachable(); } -static void error(const char* msg) -{ - /* Initialization of the LCD/buttons only if needed */ - lcd_init(); - backlight_init(); - button_init(); +static bool lcd_inited = false; +static bool usb_inited = false; +static void init_lcd(void) +{ + if(lcd_inited) + return; + + lcd_init(); + font_init(); + lcd_setfont(FONT_SYSFIXED); + + /* Clear screen before turning backlight on, otherwise we might + * display random garbage on the screen */ lcd_clear_display(); - lcd_puts(0, 0, msg); - lcd_puts(0, 2, "Press POWER to power off"); lcd_update(); - while(button_get(true) != BUTTON_POWER); - power_off(); + backlight_init(); + + lcd_inited = true; +} + +static void do_splash2(int delay, const char* msg, const char* msg2) +{ + init_lcd(); + lcd_clear_display(); + lcd_putsxy((LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg))) / 2, + (LCD_HEIGHT - SYSFONT_HEIGHT) / 2, msg); + if(msg2) { + lcd_putsxy((LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg2))) / 2, + (LCD_HEIGHT + 2*SYSFONT_HEIGHT) / 2, msg2); + } + + lcd_putsxy((LCD_WIDTH - (SYSFONT_WIDTH * strlen(rbversion))) / 2, + (LCD_HEIGHT - SYSFONT_HEIGHT), rbversion); + lcd_update(); + sleep(delay); +} + +static void do_splash(int delay, const char* msg) +{ + do_splash2(delay, msg, NULL); +} + +static void do_usb(void) +{ + if(!usb_inited) { + usb_init(); + usb_start_monitoring(); + usb_inited = true; + } + + do_splash(0, "Waiting for USB"); + + while(button_get(true) != SYS_USB_CONNECTED); + do_splash(0, "USB mode"); + + usb_acknowledge(SYS_USB_CONNECTED_ACK); + while(button_get(true) != SYS_USB_DISCONNECTED); + + do_splash(3*HZ, "USB disconnected"); } void main(void) @@ -75,22 +126,40 @@ void main(void) kernel_init(); i2c_init(); power_init(); + button_init(); enable_irq(); - if(storage_init() < 0) - error("Storage initialization failed"); + if(storage_init() < 0) { + do_splash(3*HZ, "Failed to init storage"); + power_off(); + } filesystem_init(); - if(!storage_present(0)) - error("No SD card present"); + int loadsize = 0; + do { + if(!storage_present(0)) { + do_splash(HZ, "Insert SD card"); + continue; + } - if(disk_mount_all() <= 0) - error("Unable to mount filesystem"); + if(disk_mount_all() <= 0) { + do_splash(5*HZ, "Cannot mount filesystem"); + do_usb(); + continue; + } - int loadsize = load_firmware(loadbuffer, BOOTFILE, MAX_LOAD_SIZE); - if(loadsize <= 0) - error(loader_strerror(loadsize)); + loadsize = load_firmware(loadbuffer, BOOTFILE, MAX_LOAD_SIZE); + if(loadsize <= 0) { + do_splash2(5*HZ, "Error loading Rockbox", + loader_strerror(loadsize)); + do_usb(); + continue; + } + } while(loadsize <= 0); + + if(lcd_inited) + backlight_hw_off(); disable_irq(); diff --git a/firmware/SOURCES b/firmware/SOURCES index d306f0b8e8..463933b8c5 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -1741,6 +1741,7 @@ target/mips/ingenic_x1000/pwm-x1000.c target/mips/ingenic_x1000/sfc-x1000.c target/mips/ingenic_x1000/system-x1000.c target/mips/ingenic_x1000/timer-x1000.c +target/mips/ingenic_x1000/usb-x1000.c #if (CONFIG_STORAGE & (STORAGE_SD|STORAGE_MMC|STORAGE_ATA)) target/mips/ingenic_x1000/msc-x1000.c #endif diff --git a/firmware/drivers/usb-designware.c b/firmware/drivers/usb-designware.c index 24c6055434..375fd8be74 100644 --- a/firmware/drivers/usb-designware.c +++ b/firmware/drivers/usb-designware.c @@ -53,6 +53,15 @@ #define COMMIT_DCACHE_RANGE(b,s) commit_dcache_range(b,s) #endif +/* On some platforms, virtual addresses must be mangled to + * get a physical address for DMA + */ +#if CONFIG_CPU == X1000 +# define DMA_ADDR2PHYS(x) PHYSADDR(x) +#else +# define DMA_ADDR2PHYS(x) x +#endif + #ifndef USB_DW_TOUTCAL #define USB_DW_TOUTCAL 0 #endif @@ -449,7 +458,7 @@ static void usb_dw_nptx_unqueue(int epnum) dw_ep->addr -= (bytesinfifo + 3) >> 2; #else (void) bytesinfifo; - DWC_DIEPDMA(ep) = (uint32_t)(dw_ep->addr) + sentbytes; + DWC_DIEPDMA(ep) = DMA_ADDR2PHYS((uint32_t)(dw_ep->addr) + sentbytes); #endif DWC_DIEPTSIZ(ep) = PKTCNT(packetsleft) | (dw_ep->size - sentbytes); @@ -676,7 +685,7 @@ static void usb_dw_start_xfer(int epnum, /* Set up data source */ dw_ep->addr = (uint32_t*)buf; #ifndef USB_DW_ARCH_SLAVE - DWC_EPDMA(epnum, epdir) = (uint32_t)buf; + DWC_EPDMA(epnum, epdir) = DMA_ADDR2PHYS((uint32_t)buf); #endif if (epdir == USB_DW_EPDIR_IN) diff --git a/firmware/export/config/fiiom3k.h b/firmware/export/config/fiiom3k.h index 115532dc39..eec1de6740 100644 --- a/firmware/export/config/fiiom3k.h +++ b/firmware/export/config/fiiom3k.h @@ -101,9 +101,17 @@ #define BATTERY_CAPACITY_INC 0 #define BATTERY_TYPES_COUNT 1 -/* USB is still TODO. */ +/* USB support */ #ifndef SIMULATOR -#define USB_NONE +#define CONFIG_USBOTG USBOTG_DESIGNWARE +#define USB_DW_TURNAROUND 5 +#define HAVE_USBSTACK +#define USB_VENDOR_ID 0x2972 +#define USB_PRODUCT_ID 0x0003 +#define USB_DEVBSS_ATTR __attribute__((aligned(32))) +#define HAVE_USB_POWER +#define HAVE_USB_CHARGING_ENABLE +#define HAVE_BOOTLOADER_USB_MODE #endif /* Rockbox capabilities */ diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c index a3760d145a..c346d16890 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c @@ -23,6 +23,9 @@ #include "adc.h" #include "system.h" #include "kernel.h" +#ifdef HAVE_USB_CHARGING_ENABLE +# include "usb_core.h" +#endif #include "axp173.h" #include "i2c-x1000.h" #include "gpio-x1000.h" @@ -81,6 +84,13 @@ void power_init(void) mdelay(5); } +#ifdef HAVE_USB_CHARGING_ENABLE +void usb_charging_maxcurrent_change(int maxcurrent) +{ + axp173_set_charge_current(maxcurrent); +} +#endif + void adc_init(void) { } diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h index 45a1eab1ff..e5e48e382b 100644 --- a/firmware/target/mips/ingenic_x1000/system-target.h +++ b/firmware/target/mips/ingenic_x1000/system-target.h @@ -42,6 +42,9 @@ # define X1000_CPUIDLE_STATS #endif +#define OTGBASE 0xb3500000 +#define USB_NUM_ENDPOINTS 9 + #include "mmu-mips.h" #include "mipsregs.h" #include "mipsr2-endian.h" diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c index 33d8db7222..c0b0dbc65e 100644 --- a/firmware/target/mips/ingenic_x1000/system-x1000.c +++ b/firmware/target/mips/ingenic_x1000/system-x1000.c @@ -191,6 +191,8 @@ static void UIRQ(void) } #define intr(name) extern __attribute__((weak, alias("UIRQ"))) void name(void) +/* DWC2 USB interrupt */ +#define OTG INT_USB_FUNC /* Main interrupts */ intr(DMIC); intr(AIC); intr(SFC); intr(SSI0); intr(OTG); intr(AES); diff --git a/firmware/target/mips/ingenic_x1000/usb-x1000.c b/firmware/target/mips/ingenic_x1000/usb-x1000.c new file mode 100644 index 0000000000..32413b0b94 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/usb-x1000.c @@ -0,0 +1,223 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2021 Aidan MacDonald + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "system.h" +#include "usb.h" +#include "usb_core.h" +#include "usb_drv.h" +#include "usb-designware.h" +#include "irq-x1000.h" +#include "gpio-x1000.h" +#include "x1000/cpm.h" + +#ifdef FIIO_M3K +# define USB_DETECT_PORT GPIO_B +# define USB_DETECT_PIN (1 << 11) +# define USB_DETECT_PIN_INT GPIOB11 +# define USB_ID_PORT GPIO_B +# define USB_ID_PIN (1 << 7) +#else +# ifndef USB_NONE +# error "please add USB GPIO pins" +# endif +#endif + +#define USB_DRVVBUS_PORT GPIO_B +#define USB_DRVVBUS_PIN (1 << 25) + +/* + * USB-Designware driver API + */ + +const struct usb_dw_config usb_dw_config = { + .phytype = DWC_PHYTYPE_UTMI_16, + + /* Available FIFO memory: 3576 words */ + .rx_fifosz = 1024, + .nptx_fifosz = 128, /* 1 dedicated FIFO for EP0 */ + .ptx_fifosz = 768, /* 3 dedicated FIFOs */ + +#ifndef USB_DW_ARCH_SLAVE + .ahb_burst_len = HBSTLEN_INCR16, + /* Disable Rx FIFO thresholding. It appears to cause problems, + * apparently a known issue -- Synopsys recommends disabling it + * because it can cause issues during certain error conditions. + */ + .ahb_threshold = 0, +#else + .disable_double_buffering = false, +#endif +}; + +/* USB PHY init from Linux kernel code: + * - arch/mips/xburst/soc-x1000/common/cpm_usb.c + * Copyright (C) 2005-2017 Ingenic Semiconductor + */ +void usb_dw_target_enable_clocks(void) +{ + /* Enable CPM clock */ + jz_writef(CPM_CLKGR, OTG(0)); +#if X1000_EXCLK_FREQ == 24000000 + jz_writef(CPM_USBCDR, CLKSRC_V(EXCLK), CE(1), CLKDIV(0), PHY_GATE(0)); +#else +# error "please add USB clock settings for 26 MHz EXCLK" +#endif + while(jz_readf(CPM_USBCDR, BUSY)); + jz_writef(CPM_USBCDR, CE(0)); + + /* PHY soft reset */ + jz_writef(CPM_SRBC, OTG_SR(1)); + udelay(10); + jz_writef(CPM_SRBC, OTG_SR(0)); + + /* Ungate PHY clock */ + jz_writef(CPM_OPCR, GATE_USBPHY_CLK(0)); + + /* Exit suspend state */ + jz_writef(CPM_OPCR, SPENDN0(1)); + udelay(45); + + /* Program core configuration */ + jz_overwritef(CPM_USBVBFIL, + IDDIGFIL(0), + VBFIL(0)); + jz_overwritef(CPM_USBRDT, + HB_MASK(0), + VBFIL_LD_EN(1), + IDDIG_EN(0), + RDT(0x96)); + jz_overwritef(CPM_USBPCR, + OTG_DISABLE(1), + COMMONONN(1), + VBUSVLDEXT(1), + VBUSVLDEXTSEL(1), + SQRXTUNE(7), + TXPREEMPHTUNE(1), + TXHSXVTUNE(1), + TXVREFTUNE(7)); + jz_overwritef(CPM_USBPCR1, + BVLD_REG(1), + REFCLK_SEL_V(CLKCORE), + REFCLK_DIV_V(24MHZ), /* applies for 26 MHz EXCLK too */ + WORD_IF_V(16BIT)); + + /* Power on reset */ + jz_writef(CPM_USBPCR, POR(1)); + mdelay(1); + jz_writef(CPM_USBPCR, POR(0)); + mdelay(1); +} + +void usb_dw_target_disable_clocks(void) +{ + /* Suspend and power down PHY, then gate its clock */ + jz_writef(CPM_OPCR, SPENDN0(0)); + udelay(5); + jz_writef(CPM_USBPCR, OTG_DISABLE(1), SIDDQ(1)); + jz_writef(CPM_OPCR, GATE_USBPHY_CLK(1)); + + /* Disable CPM clock */ + jz_writef(CPM_USBCDR, CE(1), STOP(1), PHY_GATE(1)); + while(jz_readf(CPM_USBCDR, BUSY)); + jz_writef(CPM_USBCDR, CE(0)); + jz_writef(CPM_CLKGR, OTG(1)); +} + +void usb_dw_target_enable_irq(void) +{ + system_enable_irq(IRQ_OTG); +} + +void usb_dw_target_disable_irq(void) +{ + system_disable_irq(IRQ_OTG); +} + +void usb_dw_target_clear_irq(void) +{ +} + +/* + * Rockbox API + */ + +#ifdef USB_STATUS_BY_EVENT +static volatile int usb_status = USB_EXTRACTED; +#endif + +static int __usb_detect(void) +{ + if(REG_GPIO_PIN(USB_DETECT_PORT) & USB_DETECT_PIN) + return USB_INSERTED; + else + return USB_EXTRACTED; +} + +void usb_enable(bool on) +{ + if(on) + usb_core_init(); + else + usb_core_exit(); +} + +void usb_init_device(void) +{ + /* Disable drvvbus pin -- it is only used when acting as a host, + * which Rockbox does not support */ + gpio_config(USB_DRVVBUS_PORT, USB_DRVVBUS_PIN, GPIO_OUTPUT(0)); + + /* Power up the core clocks to allow writing + to some registers needed to power it down */ + usb_dw_target_disable_irq(); + usb_dw_target_enable_clocks(); + usb_drv_exit(); + +#ifdef USB_STATUS_BY_EVENT + /* Setup USB detect pin IRQ */ + usb_status = __usb_detect(); + int level = (REG_GPIO_PIN(USB_DETECT_PORT) & USB_DETECT_PIN) ? 1 : 0; + gpio_config(USB_DETECT_PORT, USB_DETECT_PIN, GPIO_IRQ_EDGE(level ? 0 : 1)); + gpio_enable_irq(USB_DETECT_PORT, USB_DETECT_PIN); +#endif +} + +#ifndef USB_STATUS_BY_EVENT +int usb_detect(void) +{ + return __usb_detect(); +} +#else +int usb_detect(void) +{ + return usb_status; +} + +void USB_DETECT_PIN_INT(void) +{ + /* Update status and flip the IRQ trigger edge */ + usb_status = __usb_detect(); + REG_GPIO_PAT0(USB_DETECT_PORT) ^= USB_DETECT_PIN; + + /* Notify Rockbox of event */ + usb_status_event(usb_status); +} +#endif diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h index 752d270f20..8c5d74b2e9 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/cpm.h +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h @@ -401,6 +401,51 @@ #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL +#define REG_CPM_USBCDR jz_reg(CPM_USBCDR) +#define JA_CPM_USBCDR (0xb0000000 + 0x50) +#define JT_CPM_USBCDR JIO_32_RW +#define JN_CPM_USBCDR CPM_USBCDR +#define JI_CPM_USBCDR +#define BP_CPM_USBCDR_CLKSRC 30 +#define BM_CPM_USBCDR_CLKSRC 0xc0000000 +#define BV_CPM_USBCDR_CLKSRC__EXCLK 0x0 +#define BV_CPM_USBCDR_CLKSRC__SCLK_A 0x2 +#define BV_CPM_USBCDR_CLKSRC__MPLL 0x3 +#define BF_CPM_USBCDR_CLKSRC(v) (((v) & 0x3) << 30) +#define BFM_CPM_USBCDR_CLKSRC(v) BM_CPM_USBCDR_CLKSRC +#define BF_CPM_USBCDR_CLKSRC_V(e) BF_CPM_USBCDR_CLKSRC(BV_CPM_USBCDR_CLKSRC__##e) +#define BFM_CPM_USBCDR_CLKSRC_V(v) BM_CPM_USBCDR_CLKSRC +#define BP_CPM_USBCDR_CLKDIV 0 +#define BM_CPM_USBCDR_CLKDIV 0xff +#define BF_CPM_USBCDR_CLKDIV(v) (((v) & 0xff) << 0) +#define BFM_CPM_USBCDR_CLKDIV(v) BM_CPM_USBCDR_CLKDIV +#define BF_CPM_USBCDR_CLKDIV_V(e) BF_CPM_USBCDR_CLKDIV(BV_CPM_USBCDR_CLKDIV__##e) +#define BFM_CPM_USBCDR_CLKDIV_V(v) BM_CPM_USBCDR_CLKDIV +#define BP_CPM_USBCDR_CE 29 +#define BM_CPM_USBCDR_CE 0x20000000 +#define BF_CPM_USBCDR_CE(v) (((v) & 0x1) << 29) +#define BFM_CPM_USBCDR_CE(v) BM_CPM_USBCDR_CE +#define BF_CPM_USBCDR_CE_V(e) BF_CPM_USBCDR_CE(BV_CPM_USBCDR_CE__##e) +#define BFM_CPM_USBCDR_CE_V(v) BM_CPM_USBCDR_CE +#define BP_CPM_USBCDR_BUSY 28 +#define BM_CPM_USBCDR_BUSY 0x10000000 +#define BF_CPM_USBCDR_BUSY(v) (((v) & 0x1) << 28) +#define BFM_CPM_USBCDR_BUSY(v) BM_CPM_USBCDR_BUSY +#define BF_CPM_USBCDR_BUSY_V(e) BF_CPM_USBCDR_BUSY(BV_CPM_USBCDR_BUSY__##e) +#define BFM_CPM_USBCDR_BUSY_V(v) BM_CPM_USBCDR_BUSY +#define BP_CPM_USBCDR_STOP 27 +#define BM_CPM_USBCDR_STOP 0x8000000 +#define BF_CPM_USBCDR_STOP(v) (((v) & 0x1) << 27) +#define BFM_CPM_USBCDR_STOP(v) BM_CPM_USBCDR_STOP +#define BF_CPM_USBCDR_STOP_V(e) BF_CPM_USBCDR_STOP(BV_CPM_USBCDR_STOP__##e) +#define BFM_CPM_USBCDR_STOP_V(v) BM_CPM_USBCDR_STOP +#define BP_CPM_USBCDR_PHY_GATE 26 +#define BM_CPM_USBCDR_PHY_GATE 0x4000000 +#define BF_CPM_USBCDR_PHY_GATE(v) (((v) & 0x1) << 26) +#define BFM_CPM_USBCDR_PHY_GATE(v) BM_CPM_USBCDR_PHY_GATE +#define BF_CPM_USBCDR_PHY_GATE_V(e) BF_CPM_USBCDR_PHY_GATE(BV_CPM_USBCDR_PHY_GATE__##e) +#define BFM_CPM_USBCDR_PHY_GATE_V(v) BM_CPM_USBCDR_PHY_GATE + #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) #define JA_CPM_SSICDR (0xb0000000 + 0x74) #define JT_CPM_SSICDR JIO_32_RW @@ -447,12 +492,265 @@ #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP +#define REG_CPM_INTR jz_reg(CPM_INTR) +#define JA_CPM_INTR (0xb0000000 + 0xb0) +#define JT_CPM_INTR JIO_32_RW +#define JN_CPM_INTR CPM_INTR +#define JI_CPM_INTR +#define BP_CPM_INTR_VBUS 1 +#define BM_CPM_INTR_VBUS 0x2 +#define BF_CPM_INTR_VBUS(v) (((v) & 0x1) << 1) +#define BFM_CPM_INTR_VBUS(v) BM_CPM_INTR_VBUS +#define BF_CPM_INTR_VBUS_V(e) BF_CPM_INTR_VBUS(BV_CPM_INTR_VBUS__##e) +#define BFM_CPM_INTR_VBUS_V(v) BM_CPM_INTR_VBUS +#define BP_CPM_INTR_ADEV 0 +#define BM_CPM_INTR_ADEV 0x1 +#define BF_CPM_INTR_ADEV(v) (((v) & 0x1) << 0) +#define BFM_CPM_INTR_ADEV(v) BM_CPM_INTR_ADEV +#define BF_CPM_INTR_ADEV_V(e) BF_CPM_INTR_ADEV(BV_CPM_INTR_ADEV__##e) +#define BFM_CPM_INTR_ADEV_V(v) BM_CPM_INTR_ADEV + +#define REG_CPM_INTR_EN jz_reg(CPM_INTR_EN) +#define JA_CPM_INTR_EN (0xb0000000 + 0xb4) +#define JT_CPM_INTR_EN JIO_32_RW +#define JN_CPM_INTR_EN CPM_INTR_EN +#define JI_CPM_INTR_EN +#define BP_CPM_INTR_EN_VBUS 1 +#define BM_CPM_INTR_EN_VBUS 0x2 +#define BF_CPM_INTR_EN_VBUS(v) (((v) & 0x1) << 1) +#define BFM_CPM_INTR_EN_VBUS(v) BM_CPM_INTR_EN_VBUS +#define BF_CPM_INTR_EN_VBUS_V(e) BF_CPM_INTR_EN_VBUS(BV_CPM_INTR_EN_VBUS__##e) +#define BFM_CPM_INTR_EN_VBUS_V(v) BM_CPM_INTR_EN_VBUS +#define BP_CPM_INTR_EN_ADEV 0 +#define BM_CPM_INTR_EN_ADEV 0x1 +#define BF_CPM_INTR_EN_ADEV(v) (((v) & 0x1) << 0) +#define BFM_CPM_INTR_EN_ADEV(v) BM_CPM_INTR_EN_ADEV +#define BF_CPM_INTR_EN_ADEV_V(e) BF_CPM_INTR_EN_ADEV(BV_CPM_INTR_EN_ADEV__##e) +#define BFM_CPM_INTR_EN_ADEV_V(v) BM_CPM_INTR_EN_ADEV + #define REG_CPM_DRCG jz_reg(CPM_DRCG) #define JA_CPM_DRCG (0xb0000000 + 0xd0) #define JT_CPM_DRCG JIO_32_RW #define JN_CPM_DRCG CPM_DRCG #define JI_CPM_DRCG +#define REG_CPM_USBPCR jz_reg(CPM_USBPCR) +#define JA_CPM_USBPCR (0xb0000000 + 0x3c) +#define JT_CPM_USBPCR JIO_32_RW +#define JN_CPM_USBPCR CPM_USBPCR +#define JI_CPM_USBPCR +#define BP_CPM_USBPCR_IDPULLUP_MASK 28 +#define BM_CPM_USBPCR_IDPULLUP_MASK 0x30000000 +#define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS 0x2 +#define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS_SUSPEND 0x1 +#define BV_CPM_USBPCR_IDPULLUP_MASK__FROM_OTG 0x0 +#define BF_CPM_USBPCR_IDPULLUP_MASK(v) (((v) & 0x3) << 28) +#define BFM_CPM_USBPCR_IDPULLUP_MASK(v) BM_CPM_USBPCR_IDPULLUP_MASK +#define BF_CPM_USBPCR_IDPULLUP_MASK_V(e) BF_CPM_USBPCR_IDPULLUP_MASK(BV_CPM_USBPCR_IDPULLUP_MASK__##e) +#define BFM_CPM_USBPCR_IDPULLUP_MASK_V(v) BM_CPM_USBPCR_IDPULLUP_MASK +#define BP_CPM_USBPCR_COMPDISTUNE 17 +#define BM_CPM_USBPCR_COMPDISTUNE 0xe0000 +#define BF_CPM_USBPCR_COMPDISTUNE(v) (((v) & 0x7) << 17) +#define BFM_CPM_USBPCR_COMPDISTUNE(v) BM_CPM_USBPCR_COMPDISTUNE +#define BF_CPM_USBPCR_COMPDISTUNE_V(e) BF_CPM_USBPCR_COMPDISTUNE(BV_CPM_USBPCR_COMPDISTUNE__##e) +#define BFM_CPM_USBPCR_COMPDISTUNE_V(v) BM_CPM_USBPCR_COMPDISTUNE +#define BP_CPM_USBPCR_OTGTUNE 14 +#define BM_CPM_USBPCR_OTGTUNE 0x1c000 +#define BF_CPM_USBPCR_OTGTUNE(v) (((v) & 0x7) << 14) +#define BFM_CPM_USBPCR_OTGTUNE(v) BM_CPM_USBPCR_OTGTUNE +#define BF_CPM_USBPCR_OTGTUNE_V(e) BF_CPM_USBPCR_OTGTUNE(BV_CPM_USBPCR_OTGTUNE__##e) +#define BFM_CPM_USBPCR_OTGTUNE_V(v) BM_CPM_USBPCR_OTGTUNE +#define BP_CPM_USBPCR_SQRXTUNE 11 +#define BM_CPM_USBPCR_SQRXTUNE 0x3800 +#define BF_CPM_USBPCR_SQRXTUNE(v) (((v) & 0x7) << 11) +#define BFM_CPM_USBPCR_SQRXTUNE(v) BM_CPM_USBPCR_SQRXTUNE +#define BF_CPM_USBPCR_SQRXTUNE_V(e) BF_CPM_USBPCR_SQRXTUNE(BV_CPM_USBPCR_SQRXTUNE__##e) +#define BFM_CPM_USBPCR_SQRXTUNE_V(v) BM_CPM_USBPCR_SQRXTUNE +#define BP_CPM_USBPCR_TXFSLSTUNE 7 +#define BM_CPM_USBPCR_TXFSLSTUNE 0x780 +#define BF_CPM_USBPCR_TXFSLSTUNE(v) (((v) & 0xf) << 7) +#define BFM_CPM_USBPCR_TXFSLSTUNE(v) BM_CPM_USBPCR_TXFSLSTUNE +#define BF_CPM_USBPCR_TXFSLSTUNE_V(e) BF_CPM_USBPCR_TXFSLSTUNE(BV_CPM_USBPCR_TXFSLSTUNE__##e) +#define BFM_CPM_USBPCR_TXFSLSTUNE_V(v) BM_CPM_USBPCR_TXFSLSTUNE +#define BP_CPM_USBPCR_TXHSXVTUNE 4 +#define BM_CPM_USBPCR_TXHSXVTUNE 0x30 +#define BF_CPM_USBPCR_TXHSXVTUNE(v) (((v) & 0x3) << 4) +#define BFM_CPM_USBPCR_TXHSXVTUNE(v) BM_CPM_USBPCR_TXHSXVTUNE +#define BF_CPM_USBPCR_TXHSXVTUNE_V(e) BF_CPM_USBPCR_TXHSXVTUNE(BV_CPM_USBPCR_TXHSXVTUNE__##e) +#define BFM_CPM_USBPCR_TXHSXVTUNE_V(v) BM_CPM_USBPCR_TXHSXVTUNE +#define BP_CPM_USBPCR_TXVREFTUNE 0 +#define BM_CPM_USBPCR_TXVREFTUNE 0xf +#define BF_CPM_USBPCR_TXVREFTUNE(v) (((v) & 0xf) << 0) +#define BFM_CPM_USBPCR_TXVREFTUNE(v) BM_CPM_USBPCR_TXVREFTUNE +#define BF_CPM_USBPCR_TXVREFTUNE_V(e) BF_CPM_USBPCR_TXVREFTUNE(BV_CPM_USBPCR_TXVREFTUNE__##e) +#define BFM_CPM_USBPCR_TXVREFTUNE_V(v) BM_CPM_USBPCR_TXVREFTUNE +#define BP_CPM_USBPCR_USB_MODE 31 +#define BM_CPM_USBPCR_USB_MODE 0x80000000 +#define BV_CPM_USBPCR_USB_MODE__USB 0x0 +#define BV_CPM_USBPCR_USB_MODE__OTG 0x1 +#define BF_CPM_USBPCR_USB_MODE(v) (((v) & 0x1) << 31) +#define BFM_CPM_USBPCR_USB_MODE(v) BM_CPM_USBPCR_USB_MODE +#define BF_CPM_USBPCR_USB_MODE_V(e) BF_CPM_USBPCR_USB_MODE(BV_CPM_USBPCR_USB_MODE__##e) +#define BFM_CPM_USBPCR_USB_MODE_V(v) BM_CPM_USBPCR_USB_MODE +#define BP_CPM_USBPCR_AVLD_REG 30 +#define BM_CPM_USBPCR_AVLD_REG 0x40000000 +#define BF_CPM_USBPCR_AVLD_REG(v) (((v) & 0x1) << 30) +#define BFM_CPM_USBPCR_AVLD_REG(v) BM_CPM_USBPCR_AVLD_REG +#define BF_CPM_USBPCR_AVLD_REG_V(e) BF_CPM_USBPCR_AVLD_REG(BV_CPM_USBPCR_AVLD_REG__##e) +#define BFM_CPM_USBPCR_AVLD_REG_V(v) BM_CPM_USBPCR_AVLD_REG +#define BP_CPM_USBPCR_INCR_MASK 27 +#define BM_CPM_USBPCR_INCR_MASK 0x8000000 +#define BF_CPM_USBPCR_INCR_MASK(v) (((v) & 0x1) << 27) +#define BFM_CPM_USBPCR_INCR_MASK(v) BM_CPM_USBPCR_INCR_MASK +#define BF_CPM_USBPCR_INCR_MASK_V(e) BF_CPM_USBPCR_INCR_MASK(BV_CPM_USBPCR_INCR_MASK__##e) +#define BFM_CPM_USBPCR_INCR_MASK_V(v) BM_CPM_USBPCR_INCR_MASK +#define BP_CPM_USBPCR_TXRISETUNE 26 +#define BM_CPM_USBPCR_TXRISETUNE 0x4000000 +#define BF_CPM_USBPCR_TXRISETUNE(v) (((v) & 0x1) << 26) +#define BFM_CPM_USBPCR_TXRISETUNE(v) BM_CPM_USBPCR_TXRISETUNE +#define BF_CPM_USBPCR_TXRISETUNE_V(e) BF_CPM_USBPCR_TXRISETUNE(BV_CPM_USBPCR_TXRISETUNE__##e) +#define BFM_CPM_USBPCR_TXRISETUNE_V(v) BM_CPM_USBPCR_TXRISETUNE +#define BP_CPM_USBPCR_COMMONONN 25 +#define BM_CPM_USBPCR_COMMONONN 0x2000000 +#define BF_CPM_USBPCR_COMMONONN(v) (((v) & 0x1) << 25) +#define BFM_CPM_USBPCR_COMMONONN(v) BM_CPM_USBPCR_COMMONONN +#define BF_CPM_USBPCR_COMMONONN_V(e) BF_CPM_USBPCR_COMMONONN(BV_CPM_USBPCR_COMMONONN__##e) +#define BFM_CPM_USBPCR_COMMONONN_V(v) BM_CPM_USBPCR_COMMONONN +#define BP_CPM_USBPCR_VBUSVLDEXT 24 +#define BM_CPM_USBPCR_VBUSVLDEXT 0x1000000 +#define BF_CPM_USBPCR_VBUSVLDEXT(v) (((v) & 0x1) << 24) +#define BFM_CPM_USBPCR_VBUSVLDEXT(v) BM_CPM_USBPCR_VBUSVLDEXT +#define BF_CPM_USBPCR_VBUSVLDEXT_V(e) BF_CPM_USBPCR_VBUSVLDEXT(BV_CPM_USBPCR_VBUSVLDEXT__##e) +#define BFM_CPM_USBPCR_VBUSVLDEXT_V(v) BM_CPM_USBPCR_VBUSVLDEXT +#define BP_CPM_USBPCR_VBUSVLDEXTSEL 23 +#define BM_CPM_USBPCR_VBUSVLDEXTSEL 0x800000 +#define BF_CPM_USBPCR_VBUSVLDEXTSEL(v) (((v) & 0x1) << 23) +#define BFM_CPM_USBPCR_VBUSVLDEXTSEL(v) BM_CPM_USBPCR_VBUSVLDEXTSEL +#define BF_CPM_USBPCR_VBUSVLDEXTSEL_V(e) BF_CPM_USBPCR_VBUSVLDEXTSEL(BV_CPM_USBPCR_VBUSVLDEXTSEL__##e) +#define BFM_CPM_USBPCR_VBUSVLDEXTSEL_V(v) BM_CPM_USBPCR_VBUSVLDEXTSEL +#define BP_CPM_USBPCR_POR 22 +#define BM_CPM_USBPCR_POR 0x400000 +#define BF_CPM_USBPCR_POR(v) (((v) & 0x1) << 22) +#define BFM_CPM_USBPCR_POR(v) BM_CPM_USBPCR_POR +#define BF_CPM_USBPCR_POR_V(e) BF_CPM_USBPCR_POR(BV_CPM_USBPCR_POR__##e) +#define BFM_CPM_USBPCR_POR_V(v) BM_CPM_USBPCR_POR +#define BP_CPM_USBPCR_SIDDQ 21 +#define BM_CPM_USBPCR_SIDDQ 0x200000 +#define BF_CPM_USBPCR_SIDDQ(v) (((v) & 0x1) << 21) +#define BFM_CPM_USBPCR_SIDDQ(v) BM_CPM_USBPCR_SIDDQ +#define BF_CPM_USBPCR_SIDDQ_V(e) BF_CPM_USBPCR_SIDDQ(BV_CPM_USBPCR_SIDDQ__##e) +#define BFM_CPM_USBPCR_SIDDQ_V(v) BM_CPM_USBPCR_SIDDQ +#define BP_CPM_USBPCR_OTG_DISABLE 20 +#define BM_CPM_USBPCR_OTG_DISABLE 0x100000 +#define BF_CPM_USBPCR_OTG_DISABLE(v) (((v) & 0x1) << 20) +#define BFM_CPM_USBPCR_OTG_DISABLE(v) BM_CPM_USBPCR_OTG_DISABLE +#define BF_CPM_USBPCR_OTG_DISABLE_V(e) BF_CPM_USBPCR_OTG_DISABLE(BV_CPM_USBPCR_OTG_DISABLE__##e) +#define BFM_CPM_USBPCR_OTG_DISABLE_V(v) BM_CPM_USBPCR_OTG_DISABLE +#define BP_CPM_USBPCR_TXPREEMPHTUNE 6 +#define BM_CPM_USBPCR_TXPREEMPHTUNE 0x40 +#define BF_CPM_USBPCR_TXPREEMPHTUNE(v) (((v) & 0x1) << 6) +#define BFM_CPM_USBPCR_TXPREEMPHTUNE(v) BM_CPM_USBPCR_TXPREEMPHTUNE +#define BF_CPM_USBPCR_TXPREEMPHTUNE_V(e) BF_CPM_USBPCR_TXPREEMPHTUNE(BV_CPM_USBPCR_TXPREEMPHTUNE__##e) +#define BFM_CPM_USBPCR_TXPREEMPHTUNE_V(v) BM_CPM_USBPCR_TXPREEMPHTUNE + +#define REG_CPM_USBRDT jz_reg(CPM_USBRDT) +#define JA_CPM_USBRDT (0xb0000000 + 0x40) +#define JT_CPM_USBRDT JIO_32_RW +#define JN_CPM_USBRDT CPM_USBRDT +#define JI_CPM_USBRDT +#define BP_CPM_USBRDT_RDT 0 +#define BM_CPM_USBRDT_RDT 0x7fffff +#define BF_CPM_USBRDT_RDT(v) (((v) & 0x7fffff) << 0) +#define BFM_CPM_USBRDT_RDT(v) BM_CPM_USBRDT_RDT +#define BF_CPM_USBRDT_RDT_V(e) BF_CPM_USBRDT_RDT(BV_CPM_USBRDT_RDT__##e) +#define BFM_CPM_USBRDT_RDT_V(v) BM_CPM_USBRDT_RDT +#define BP_CPM_USBRDT_HB_MASK 26 +#define BM_CPM_USBRDT_HB_MASK 0x4000000 +#define BF_CPM_USBRDT_HB_MASK(v) (((v) & 0x1) << 26) +#define BFM_CPM_USBRDT_HB_MASK(v) BM_CPM_USBRDT_HB_MASK +#define BF_CPM_USBRDT_HB_MASK_V(e) BF_CPM_USBRDT_HB_MASK(BV_CPM_USBRDT_HB_MASK__##e) +#define BFM_CPM_USBRDT_HB_MASK_V(v) BM_CPM_USBRDT_HB_MASK +#define BP_CPM_USBRDT_VBFIL_LD_EN 25 +#define BM_CPM_USBRDT_VBFIL_LD_EN 0x2000000 +#define BF_CPM_USBRDT_VBFIL_LD_EN(v) (((v) & 0x1) << 25) +#define BFM_CPM_USBRDT_VBFIL_LD_EN(v) BM_CPM_USBRDT_VBFIL_LD_EN +#define BF_CPM_USBRDT_VBFIL_LD_EN_V(e) BF_CPM_USBRDT_VBFIL_LD_EN(BV_CPM_USBRDT_VBFIL_LD_EN__##e) +#define BFM_CPM_USBRDT_VBFIL_LD_EN_V(v) BM_CPM_USBRDT_VBFIL_LD_EN +#define BP_CPM_USBRDT_IDDIG_EN 24 +#define BM_CPM_USBRDT_IDDIG_EN 0x1000000 +#define BF_CPM_USBRDT_IDDIG_EN(v) (((v) & 0x1) << 24) +#define BFM_CPM_USBRDT_IDDIG_EN(v) BM_CPM_USBRDT_IDDIG_EN +#define BF_CPM_USBRDT_IDDIG_EN_V(e) BF_CPM_USBRDT_IDDIG_EN(BV_CPM_USBRDT_IDDIG_EN__##e) +#define BFM_CPM_USBRDT_IDDIG_EN_V(v) BM_CPM_USBRDT_IDDIG_EN +#define BP_CPM_USBRDT_IDDIG_REG 23 +#define BM_CPM_USBRDT_IDDIG_REG 0x800000 +#define BF_CPM_USBRDT_IDDIG_REG(v) (((v) & 0x1) << 23) +#define BFM_CPM_USBRDT_IDDIG_REG(v) BM_CPM_USBRDT_IDDIG_REG +#define BF_CPM_USBRDT_IDDIG_REG_V(e) BF_CPM_USBRDT_IDDIG_REG(BV_CPM_USBRDT_IDDIG_REG__##e) +#define BFM_CPM_USBRDT_IDDIG_REG_V(v) BM_CPM_USBRDT_IDDIG_REG + +#define REG_CPM_USBVBFIL jz_reg(CPM_USBVBFIL) +#define JA_CPM_USBVBFIL (0xb0000000 + 0x44) +#define JT_CPM_USBVBFIL JIO_32_RW +#define JN_CPM_USBVBFIL CPM_USBVBFIL +#define JI_CPM_USBVBFIL +#define BP_CPM_USBVBFIL_IDDIGFIL 16 +#define BM_CPM_USBVBFIL_IDDIGFIL 0xffff0000 +#define BF_CPM_USBVBFIL_IDDIGFIL(v) (((v) & 0xffff) << 16) +#define BFM_CPM_USBVBFIL_IDDIGFIL(v) BM_CPM_USBVBFIL_IDDIGFIL +#define BF_CPM_USBVBFIL_IDDIGFIL_V(e) BF_CPM_USBVBFIL_IDDIGFIL(BV_CPM_USBVBFIL_IDDIGFIL__##e) +#define BFM_CPM_USBVBFIL_IDDIGFIL_V(v) BM_CPM_USBVBFIL_IDDIGFIL +#define BP_CPM_USBVBFIL_VBFIL 0 +#define BM_CPM_USBVBFIL_VBFIL 0xffff +#define BF_CPM_USBVBFIL_VBFIL(v) (((v) & 0xffff) << 0) +#define BFM_CPM_USBVBFIL_VBFIL(v) BM_CPM_USBVBFIL_VBFIL +#define BF_CPM_USBVBFIL_VBFIL_V(e) BF_CPM_USBVBFIL_VBFIL(BV_CPM_USBVBFIL_VBFIL__##e) +#define BFM_CPM_USBVBFIL_VBFIL_V(v) BM_CPM_USBVBFIL_VBFIL + +#define REG_CPM_USBPCR1 jz_reg(CPM_USBPCR1) +#define JA_CPM_USBPCR1 (0xb0000000 + 0x48) +#define JT_CPM_USBPCR1 JIO_32_RW +#define JN_CPM_USBPCR1 CPM_USBPCR1 +#define JI_CPM_USBPCR1 +#define BP_CPM_USBPCR1_REFCLK_SEL 26 +#define BM_CPM_USBPCR1_REFCLK_SEL 0xc000000 +#define BV_CPM_USBPCR1_REFCLK_SEL__CLKCORE 0x2 +#define BV_CPM_USBPCR1_REFCLK_SEL__EXTERNAL 0x1 +#define BV_CPM_USBPCR1_REFCLK_SEL__CRYSTAL 0x0 +#define BF_CPM_USBPCR1_REFCLK_SEL(v) (((v) & 0x3) << 26) +#define BFM_CPM_USBPCR1_REFCLK_SEL(v) BM_CPM_USBPCR1_REFCLK_SEL +#define BF_CPM_USBPCR1_REFCLK_SEL_V(e) BF_CPM_USBPCR1_REFCLK_SEL(BV_CPM_USBPCR1_REFCLK_SEL__##e) +#define BFM_CPM_USBPCR1_REFCLK_SEL_V(v) BM_CPM_USBPCR1_REFCLK_SEL +#define BP_CPM_USBPCR1_REFCLK_DIV 24 +#define BM_CPM_USBPCR1_REFCLK_DIV 0x3000000 +#define BV_CPM_USBPCR1_REFCLK_DIV__48MHZ 0x2 +#define BV_CPM_USBPCR1_REFCLK_DIV__24MHZ 0x1 +#define BV_CPM_USBPCR1_REFCLK_DIV__12MHZ 0x0 +#define BF_CPM_USBPCR1_REFCLK_DIV(v) (((v) & 0x3) << 24) +#define BFM_CPM_USBPCR1_REFCLK_DIV(v) BM_CPM_USBPCR1_REFCLK_DIV +#define BF_CPM_USBPCR1_REFCLK_DIV_V(e) BF_CPM_USBPCR1_REFCLK_DIV(BV_CPM_USBPCR1_REFCLK_DIV__##e) +#define BFM_CPM_USBPCR1_REFCLK_DIV_V(v) BM_CPM_USBPCR1_REFCLK_DIV +#define BP_CPM_USBPCR1_BVLD_REG 31 +#define BM_CPM_USBPCR1_BVLD_REG 0x80000000 +#define BF_CPM_USBPCR1_BVLD_REG(v) (((v) & 0x1) << 31) +#define BFM_CPM_USBPCR1_BVLD_REG(v) BM_CPM_USBPCR1_BVLD_REG +#define BF_CPM_USBPCR1_BVLD_REG_V(e) BF_CPM_USBPCR1_BVLD_REG(BV_CPM_USBPCR1_BVLD_REG__##e) +#define BFM_CPM_USBPCR1_BVLD_REG_V(v) BM_CPM_USBPCR1_BVLD_REG +#define BP_CPM_USBPCR1_PORT_RST 21 +#define BM_CPM_USBPCR1_PORT_RST 0x200000 +#define BF_CPM_USBPCR1_PORT_RST(v) (((v) & 0x1) << 21) +#define BFM_CPM_USBPCR1_PORT_RST(v) BM_CPM_USBPCR1_PORT_RST +#define BF_CPM_USBPCR1_PORT_RST_V(e) BF_CPM_USBPCR1_PORT_RST(BV_CPM_USBPCR1_PORT_RST__##e) +#define BFM_CPM_USBPCR1_PORT_RST_V(v) BM_CPM_USBPCR1_PORT_RST +#define BP_CPM_USBPCR1_WORD_IF 19 +#define BM_CPM_USBPCR1_WORD_IF 0x80000 +#define BV_CPM_USBPCR1_WORD_IF__16BIT 0x1 +#define BV_CPM_USBPCR1_WORD_IF__8BIT 0x0 +#define BF_CPM_USBPCR1_WORD_IF(v) (((v) & 0x1) << 19) +#define BFM_CPM_USBPCR1_WORD_IF(v) BM_CPM_USBPCR1_WORD_IF +#define BF_CPM_USBPCR1_WORD_IF_V(e) BF_CPM_USBPCR1_WORD_IF(BV_CPM_USBPCR1_WORD_IF__##e) +#define BFM_CPM_USBPCR1_WORD_IF_V(v) BM_CPM_USBPCR1_WORD_IF + #define REG_CPM_APCR jz_reg(CPM_APCR) #define JA_CPM_APCR (0xb0000000 + 0x10) #define JT_CPM_APCR JIO_32_RW @@ -791,6 +1089,102 @@ #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE +#define REG_CPM_SRBC jz_reg(CPM_SRBC) +#define JA_CPM_SRBC (0xb0000000 + 0xc4) +#define JT_CPM_SRBC JIO_32_RW +#define JN_CPM_SRBC CPM_SRBC +#define JI_CPM_SRBC +#define BP_CPM_SRBC_JPEG_SR 31 +#define BM_CPM_SRBC_JPEG_SR 0x80000000 +#define BF_CPM_SRBC_JPEG_SR(v) (((v) & 0x1) << 31) +#define BFM_CPM_SRBC_JPEG_SR(v) BM_CPM_SRBC_JPEG_SR +#define BF_CPM_SRBC_JPEG_SR_V(e) BF_CPM_SRBC_JPEG_SR(BV_CPM_SRBC_JPEG_SR__##e) +#define BFM_CPM_SRBC_JPEG_SR_V(v) BM_CPM_SRBC_JPEG_SR +#define BP_CPM_SRBC_JPEG_STOP 30 +#define BM_CPM_SRBC_JPEG_STOP 0x40000000 +#define BF_CPM_SRBC_JPEG_STOP(v) (((v) & 0x1) << 30) +#define BFM_CPM_SRBC_JPEG_STOP(v) BM_CPM_SRBC_JPEG_STOP +#define BF_CPM_SRBC_JPEG_STOP_V(e) BF_CPM_SRBC_JPEG_STOP(BV_CPM_SRBC_JPEG_STOP__##e) +#define BFM_CPM_SRBC_JPEG_STOP_V(v) BM_CPM_SRBC_JPEG_STOP +#define BP_CPM_SRBC_JPEG_ACK 29 +#define BM_CPM_SRBC_JPEG_ACK 0x20000000 +#define BF_CPM_SRBC_JPEG_ACK(v) (((v) & 0x1) << 29) +#define BFM_CPM_SRBC_JPEG_ACK(v) BM_CPM_SRBC_JPEG_ACK +#define BF_CPM_SRBC_JPEG_ACK_V(e) BF_CPM_SRBC_JPEG_ACK(BV_CPM_SRBC_JPEG_ACK__##e) +#define BFM_CPM_SRBC_JPEG_ACK_V(v) BM_CPM_SRBC_JPEG_ACK +#define BP_CPM_SRBC_LCD_SR 25 +#define BM_CPM_SRBC_LCD_SR 0x2000000 +#define BF_CPM_SRBC_LCD_SR(v) (((v) & 0x1) << 25) +#define BFM_CPM_SRBC_LCD_SR(v) BM_CPM_SRBC_LCD_SR +#define BF_CPM_SRBC_LCD_SR_V(e) BF_CPM_SRBC_LCD_SR(BV_CPM_SRBC_LCD_SR__##e) +#define BFM_CPM_SRBC_LCD_SR_V(v) BM_CPM_SRBC_LCD_SR +#define BP_CPM_SRBC_LCD_STOP 24 +#define BM_CPM_SRBC_LCD_STOP 0x1000000 +#define BF_CPM_SRBC_LCD_STOP(v) (((v) & 0x1) << 24) +#define BFM_CPM_SRBC_LCD_STOP(v) BM_CPM_SRBC_LCD_STOP +#define BF_CPM_SRBC_LCD_STOP_V(e) BF_CPM_SRBC_LCD_STOP(BV_CPM_SRBC_LCD_STOP__##e) +#define BFM_CPM_SRBC_LCD_STOP_V(v) BM_CPM_SRBC_LCD_STOP +#define BP_CPM_SRBC_LCD_ACK 23 +#define BM_CPM_SRBC_LCD_ACK 0x800000 +#define BF_CPM_SRBC_LCD_ACK(v) (((v) & 0x1) << 23) +#define BFM_CPM_SRBC_LCD_ACK(v) BM_CPM_SRBC_LCD_ACK +#define BF_CPM_SRBC_LCD_ACK_V(e) BF_CPM_SRBC_LCD_ACK(BV_CPM_SRBC_LCD_ACK__##e) +#define BFM_CPM_SRBC_LCD_ACK_V(v) BM_CPM_SRBC_LCD_ACK +#define BP_CPM_SRBC_CIM_STOP 21 +#define BM_CPM_SRBC_CIM_STOP 0x200000 +#define BF_CPM_SRBC_CIM_STOP(v) (((v) & 0x1) << 21) +#define BFM_CPM_SRBC_CIM_STOP(v) BM_CPM_SRBC_CIM_STOP +#define BF_CPM_SRBC_CIM_STOP_V(e) BF_CPM_SRBC_CIM_STOP(BV_CPM_SRBC_CIM_STOP__##e) +#define BFM_CPM_SRBC_CIM_STOP_V(v) BM_CPM_SRBC_CIM_STOP +#define BP_CPM_SRBC_CIM_ACK 20 +#define BM_CPM_SRBC_CIM_ACK 0x100000 +#define BF_CPM_SRBC_CIM_ACK(v) (((v) & 0x1) << 20) +#define BFM_CPM_SRBC_CIM_ACK(v) BM_CPM_SRBC_CIM_ACK +#define BF_CPM_SRBC_CIM_ACK_V(e) BF_CPM_SRBC_CIM_ACK(BV_CPM_SRBC_CIM_ACK__##e) +#define BFM_CPM_SRBC_CIM_ACK_V(v) BM_CPM_SRBC_CIM_ACK +#define BP_CPM_SRBC_CPU_STOP 15 +#define BM_CPM_SRBC_CPU_STOP 0x8000 +#define BF_CPM_SRBC_CPU_STOP(v) (((v) & 0x1) << 15) +#define BFM_CPM_SRBC_CPU_STOP(v) BM_CPM_SRBC_CPU_STOP +#define BF_CPM_SRBC_CPU_STOP_V(e) BF_CPM_SRBC_CPU_STOP(BV_CPM_SRBC_CPU_STOP__##e) +#define BFM_CPM_SRBC_CPU_STOP_V(v) BM_CPM_SRBC_CPU_STOP +#define BP_CPM_SRBC_CPU_ACK 14 +#define BM_CPM_SRBC_CPU_ACK 0x4000 +#define BF_CPM_SRBC_CPU_ACK(v) (((v) & 0x1) << 14) +#define BFM_CPM_SRBC_CPU_ACK(v) BM_CPM_SRBC_CPU_ACK +#define BF_CPM_SRBC_CPU_ACK_V(e) BF_CPM_SRBC_CPU_ACK(BV_CPM_SRBC_CPU_ACK__##e) +#define BFM_CPM_SRBC_CPU_ACK_V(v) BM_CPM_SRBC_CPU_ACK +#define BP_CPM_SRBC_OTG_SR 12 +#define BM_CPM_SRBC_OTG_SR 0x1000 +#define BF_CPM_SRBC_OTG_SR(v) (((v) & 0x1) << 12) +#define BFM_CPM_SRBC_OTG_SR(v) BM_CPM_SRBC_OTG_SR +#define BF_CPM_SRBC_OTG_SR_V(e) BF_CPM_SRBC_OTG_SR(BV_CPM_SRBC_OTG_SR__##e) +#define BFM_CPM_SRBC_OTG_SR_V(v) BM_CPM_SRBC_OTG_SR +#define BP_CPM_SRBC_AHB2_STOP 8 +#define BM_CPM_SRBC_AHB2_STOP 0x100 +#define BF_CPM_SRBC_AHB2_STOP(v) (((v) & 0x1) << 8) +#define BFM_CPM_SRBC_AHB2_STOP(v) BM_CPM_SRBC_AHB2_STOP +#define BF_CPM_SRBC_AHB2_STOP_V(e) BF_CPM_SRBC_AHB2_STOP(BV_CPM_SRBC_AHB2_STOP__##e) +#define BFM_CPM_SRBC_AHB2_STOP_V(v) BM_CPM_SRBC_AHB2_STOP +#define BP_CPM_SRBC_AHB2_ACK 7 +#define BM_CPM_SRBC_AHB2_ACK 0x80 +#define BF_CPM_SRBC_AHB2_ACK(v) (((v) & 0x1) << 7) +#define BFM_CPM_SRBC_AHB2_ACK(v) BM_CPM_SRBC_AHB2_ACK +#define BF_CPM_SRBC_AHB2_ACK_V(e) BF_CPM_SRBC_AHB2_ACK(BV_CPM_SRBC_AHB2_ACK__##e) +#define BFM_CPM_SRBC_AHB2_ACK_V(v) BM_CPM_SRBC_AHB2_ACK +#define BP_CPM_SRBC_DDR_STOP 6 +#define BM_CPM_SRBC_DDR_STOP 0x40 +#define BF_CPM_SRBC_DDR_STOP(v) (((v) & 0x1) << 6) +#define BFM_CPM_SRBC_DDR_STOP(v) BM_CPM_SRBC_DDR_STOP +#define BF_CPM_SRBC_DDR_STOP_V(e) BF_CPM_SRBC_DDR_STOP(BV_CPM_SRBC_DDR_STOP__##e) +#define BFM_CPM_SRBC_DDR_STOP_V(v) BM_CPM_SRBC_DDR_STOP +#define BP_CPM_SRBC_DDR_ACK 5 +#define BM_CPM_SRBC_DDR_ACK 0x20 +#define BF_CPM_SRBC_DDR_ACK(v) (((v) & 0x1) << 5) +#define BFM_CPM_SRBC_DDR_ACK(v) BM_CPM_SRBC_DDR_ACK +#define BF_CPM_SRBC_DDR_ACK_V(e) BF_CPM_SRBC_DDR_ACK(BV_CPM_SRBC_DDR_ACK__##e) +#define BFM_CPM_SRBC_DDR_ACK_V(v) BM_CPM_SRBC_DDR_ACK + #define REG_CPM_OPCR jz_reg(CPM_OPCR) #define JA_CPM_OPCR (0xb0000000 + 0x24) #define JT_CPM_OPCR JIO_32_RW diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index 39ad26e782..0d971c59f8 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen @@ -435,6 +435,17 @@ node CPM { fld 7 0 CLKDIV } + reg USBCDR 0x50 { + fld 31 30 CLKSRC { enum EXCLK 0; enum SCLK_A 2; enum MPLL 3; } + bit 29 CE + bit 28 BUSY + bit 27 STOP + # PHY_GATE bit undocumented but present in Ingenic kernel sources, + # it's not clear it does anything. + bit 26 PHY_GATE + fld 7 0 CLKDIV + } + reg SSICDR 0x74 { bit 31 SFC_CS { enum SCLK_A 0; enum MPLL 1 } bit 30 SSI_CS { enum EXCLK 0; enum HALF_SFC 1 } @@ -444,8 +455,60 @@ node CPM { fld 7 0 CLKDIV } + reg INTR 0xb0 { + bit 1 VBUS + bit 0 ADEV + } + + reg INTR_EN 0xb4 { + bit 1 VBUS + bit 0 ADEV + } + reg DRCG 0xd0 + reg USBPCR 0x3c { + bit 31 USB_MODE { enum USB 0; enum OTG 1; } + bit 30 AVLD_REG + fld 29 28 IDPULLUP_MASK { enum ALWAYS 2; enum ALWAYS_SUSPEND 1; enum FROM_OTG 0; } + bit 27 INCR_MASK + bit 26 TXRISETUNE + bit 25 COMMONONN + bit 24 VBUSVLDEXT + bit 23 VBUSVLDEXTSEL + bit 22 POR + bit 21 SIDDQ + bit 20 OTG_DISABLE + fld 19 17 COMPDISTUNE + fld 16 14 OTGTUNE + fld 13 11 SQRXTUNE + fld 10 7 TXFSLSTUNE + bit 6 TXPREEMPHTUNE + fld 5 4 TXHSXVTUNE + fld 3 0 TXVREFTUNE + } + + reg USBRDT 0x40 { + bit 26 HB_MASK + bit 25 VBFIL_LD_EN + bit 24 IDDIG_EN + bit 23 IDDIG_REG + fld 22 0 RDT + } + + reg USBVBFIL 0x44 { + fld 31 16 IDDIGFIL + fld 15 0 VBFIL + } + + reg USBPCR1 0x48 { + bit 31 BVLD_REG + fld 27 26 REFCLK_SEL { enum CLKCORE 2; enum EXTERNAL 1; enum CRYSTAL 0 } + fld 25 24 REFCLK_DIV { enum 48MHZ 2; enum 24MHZ 1; enum 12MHZ 0 } + bit 21 PORT_RST + bit 19 WORD_IF { enum 16BIT 1; enum 8BIT 0 } + } + reg APCR 0x10 { bit 31 BS fld 30 24 PLLM @@ -512,6 +575,24 @@ node CPM { bit 1 EFUSE } + reg SRBC 0xc4 { + bit 31 JPEG_SR + bit 30 JPEG_STOP + bit 29 JPEG_ACK + bit 25 LCD_SR + bit 24 LCD_STOP + bit 23 LCD_ACK + bit 21 CIM_STOP + bit 20 CIM_ACK + bit 15 CPU_STOP + bit 14 CPU_ACK + bit 12 OTG_SR + bit 8 AHB2_STOP + bit 7 AHB2_ACK + bit 6 DDR_STOP + bit 5 DDR_ACK + } + reg OPCR 0x24 { bit 31 IDLE_DIS bit 30 MASK_INT