diff --git a/www/Makefile b/www/Makefile new file mode 100644 index 0000000000..9a2e76e095 --- /dev/null +++ b/www/Makefile @@ -0,0 +1,44 @@ +ACTION=@echo preprocessing $@; rm -f $@; fcpp -WWW -Uunix -H -C -V -LL >$@ + +SRC := $(wildcard *.t) +OBJS := $(SRC:%.t=%.html) + +.SUFFIXES: .t .html + +%.html : %.t + $(ACTION) $< + +all: $(OBJS) descramble descramble.static.bz2 sh2d sh2d.static.bz2 \ + scramble scramble.static.bz2 + @(cd schematics; $(MAKE)) + @(cd docs; $(MAKE)) + @(cd mods; $(MAKE)) + +main.html: main.t activity.html + +descramble: descramble.c + cc -Wall -ansi -O2 -s -o $@ $< + chmod a+r descramble + +descramble.static.bz2: descramble.c + cc -static -O2 -s -o descramble.static $< + bzip2 -f descramble.static + chmod a+r descramble.static.bz2 + +scramble: scramble.c + cc -Wall -ansi -O2 -s -o $@ $< + chmod a+r scramble + +scramble.static.bz2: scramble.c + cc -static -O2 -s -o scramble.static $< + bzip2 -f scramble.static + chmod a+r scramble.static.bz2 + +sh2d: sh2d.c + cc -O2 -s -o $@ $< + chmod a+r sh2d + +sh2d.static.bz2: sh2d.c + cc -static -O2 -s -o sh2d.static $< + bzip2 -f sh2d.static + chmod a+r sh2d.static.bz2 diff --git a/www/activity.t b/www/activity.t new file mode 100644 index 0000000000..eabd0be18b --- /dev/null +++ b/www/activity.t @@ -0,0 +1,12 @@ +#define STATUS(_a_,_b_,_c_) \ +_a__b__c_ + + + +STATUS(Björn,I2C driver and MAS serial port,Idle - trying to repair his Archos...) +STATUS(Linus,Serial port GDB stub to bring remote debugging to the archos,Works well; some details left) +STATUS(Alan,FAT-32 file system and handling,Can create files. Not safe yet ;->) +STATUS(Daniel,GUI simulator for X11,Partly working) +STATUS(Rob,Assembling a FAQ,Just began) +
PersonActivityCurrent status
+Updated __DATE__ diff --git a/www/cross-gcc.t b/www/cross-gcc.t new file mode 100644 index 0000000000..8e6b72a66c --- /dev/null +++ b/www/cross-gcc.t @@ -0,0 +1,92 @@ +#define _PAGE_ Building the SH1 cross compiler +#include "head.t" + +

+In this example I will assume that you are running Linux with the bash shell. +We will only build the C compiler along with the assembler, linker and stuff. +

Download the source code

+

+You will need the following archives: +

+

Unpack the archives

+

+

+ /home/linus> tar zxf binutils-2.11.tar.gz
+ /home/linus> tar zxf gcc-3.0.3.tar.gz
+ /home/linus> tar zxf newlib-1.10.0.tar.gz
+ /home/linus> tar zxf gdb-5.1.1.tar.gz
+
+

Create the directory tree

+

+

+ /home/linus> mkdir build
+ /home/linus> cd build
+ /home/linus/build> mkdir binutils
+ /home/linus/build> mkdir gcc
+ /home/linus/build> mkdir gdb
+
+

Create the newlib and libgloss links

+

+The GCC configuration script finds the newlib and libgloss files if they are in the GCC tree. Let's create two soft links. +

+ /home/linus> cd gcc-3.0.3
+ /home/linus/gcc-3.0.3> ln -s ../newlib-1.10.0/newlib .
+ /home/linus/gcc-3.0.3> ln -s ../newlib-1.10.0/libgloss .
+
+

Make up your mind

+

+Now is the time to decide where you want the tools to be installed. This is +the directory where all binaries, libraries, man pages and stuff end up when +you do "make install". +

+In this example I have chosen "/home/linus/sh1" as my installation directory, or prefix as it is called. Feel free to use any prefix, like +/usr/local/sh1 for example. +

Build binutils

+

+We will start with building the binutils (the assembler, linker and stuff). +This is pretty straightforward. We will be installing the whole tool chain +in the /home/linus/sh1 directory. +

+ /home/linus> cd build/binutils
+ /home/linus/build/binutils> ../../binutils-2.11/configure --target=sh-elf --prefix=/home/linus/sh1
+ /home/linus/build/binutils> make
+ /home/linus/build/binutils> make install
+
+

Build GCC

+

+Now you are ready to build GCC. To do this, you must have the newly built +binutils in the PATH. +

+ /home/linus> export PATH=/home/linus/sh1/bin:$PATH
+ /home/linus> cd build/gcc
+ /home/linus/gcc> ../../gcc-3.0.3/configure --target=sh-elf --prefix=/home/linus/sh1 --with-newlib --enable-languages=c
+ /home/linus/build/binutils> make
+ /home/linus/build/binutils> make install
+
+

Build GDB

+

+If you are planning to debug your code with GDB, you have to build it as well. +

+ /home/linus> export PATH=/home/linus/sh1/bin:$PATH
+ /home/linus> cd build/gdb
+ /home/linus/gdb> ../../gdb-5.1.1/configure --target=sh-elf --prefix=/home/linus/sh1
+ /home/linus/build/binutils> make
+ /home/linus/build/binutils> make install
+
+

Done

+

+If someone up there likes you, you now have a working tool chain for SH1. +To compile a file with gcc: +

+ /home/linus> sh-elf-gcc -c main.o main.c
+
+Good luck! +

+Linus + +#include "foot.t" diff --git a/www/foot.t b/www/foot.t new file mode 100644 index 0000000000..459aa2d339 --- /dev/null +++ b/www/foot.t @@ -0,0 +1,4 @@ +

+Page was last modified __DATE__ Björn Stenberg + + diff --git a/www/head.t b/www/head.t new file mode 100644 index 0000000000..a0fab05043 --- /dev/null +++ b/www/head.t @@ -0,0 +1,25 @@ +#define BGCOLOR "#99ccff" +#define TITLE(_x)

_x

+ + + + +#ifdef _PAGE_ +Rockbox - _PAGE_ +#else +Rockbox +#endif + +#ifndef _PAGE_ + +#endif + + +#ifdef _LOGO_ +_LOGO_ +#else + + +TITLE(_PAGE_) +#endif + diff --git a/www/lock.t b/www/lock.t new file mode 100644 index 0000000000..0e6944f2b8 --- /dev/null +++ b/www/lock.t @@ -0,0 +1,44 @@ +#define _PAGE_ Unlocking a password protected harddisk +#include "head.t" + +

During development of the Rockbox firmware, on several occations the harddisk has become locked, i.e. password protected. This results in the Archos displaying: +

+Part. Error
+Pls Chck HD
+
+ +

We are still not 100% sure why it happens. Theories range from +low-power conditions to accidental chip select failure. +It has also happened for normal users, +using the standard Archos-supplied firmware, although it's more frequent for +us developers. + +

We do however know how to unlock the disk: + +

Windows/DOS unlock

+ +

Note: This requires taking the Archos apart, which will void your warranty! + +

    +
  1. Grab +atapwd +(written by +Alex Mina) +
  2. Create a bootable DOS floppy disk, and put atapwd.exe on it +
  3. Remove the harddisk from your Archos and plug it into a laptop (or a standard PC, using a 3.5" => 2.5" IDE adapter) +
  4. Boot from the floppy and run atapwd.exe +
  5. Select the locked harddrive and press enter for the menu +
  6. For Fujitsu disks: Choose "unlock with user password", then "disable with user password". The password is empty, so just press enter at the prompt. +
  7. For Toshiba disks, if the above doesn't work: Choose "unlock with master password", then "disable with master password". The password is all spaces. +
  8. Your disk is now unlocked. Shut down the computer and remove the disk. +
+ +

Big thanks to Magnus Andersson for discovering the Fujitsu (lack of) user password! + +

Linux unlock

+ +

For those of us using Linux, we have written +an isd200 driver patch for unlocking the disk. +This modified driver will automatically unlock the disk when you connect your Archos via USB, so you don't have to do anything special. Apply the patch to a 2.4.18 linux kernel tree. + +#include "foot.t" diff --git a/www/main.t b/www/main.t new file mode 100644 index 0000000000..c082692db2 --- /dev/null +++ b/www/main.t @@ -0,0 +1,212 @@ +#define _LOGO_ +#define _PAGE_ Open Source Jukebox Firmware +#include "head.t" + +

research notes · +data sheets · +schematics · +hardware mods · +mail list archive · +descrambler · +sh2d disassembler · +archos internals · +sourceforge project + + +

Purpose

+ +

The purpose of this project is to write an Open Source replacement +firmware for the Archos Jukebox 6000, Studio and Recorder MP3 players. + +

The main emphasis and first target is the Jukebox 6000. + +#if 0 +

Warning

+

All firmware mods on this page are still highly experimental. +Try them on your own risk. If you are not 100% sure of what you are doing, keep cool. +#endif + +

Activity

+ +#include "activity.html" + +

News

+ +

2002-03-25: New section for +hardware modifications. +First out is the long awaited +serial port mod. + +

2002-03-25: New instructions for +how to build an SH-1 cross-compiler. + +

2002-03-14: New linux patch and instructions for +unlocking the archos harddisk if you have the "Part. Error" problem. + +

2002-03-08: Uploaded a simple example, showing +how to build a program for the Archos. + +

2002-03-05: The +harddisk password lock problem is solved! +Development can now resume at full speed! + +

2002-01-29: If you have feature requests or suggestions, +please submit them to our +Sourceforge page. + +

2002-01-19: Cool logo submitted by Thomas Saeys. + +

2002-01-16: The project now has a proper name: Rockbox. +Logos are welcome! :-) +
Also, Felix Arends wrote a quick tutorial +for how to get sh-gcc running under windows. + +

2002-01-09: Nicolas Sauzede +found out +how to +display icons and custom characters on the Jukebox LCD. + +

2002-01-08: The two LCD charsets have been +mapped and drawn. + +

2002-01-07: +Jukebox LCD code. +I have written a small test program that scrolls some text on the display. +You need +this file +for units with ROM earlier than 4.50 and +this file +for all others. (The files are gzipped, you need to unzip them before they will work.) + +

2001-12-29: Recorder LCD code. Gary Czvitkovicz knew the Recorder LCD controller since before and wrote some +code +that writes text on the Recorder screen. + +

2001-12-13: First program +released! +A 550 bytes long +archos.mod +that performs the amazing magic of flashing the red LED. :-) + +

2001-12-11: Checksum algorithm solved, thanks to Andy Choi. A new "scramble" utility is available. + +

2001-12-09: Working my way through the setup code. The notes are being updated continously. + +

2001-12-08: Analyzed the exception vector table. See the notes. Also, a mailing list archive is up. + +

2001-12-07: + I just wrote this web page to announce descramble.c. +I've disassembled one firmware version and looked a bit on the code, but no real analysis yet. +Summary: Lots of dreams, very little reality. :-) + +

I've set up a mailing list: rockbox@cool.haxx.se. +To subscribe, send a message to majordomo@cool.haxx.se with the words "subscribe rockbox" in the body. + + +

About the hardware

+ +

I wrote a "dissection" page some months ago, +showing the inside of the Archos and listing the main components. +I have also collected a couple of data sheets. + +

About the software

+ +

The player has one version of the firmware burnt into flash ROM. +The first thing this version does after boot is to look for a file called +"archos.mod" in the root directory of the harddisk. +If it exists, it is loaded into RAM and started. +This is how firmware upgrades are loaded. + +

File format

+

The archos.mod file is scrambled, but luckily not using encryption. + +

Each data byte is inverted and ROLed 1 bit. +The data is then spread over four memory segments. The two least significant bits of the address is used as segment number and the rest as offset in the segment. So, basically: + +

+ +

A 6-byte header is added to the beginning of the scrambled image: +

+ + +

I've written a small utility to descramble firmware files: +

 + + +

...and one to scramble files: +

 + +

So?

+ +

We now have the possiblity to actually research how the Archos works +and create our own software for it. +There is of course a long way still to go before we can start playing +around with fancy mp3 features. + + +

Disassembler

+ +

I found a nice public domain SH-1/SH-2 disassembler written by Bart Trzynadlowski, called sh2d: +

Update: I've added address lookup and register name translation to the disassembler (2001-12-09) +

+ +

Compiler

+ +

GCC supports the SH processor. Just +cook yourself a cross-compiler +(sh-elf-gcc) and voila, instant SH-1 code. + +

There are also + +pre-cooked RH7.1 RPMs available from sh-linux.org + +

Dreams

+

Ok, forget about reality, what could we do with this? + +

+ +#include "foot.t" diff --git a/www/notes.t b/www/notes.t new file mode 100644 index 0000000000..71e40651d1 --- /dev/null +++ b/www/notes.t @@ -0,0 +1,411 @@ +#define _PAGE_ Jukebox notes +#include "head.t" + +

Exception vectors

+ +

The first 0x200 bytes of the image appears to be the exception vector table. +The vectors are explained on pages 54 and 70-71 in the SH-1 Hardware Manual, + +

Here's the vector table for v5.03a: + + + + + + + + + + + + + + + + + +
VectorAddressDescription/interrupt source
009000200Power-on reset PC
10903f2bcPower-on reset SP
209000200Manual reset PC
30903f2bcManual reset SP
1109000cacNMI
640900c060IRQ0
7009004934IRQ6
7809004a38DMAC3 DEI3
800900dfd0ITU0 IMIA0
880900df60ITU2 IMIA2
900900df60ITU2 OVI2
10409004918SCI1 ERI1
105090049e0SCI1 Rxl1
10909010270A/D ITI
+ +

From the use of address 0x0903f2bc as stack pointer, we can deduce +that the DRAM is located at address 0x09000000. +This is backed by the HW manual p102, which says that DRAM can only be at put on CS1, which is either 0x01000000 (8-bit) or 0x09000000 (16-bit). + +

The vector table also corresponds with the fact that there is code at address 0x200 of the image file. 0x200 is thus the starting point for all code. + +

Port pins

+

+ +

Port A pin function configuration summary: + + + + + + + + + + + + + + + + + + +
PinFunctionInput/outputInitial valueUsed for
PA0i/oInputDC adapter detect
PA1/RASOutputDRAM
PA2/CS6OutputIDE
PA3/WAIT
PA4/WROutputDRAM+Flash
PA5i/oInputKey: ON
PA6/RDOutputIDE
PA7i/oOutput0
PA8i/oOutput0
PA9i/oOutput1
PA10i/oOutput
PA11i/oInputKey: STOP
PA12/IRQ0
PA13i/o
PA14i/o
PA15i/oInputUSB cable detect
+ +

 + +

Port B pin function configuration summary: + + + + + + + + + + + + + + + + + + +
PinFunctionInput/outputInitial valueUsed for
PB0i/oOutputLCD
PB1i/oOutputLCD
PB2i/oOutputLCD
PB3i/oOutputLCD
PB4i/oInput
PB5i/oOutput1I²C data
PB6i/oOutput0
PB7i/oOutputI²C clock
PB8i/o
PB9TxD0OutputMPEG
PB10RxD1InputRemote
PB11TxD1OutputRemote?
PB12SCK0OutputMPEG
PB13i/o
PB14/IRQ6Input
PB15i/oInput
+ + +

+ +

Port C pin function configuration summary: + + + + + + + + + + +
PinFunctionInput/outputUsed for
PC0i/oInputKey: - / PREV
PC1i/oInputKey: MENU
PC2i/oInputKey: + / NEXT
PC3i/oInputKey: PLAY
PC4i/oInput
PC5i/oInput
PC6i/oInput
PC7i/oInput
+ + +

Labels

+

Note: Everything is about v5.03a. + +

+ + +

Setup

+ +

The startup code at 0x200 (0x09000200) naturally begins with setting up the system. + +

Vector Base Register

+ +

The first thing the code does is setting the VBR, Vector Base Register, +and thus move the exception vector table from the internal ROM at address 0 +to the DRAM at address 0x09000000: + +

+0x00000200: mov.l  @(0x02C,pc),r1  ; 0x0000022C (0x09000000)
+0x00000202: ldc	   r1,vbr
+
+ +

Stack

+ +

The next instruction loads r15 with the contents of 0x228, which is 0x0903f2bc. This is the stack pointer, which is used all over the code. + +

+0x00000204: mov.l  @(0x024,pc),r15 ; 0x00000228 (0x0903F2BC)
+
+ +

After that the code jumps to the hardware setup at 0xc8c0. +

+0x00000206: mov.l  @(0x01C,pc),r0   ; 0x00000220 (0x0900C8C0)
+0x00000208: jsr    @r0
+
+ +

DRAM controller

+ +

First up is DRAM setup, at 0xc8c8. It sets the memory controller registers: + +

+0x0000C8C8: mov.l  @(0x068,pc),r2  ; 0x0000C930 (0x05FFFFA8)
+0x0000C8CA: mov.w  @(0x05A,pc),r1  ; 0x0000C924 (0x1E00)
+0x0000C8CC: mov.l  @(0x068,pc),r7  ; 0x0000C934 (0x0F0001C0)
+0x0000C8CE: mov.w  r1,@r2          ; 0x1e00 -> DCR
+0x0000C8D0: mov.l  @(0x068,pc),r2  ; 0x0000C938 (0x05FFFFAC)
+0x0000C8D2: mov.w  @(0x054,pc),r1  ; 0x0000C926 (0x5AB0)
+0x0000C8D4: mov.w  r1,@r2          ; 0x5ab0 -> RCR
+0x0000C8D6: mov.l  @(0x068,pc),r2  ; 0x0000C93C (0x05FFFFB2)
+0x0000C8D8: mov.w  @(0x050,pc),r1  ; 0x0000C928 (0x9605)
+0x0000C8DA: mov.w  r1,@r2          ; 0x9505 -> RTCOR
+0x0000C8DC: mov.l  @(0x064,pc),r2  ; 0x0000C940 (0x05FFFFAE)
+0x0000C8DE: mov.w  @(0x04C,pc),r1  ; 0x0000C92A (0xA518)
+0x0000C8E0: mov.w  r1,@r2          ; 0xa518 -> RTCSR
+
+ +

Serial port 0

+ +

Code starting at 0x483c. + +

As C code: + +
+
+void setup_sci0(void)
+{
+    /* set PB12 to output */
+    PBIOR |= 0x1000;
+     
+    /* Disable serial port */
+    SCR0 = 0x00;
+ 
+    /* Syncronous, 8N1, no prescale */
+    SMR0 = 0x80;
+ 
+    /* Set baudrate 1Mbit/s */
+    BRR0 = 0x03;
+ 
+    /* use SCK as serial clock output */
+    SCR0 = 0x01;
+ 
+    /* Clear FER and PER */
+    SSR0 &= 0xe7;
+ 
+    /* Set interrupt D priority to 0 */
+    IPRD &= 0x0ff0;
+ 
+    /* set IRQ6 and IRQ7 to edge detect */
+    ICR |= 0x03;
+ 
+    /* set PB15 and PB14 to inputs */
+    PBIOR &= 0x7fff;
+    PBIOR &= 0xbfff;
+ 
+    /* set IRQ6 prio 8 and IRQ7 prio 0 */
+    IPRB = ( IPRB & 0xff00 ) | 0x80;
+ 
+    /* Enable Tx (only!) */
+    SCR0 = 0x20;
+}
+
+
+ + +

Serial port 1

+ +

Code starting at 0x47a0. + +

As C code: + +
+
+#define SYSCLOCK 12000000
+#define PRIORITY 8
+ 
+void setup_sci1(int baudrate)
+{
+    /* Disable serial port */
+    SCR1 = 0;
+     
+    /* Set PB11 to Tx and PB10 to Rx */
+    PBCR1 = (PBCR1 & 0xff0f) | 0xa0;
+ 
+    /* Asynchronous, 8N1, no prescaler */
+    SMR1 = 0;
+ 
+    /* Set baudrate */
+    BRR1 = SYSCLOCK / (baudrate * 32) - 1;
+ 
+    /* Clear FER and PER */
+    SSR1 &= 0xe7;
+ 
+    /* Set interrupt priority to 8 */
+    IPRE = (IPRE & 0x0fff) | (PRIORITY << 12);
+ 
+    /* Enable Rx, Tx and Rx interrupt */
+    SCR1 = 0x70;
+}
+
+
+ +

Pin configuration

+ +

Starting at 0xc40a: + +

CASCR = 0xafff: Column Address Strobe Pin Control Register. Set bits CASH MD1 and CASL MD1. + +

Port A

+
PACR1 = 0x0102: Set pin functions +
PACR2 = 0xbb98: Set pin functions +
PAIOR &= 0xfffe: PA0 is input +
PAIOR &= 0xffdf: PA5 is input +
PADR &= 0xff7f: Set pin PA7 low +
PAIOR |= 0x80: PA7 is output +
PAIOR |= 0x100: PA8 is output +
PADR |= 0x200: Set pin PA9 high +
PAIOR |= 0x200: PA9 is output +
PAIOR |= 0x400: PA10 is output +
PAIOR &= 0xf7ff: PA11 is input +
PAIOR &= 0xbfff: PA14 is input +
PAIOR = 0x7fff: PA15 is input +
PADR &= 0xfeff: Set pin PA8 low + +

Port B

+
PBCR1 = 0x12a8: Set pin functions +
PBCR2 = 0x0000: Set pin functions +
PBDR &= 0xffef: Set pin PB4 low +
PBIOR &= 0xffef: PB4 is input +
PBIOR |= 0x20: PB5 is output +
PBIOR |= 0x40: PA6 is output +
PBDR &= 0xffbf: Set pin PB6 low +
PBDR |= 0x20: Set pin PB5 high + +

ITU (Integrated Timer Pulse Unit)

+ +

Starting at 0xfcd0: + +

TSNC &= 0xfe: The timer counter for channel 0 (TCNT0) operates independently of other channels +
TMDR &= 0xfe: Channel 0 operates in normal (not PWM) mode +
GRA0 = 0x1d4c: +
TCR0 &= 0x67; TCR0 |= 0x23: TCNT is cleared by general register A (GRA) compare match or input capture. Counter clock = f/8 +
TIOR0 = 0x88: Compare disabled +
TIER0 = 0xf9: Enable interrupt requests by IMFA (IMIA) +
IPRC &= 0xff0f; IPRC |= 0x30: Set ITU0 interrupt priority level 3. +
TSTR |= 0x01: Start TCNT0 + +

Memory area #6 ?

+ +

From 0xc52a: + +

PADR |= 0x0200: Set PA13 high +
WCR1 = 0x40ff: Enable /WAIT support for memory area 6. Hmmm, what's on CS6? +
WCR1 &= 0xfdfd: Turn off RW5 (was off already) and WW1 (enable short address output cycle). +
WCR3 &= 0xe7ff: Turn off A6LW1 and A6LW0; 1 wait state for CS6. +
ICR |= 0x80: Interrupt is requested on falling edge of IRQ0 input + +

Remote control

+

Tjerk Schuringa reports: +"Finally got that extra bit going on my bitpattern generator. So far I fed only +simple characters to my jukebox, and this is the result: + +

+START D0 1 2 3 4 5 6 7 STOP FUNCTION
+0      0 0 0 0 0 1 1 1    1 VOL- (the one I got already)
+       0 0 0 0 1 0 1 1      VOL+ (figures)
+       0 0 0 1 0 0 1 1      +
+       0 0 1 0 0 0 1 1      -
+       0 1 0 0 0 0 1 1      STOP
+       1 0 0 0 0 0 1 1      PLAY
+
+ +

I also found that "repeat" functions (keep a button depressed) needs to be +faster than 0.5 s. If it is around 1 second or more it is interpreted as a +seperate keypress. So far I did not get the "fast forward" function because the +fastest I can get is 0.5 s. + +

Very important: the baudrate is indeed 9600 baud! These pulses are fed to the +second ring on the headphone jack, and (if I understood correctly) go to RxD1 +of the SH1." + +

LCD display

+ +

The Recorder uses a Shing Yih Technology G112064-30 graphic LCD display with 112x64 pixels. The controller is a Solomon SSD1815Z. + +

It's not yet known what display/controller the Jukebox has, but I'd be surprised if it doesn't use a similar controller. + +

Starting at 0xE050, the code flicks PB2 and PB3 a great deal and then some with PB1 and PB0. Which gives us the following connections: + + + + + + +
CPU pinLCD pin
PB0DC
PB1CS1
PB2SCK
PB3SDA
+ +

The Recorder apparently has the connections this way (according to Gary Czvitkovicz): + + + + + +
CPU pinLCD pin
PB0SDA
PB1SCK
PB2DC
PB3CS1
+ +

The charsets: + +

+ +

+Old LCD charset (before v4.50)
+New LCD charset (after v4.50)
+ + +

Code

+ +

This C snippet write a byte to the Jukebox LCD controller. +The 'data' flag inticates if the byte is a command byte or a data byte. + +
+
+#define DC  1
+#define CS1 2
+#define SDA 4
+#define SCK 8
+ 
+void lcd_write(int byte, int data)
+{
+   int i;
+   char on,off;
+ 
+   PBDR &= ~CS1; /* enable lcd chip select */
+ 
+   if ( data ) {
+      on=~(SDA|SCK);
+      off=SCK|DC;
+   }
+   else {
+      on=~(SDA|SCK|DC);
+      off=SCK;
+   }
+   /* clock out each bit, MSB first */
+   for (i=0x80;i;i>>=1)
+   {
+      PBDR &= on;
+      if (i & byte)
+         PBDR |= SDA;
+      PBDR |= off;
+   }
+ 
+   PBDR |= CS1; /* disable lcd chip select */
+}
+
+
+ +

Firmware size

+ +

Joachim Schiffer found out that firmware files have to be at least 51200 +bytes to be loaded by newer firmware ROMs. +So my "first program" only works on players with older firmware in ROM +(my has 3.18). Joachim posted a +padded version that works everywhere. + +#include "foot.t"