From 52ca65806930fac06216a1d2ae62861b1da39a1f Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Tue, 29 Nov 2022 22:33:56 +0000 Subject: [PATCH] x1000: Add support for DS35x1GAxxx flash chips This flash chip is found on some Surfans F20 units. For our purposes it's the same as the GD5F1GA4xExx so just #define an alias instead of adding a whole new chip struct. Change-Id: I2f4c4fbf1faf3a0c7a1503534430afacbddc426e --- firmware/target/mips/ingenic_x1000/nand-x1000.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 28e050fcef..a0efbb2cbe 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c @@ -93,11 +93,15 @@ static const struct nand_chip chip_gd5f1gq4xexx = { .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4, }; +#define chip_ds35x1gaxxx chip_gd5f1gq4xexx + const struct nand_chip_id supported_nand_chips[] = { NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12), NAND_CHIP_ID(&chip_w25n01gvxx, NAND_READID_ADDR, 0xef, 0xaa, 0x21), NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xd1), NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xc1), + NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x71), /* 3.3 V */ + NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x21), /* 1.8 V */ }; const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips);