247 lines
7.7 KiB
ArmAsm
247 lines
7.7 KiB
ArmAsm
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/*
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* init.S
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*
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* Initialization code for JzRISC.
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*
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* Author: Seeger Chin
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* e-mail: seeger.chin@gmail.com
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include "config.h"
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#include "mips.h"
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.text
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.set mips3
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.extern main
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.global _start
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#ifdef BOOTLOADER
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.section .init.text,"ax",%progbits
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#else
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.section .resetvectors,"ax",%progbits
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#endif
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.set noreorder
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.set noat
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#ifdef BOOTLOADER
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.word 0 /* HACK */
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.word 0 /* HACK */
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#endif
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_start:
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la ra, _start
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//----------------------------------------------------
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// init cp0 registers.
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//----------------------------------------------------
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mtc0 zero, C0_WATCHLO
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mtc0 zero, C0_WATCHHI
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li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
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| M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
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| M_StatusIM2 | M_StatusERL)
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// BEV = Enable Boot Exception Vectors
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// IMx = Interrupt mask
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// ERL = Denotes error level
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mtc0 t0, C0_STATUS
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li t1, M_CauseIV
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mtc0 t1, C0_CAUSE
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//----------------------------------------------------
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// init caches, assumes a 4way*128set*32byte i/d cache
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//----------------------------------------------------
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li t0, 3 // enable cache for kseg0 accesses
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mtc0 t0, C0_CONFIG // CONFIG reg
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la t0, 0x80000000 // an idx op should use a unmappable address
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ori t1, t0, 0x4000 // 16kB cache
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mtc0 zero, C0_TAGLO // TAGLO reg
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mtc0 zero, C0_TAGHI // TAGHI reg
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_init_cache_loop:
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cache 0x8, 0(t0) // index store icache tag
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cache 0x9, 0(t0) // index store dcache tag
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bne t0, t1, _init_cache_loop
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addiu t0, t0, 0x20 // 32 bytes per cache line
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nop
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//----------------------------------------------------
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// Invalidate BTB
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//----------------------------------------------------
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mfc0 t0, C0_CONFIG
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nop
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ori t0, 2
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mtc0 t0, C0_CONFIG
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nop
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//----------------------------------------------------
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// setup stack, jump to C code
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//----------------------------------------------------
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la sp, stackend
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la t0, stackbegin
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li t1, 0xDEADBEEF
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_init_stack_loop:
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sw t1, 0(t0)
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bne t0, sp, _init_stack_loop
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addiu t0, t0, 4
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la t0, main
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jr t0
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nop
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#ifndef BOOTLOADER
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.section .vectors,"ax",%progbits
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#endif
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.extern exception_handler
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.global except_common_entry
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.type except_common_entry,@function
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except_common_entry:
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la k0, exception_handler
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jr k0
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nop
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nop
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nop
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.extern _int
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.extern _exception
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.global exception_handler
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.type exception_handler,@function
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.set noreorder
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exception_handler:
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addiu sp, -0x80 # Add Immediate Unsigned
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sw ra, 0(sp) # Store Word
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sw fp, 4(sp) # Store Word
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sw gp, 8(sp) # Store Word
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sw t9, 0xC(sp) # Store Word
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sw t8, 0x10(sp) # Store Word
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sw s7, 0x14(sp) # Store Word
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sw s6, 0x18(sp) # Store Word
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sw s5, 0x1C(sp) # Store Word
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sw s4, 0x20(sp) # Store Word
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sw s3, 0x24(sp) # Store Word
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sw s2, 0x28(sp) # Store Word
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sw s1, 0x2C(sp) # Store Word
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sw s0, 0x30(sp) # Store Word
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sw t7, 0x34(sp) # Store Word
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sw t6, 0x38(sp) # Store Word
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sw t5, 0x3C(sp) # Store Word
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sw t4, 0x40(sp) # Store Word
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sw t3, 0x44(sp) # Store Word
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sw t2, 0x48(sp) # Store Word
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sw t1, 0x4C(sp) # Store Word
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sw t0, 0x50(sp) # Store Word
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sw a3, 0x54(sp) # Store Word
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sw a2, 0x58(sp) # Store Word
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sw a1, 0x5C(sp) # Store Word
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sw a0, 0x60(sp) # Store Word
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sw v1, 0x64(sp) # Store Word
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sw v0, 0x68(sp) # Store Word
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sw $1, 0x6C(sp) # Store Word
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mflo t0 # Move F LO
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nop
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sw t0, 0x70(sp) # Store Word
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mfhi t0 # Move F HI
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nop
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sw t0, 0x74(sp) # Store Word
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mfc0 t0, C0_STATUS # Status register
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sw t0, 0x78(sp) # Store Word
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mfc0 t0, C0_EPC # Exception Program Counter
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sw t0, 0x7C(sp) # Store Word
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li k1, 0x7C # Load Immediate
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mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
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and k0, k1 # AND
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beq zero, k0, _int # Branch on Equal
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nop
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la k0, _exception
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jr k0
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nop
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.global _int
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.type _int,@function
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_int:
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jal intr_handler # Jump And Link
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nop
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lw ra, 0(sp) # Load Word
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lw fp, 4(sp) # Load Word
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sw gp, 8(sp) # Store Word
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lw t9, 0xC(sp) # Load Word
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lw t8, 0x10(sp) # Load Word
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lw s7, 0x14(sp) # Load Word
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lw s6, 0x18(sp) # Load Word
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lw s5, 0x1C(sp) # Load Word
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lw s4, 0x20(sp) # Load Word
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lw s3, 0x24(sp) # Load Word
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lw s2, 0x28(sp) # Load Word
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lw s1, 0x2C(sp) # Load Word
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lw s0, 0x30(sp) # Load Word
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lw t7, 0x34(sp) # Load Word
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lw t6, 0x38(sp) # Load Word
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lw t5, 0x3C(sp) # Load Word
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lw t4, 0x40(sp) # Load Word
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lw t3, 0x44(sp) # Load Word
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lw t2, 0x48(sp) # Load Word
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lw t1, 0x4C(sp) # Load Word
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lw t0, 0x50(sp) # Load Word
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lw a3, 0x54(sp) # Load Word
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lw a2, 0x58(sp) # Load Word
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lw a1, 0x5C(sp) # Load Word
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lw a0, 0x60(sp) # Load Word
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lw v1, 0x64(sp) # Load Word
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lw v0, 0x68(sp) # Load Word
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lw v1, 0x6C(sp) # Load Word
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lw k0, 0x70(sp) # Load Word
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mtlo k0 # Move To LO
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nop
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lw k0, 0x74(sp) # Load Word
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mthi k0 # Move To HI
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nop
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lw k0, 0x78(sp) # Load Word
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nop
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mtc0 k0, C0_STATUS # Status register
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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lw k0, 0x7C(sp) # Load Word
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nop
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mtc0 k0, C0_EPC # Exception Program Counter
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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addiu sp, 0x80 # Add Immediate Unsigned
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eret # Exception Return
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nop
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.extern _except_handler
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.global _exception
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.type _exception,@function
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_exception:
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move a0, sp
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mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
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mfc0 a2, C0_EPC # Exception Program Counter
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la k0, except_handler # Load Address
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jr k0 # Jump Register
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nop
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.set reorder
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