2006-11-08 16:22:30 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Jens Arnold
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* Based on the work of Alan Korr and J<EFBFBD>rg Hohensohn
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .icode,"ax",@progbits
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.align 2
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.global lcd_write_command
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.type lcd_write_command,@function
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lcd_write_command:
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2008-01-04 23:42:38 +00:00
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move.l #~8, %d1
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and.l %d1, (MBAR2+0xb4)
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move.l (4, %sp), %d0
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move.w %d0, 0xf0000000
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2006-11-08 16:22:30 +00:00
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rts
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.wc_end:
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.size lcd_write_command,.wc_end-lcd_write_command
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.align 2
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.global lcd_write_command_ex
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.type lcd_write_command_ex,@function
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lcd_write_command_ex:
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2008-01-04 23:42:38 +00:00
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lea.l 0xf0000000, %a0
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lea.l MBAR2+0xb4, %a1
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2006-11-08 16:22:30 +00:00
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2008-01-04 23:42:38 +00:00
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move.l #~8, %d1 /* Set A0 = 0 */
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and.l %d1, (%a1)
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2006-11-08 16:22:30 +00:00
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2008-01-04 23:42:38 +00:00
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move.l (4, %sp), %d0 /* Command */
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move.w %d0, (%a0) /* Write to LCD */
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2006-11-08 16:22:30 +00:00
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2008-01-04 23:42:38 +00:00
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not.l %d1 /* Set A0 = 1 */
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or.l %d1, (%a1)
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2006-11-08 16:22:30 +00:00
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2008-01-04 23:42:38 +00:00
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move.l (8, %sp), %d0 /* Data */
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cmp.l #-1, %d0 /* -1? */
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2006-11-08 16:22:30 +00:00
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beq.b .last
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2008-01-04 23:42:38 +00:00
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move.w %d0, (%a0) /* Write to LCD */
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2006-11-08 16:22:30 +00:00
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2008-01-04 23:42:38 +00:00
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move.l (12, %sp), %d0 /* Data */
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cmp.l #-1, %d0 /* -1? */
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2006-11-08 16:22:30 +00:00
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beq.b .last
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2008-01-04 23:42:38 +00:00
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move.w %d0, (%a0) /* Write to LCD */
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2006-11-08 16:22:30 +00:00
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.last:
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rts
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.wcex_end:
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.size lcd_write_command_ex,.wcex_end-lcd_write_command_ex
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.align 2
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.global lcd_write_data
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.type lcd_write_data,@function
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lcd_write_data:
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2008-01-04 23:42:38 +00:00
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movem.l (4, %sp), %a0-%a1 /* Data pointer */
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move.l %a1, %d0 /* Length */
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moveq #8, %d1
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or.l %d1, (MBAR2+0xb4)
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lea.l 0xf0000000, %a1
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2006-11-08 16:22:30 +00:00
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.loop:
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2007-10-15 21:16:50 +00:00
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/* When running in IRAM, this loop takes 10 cycles plus the LCD write.
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The 10 cycles are necessary to follow the LCD timing specs
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2006-11-08 16:22:30 +00:00
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at 140MHz */
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2008-01-04 23:42:38 +00:00
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nop /* 3(0/0) */
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move.b (%a0)+, %d1 /* 3(1/0) */
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move.w %d1, (%a1) /* 1(0/1) */
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subq.l #1, %d0 /* 1(0/0) */
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bne .loop /* 2(0/0) */
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2006-11-08 16:22:30 +00:00
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rts
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.wd_end:
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.size lcd_write_data,.wd_end-lcd_write_data
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2008-01-04 23:42:38 +00:00
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.align 2
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.global lcd_grey_data
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.type lcd_grey_data,@function
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2008-01-15 00:51:58 +00:00
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/* The main loop assumes the buffers are in SDRAM. Otherwise the LCD
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* controller timing won't be met at 124 MHz and graphical glitches
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* will occur. */
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2008-01-04 23:42:38 +00:00
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lcd_grey_data:
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2008-01-15 00:51:58 +00:00
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lea.l (-10*4, %sp), %sp
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movem.l %d2-%d6/%a2-%a6, (%sp) /* free some registers */
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movem.l (10*4+4, %sp), %a0-%a2 /* values, phases, length */
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2008-01-09 23:48:26 +00:00
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lea.l (%a1, %a2.l*4), %a2 /* end address */
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2008-01-04 23:42:38 +00:00
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moveq #8, %d1
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or.l %d1, (MBAR2+0xb4) /* A0 = 1 (data) */
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2008-01-09 23:48:26 +00:00
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lea 0xf0000000, %a3 /* LCD data port */
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moveq.l #15, %d3
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add.l %a1, %d3
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and.l #0xfffffff0, %d3 /* first line bound */
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move.l %a2, %d1
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and.l #0xfffffff0, %d1 /* last line bound */
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cmp.l %d3, %d1
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bls.w .g_tloop /* no lines to copy - jump to tail loop */
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cmp.l %a1, %d0
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bls.s .g_lloop /* no head blocks - jump to line loop */
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.g_hloop:
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move.l (%a1), %d2 /* fetch 4 pixel phases */
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bclr.l #31, %d2 /* Z = !(p0 & 0x80); p0 &= ~0x80; */
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seq.b %d0 /* %d0 = ........................00000000 */
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lsl.l #2, %d0 /* %d0 = ......................00000000.. */
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bclr.l #23, %d2 /* Z = !(p1 & 0x80); p1 &= ~0x80; */
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seq.b %d0 /* %d0 = ......................0011111111 */
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lsl.l #2, %d0 /* %d0 = ....................0011111111.. */
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bclr.l #15, %d2 /* Z = !(p2 & 0x80); p2 &= ~0x80; */
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seq.b %d0 /* %d0 = ....................001122222222 */
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lsl.l #2, %d0 /* %d0 = ..................001122222222.. */
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bclr.l #7, %d2 /* Z = !(p3 & 0x80); p3 &= ~0x80; */
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seq.b %d0 /* %d0 = ..................00112233333333 */
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lsr.l #6, %d0 /* %d0 = ........................00112233 */
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move.w %d0, (%a3) /* write pixel block */
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add.l (%a0)+, %d2 /* add 4 pixel values to the phases */
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move.l %d2, (%a1)+ /* store new phases, advance pointer */
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cmp.l %a1, %d3 /* go up to first line bound */
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bhi.s .g_hloop
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.g_lloop:
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2008-01-15 00:51:58 +00:00
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movem.l (%a1), %d2-%d5 /* fetch 4 blocks of 4 pixel phases each */
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2008-01-04 23:42:38 +00:00
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2008-01-15 00:51:58 +00:00
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bclr.l #31, %d2 /* calculate first pixel block */
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2008-01-09 23:48:26 +00:00
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #23, %d2
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #15, %d2
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #7, %d2
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seq.b %d0
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lsr.l #6, %d0
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2008-01-15 00:51:58 +00:00
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move.w %d0, (%a3) /* write first block to LCD */
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bclr.l #31, %d3 /* calculate second pixel block */
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seq.b %d6
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lsl.l #2, %d6
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2008-01-09 23:48:26 +00:00
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bclr.l #23, %d3
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2008-01-15 00:51:58 +00:00
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seq.b %d6
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lsl.l #2, %d6
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2008-01-09 23:48:26 +00:00
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bclr.l #15, %d3
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2008-01-15 00:51:58 +00:00
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seq.b %d6
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lsl.l #2, %d6
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2008-01-09 23:48:26 +00:00
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bclr.l #7, %d3
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2008-01-15 00:51:58 +00:00
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seq.b %d6
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lsr.l #6, %d6
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bclr.l #31, %d4 /* calculate third pixel block */
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2008-01-09 23:48:26 +00:00
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #23, %d4
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #15, %d4
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #7, %d4
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seq.b %d0
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lsr.l #6, %d0
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2008-01-15 00:51:58 +00:00
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move.w %d6, (%a3) /* write second block to LCD */
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movem.l (%a0), %d6/%a4-%a6 /* fetch 4 blocks of 4 pixel values each */
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lea.l (16, %a0), %a0
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move.w %d0, (%a3) /* write third block to LCD */
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bclr.l #31, %d5 /* calculate fourth pixel block */
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2008-01-09 23:48:26 +00:00
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #23, %d5
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #15, %d5
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #7, %d5
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seq.b %d0
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lsr.l #6, %d0
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2008-01-15 00:51:58 +00:00
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add.l %d6, %d2 /* calculate 4*4 new pixel phases */
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add.l %a4, %d3 /* (packed addition) */
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2008-01-09 23:48:26 +00:00
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add.l %a5, %d4
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add.l %a6, %d5
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2008-01-15 00:51:58 +00:00
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movem.l %d2-%d5, (%a1) /* store 4*4 new pixel phases */
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2008-01-09 23:48:26 +00:00
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lea.l (16, %a1), %a1
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2008-01-15 00:51:58 +00:00
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move.w %d0, (%a3) /* write fourth block to LCD */
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2008-01-09 23:48:26 +00:00
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cmp.l %a1, %d1 /* go up to last line bound */
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bhi.w .g_lloop
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cmp.l %a1, %a2
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bls.s .g_no_tail
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.g_tloop:
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move.l (%a1), %d2
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bclr.l #31, %d2
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #23, %d2
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #15, %d2
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seq.b %d0
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lsl.l #2, %d0
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bclr.l #7, %d2
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seq.b %d0
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lsr.l #6, %d0
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move.w %d0, (%a3)
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add.l (%a0)+, %d2
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move.l %d2, (%a1)+
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cmp.l %a1, %a2 /* go up to end address */
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bhi.s .g_tloop
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.g_no_tail:
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2008-01-15 00:51:58 +00:00
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movem.l (%sp), %d2-%d6/%a2-%a6 /* restore registers */
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lea.l (10*4, %sp), %sp
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2008-01-04 23:42:38 +00:00
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rts
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2008-01-09 23:48:26 +00:00
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2008-01-04 23:42:38 +00:00
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.gd_end:
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.size lcd_grey_data,.gd_end-lcd_grey_data
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