113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "timer.h"
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#include "clkctl-imx31.h"
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#include "avic-imx31.h"
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static void __attribute__((interrupt("IRQ"))) EPIT2_HANDLER(void)
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{
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EPITSR2 = EPITSR_OCIF; /* Clear the pending status */
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if (pfn_timer != NULL)
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pfn_timer();
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}
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static void stop_timer(bool clock_off)
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{
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/* Ensure clock gating on (before touching any module registers) */
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imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_ON_ALL);
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/* Disable insterrupt */
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avic_disable_int(EPIT2);
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/* Clear wakeup mask */
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CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT2;
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/* Disable counter */
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EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN);
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/* Clear pending */
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EPITSR2 = EPITSR_OCIF;
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if (clock_off)
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{
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/* Final stop, not reset; don't clock module any longer */
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imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_OFF);
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}
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}
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bool _timer_set(long cycles, bool start)
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{
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/* Maximum cycle count expressible in the cycles parameter is 2^31-1
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* and the modulus counter is capable of 2^32-1 and as a result there is
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* no requirement to use a prescaler > 1. This gives a frequency range of
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* ~0.015366822Hz - 66000000Hz. The highest input frequency gives the
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* greatest possible accuracy anyway. */
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* Halt timer if running - leave module clock enabled */
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stop_timer(false);
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if (start && pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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/* CLKSRC = ipg_clk,
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* EPIT output disconnected,
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* Enabled in wait mode
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* Prescale 1 for 66MHz
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* Reload from modulus register,
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* Count from load value */
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EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
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EPITCR_PRESCALER(1-1) | EPITCR_RLD | EPITCR_ENMOD;
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EPITLR2 = cycles;
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/* Event when counter reaches 0 */
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EPITCMPR2 = 0;
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restore_interrupt(oldstatus);
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return true;
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}
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bool _timer_register(void)
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{
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* Halt timer if running - leave module clock enabled */
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stop_timer(false);
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/* Enable interrupt */
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EPITCR2 |= EPITCR_OCIEN;
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avic_enable_int(EPIT2, IRQ, 8, EPIT2_HANDLER);
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/* Start timer */
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EPITCR2 |= EPITCR_EN;
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restore_interrupt(oldstatus);
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return true;
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}
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void _timer_unregister(void)
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{
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* Halt timer if running - stop module clock */
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stop_timer(true);
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restore_interrupt(oldstatus);
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}
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